TI MSP430F4260IRGZT Mixed signal microcontroller Datasheet

 SLAS455C − MARCH 2005 − REVISED AUGUST 2005
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
Active Mode: 250 µA at 1 MHz, 2.2 V
Standby Mode: 1.1 µA
Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Sigma-Delta A/D Converter With
Internal Reference and Five Differential
Analog Inputs
12-Bit D/A Converter
16-Bit Timer_A With Three
Capture/Compare Registers
Brownout Detector
Bootstrap Loader
D Serial Onboard Programming,
D
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Integrated LCD Driver with Contrast
Control for Up to 56 Segments
MSP430x42x0 Family Members Include:
MSP430F4250: 16KB+256B Flash Memory
256B RAM
MSP430F4260: 24KB+256B Flash Memory
256B RAM
MSP430F4270: 32KB+256B Flash Memory
256B RAM
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
For Additional Device Information, See The
MSP430F42x0 Device Erratasheet,
Literature Number SLAZ022
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430F42x0 is a microcontroller configuration with a 16-bit timer, a high performance 16-bit sigma-delta
A/D converter, 12-bit D/A converter, 32 I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C
−40
C to 85
85°C
C
PLASTIC 48-PIN SSOP
(DL)
PLASTIC 48-PIN QFN
(RGZ)
MSP430F4250IDL
MSP430F4250IRGZ
MSP430F4260IDL
MSP430F4260IRGZ
MSP430F4270IDL
MSP430F4270IRGZ
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
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pin designation, MSP430F42x0
DL PACKAGE
(TOP VIEW)
TDO/TDI
TDI/TCLK
TMS
TCK
RST/NMI
DVCC
DVSS
XIN
XOUT
AVSS
AVCC
VREF
P6.0/A0+
P6.1/A0−
P6.2/A1+
P6.3/A1−
P6.4
P6.5
P6.6
P6.7
P1.7/A2+
P1.6/A2−
P1.5/TACLK/ACLK/A3+
P1.4/A3−/DAC0
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSP430F42x0IDL
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.0/S13
P2.1/S12
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
S5
P5.7/S4
P5.6/S3
P5.5/S2
P5.0/S1
P5.1/S0
LCDCAP/R23
LCDREF/R13
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/A4−
P1.3/TA2/A4+
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pin designation, MSP430F42x0 (continued)
47 46 45 44 43 42 41 40 39 38
P2.1/S12
P2.0/S13
COM0
P5.2/COM1
P5.3/COM2
P5.4/COM3
TDO/TDI
TDI/TCLK
TMS
TCK
RST/NMI
DVCC
RGZ PACKAGE
(TOP VIEW)
P2.2/S11
2
35
P2.3/S10
XOUT
3
34
P2.4/S9
AVSS
4
33
P2.5/S8
AVCC
5
32
P2.6/S7
VREF
6
31
P2.7/S6
P6.0/A0+
7
30
S5
P6.1/A0−
8
29
P5.7/S4
P6.2/A1+
9
28
P5.6/S3
P6.3/A1−
10
27
P5.5/S2
P6.4
11
26
P5.0/S1
P6.5
12
25
P5.1/S0
MSP430F42x0IRGZ
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LCDREF/R13
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/A4−
P1.3/TA2/A4+
P1.4/A3−/DAC0
P1.5/TACLK/ACLK/A3+
P1.6/A2−
P1.7/A2+
14 15 16 17 18 19 20 21 22 23
P6.7
XIN
P6.6
1
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LCDCAP/R23
36
DVSS
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MSP430F42x0 functional block diagram
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
Oscillator
FLL+
ACLK
32KB Flash
24KB Flash
SMCLK 16KB Flash
256B RAM
SD16_A
DAC12
16-Bit
12-Bit
1 Channel
Voltage out
P5
P2
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P6
8
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
Watchdog
Timer+
Timer_A3
POR
Brownout
Basic
Timer 1
3 CC Reg
1 Interrupt
Vector
15/16-Bit
TDO/TDI
LCD_A
56
Segments
1,2,3,4 MUX
fLCD
4
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MSP430F42x0 Terminal Functions
TERMINAL
NAME
DESCRIPTION
DL
NO.
RGZ
NO.
I/O
TDO/TDI
1
43
I/O
TDI/TCLK
2
44
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
3
45
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
4
46
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
5
47
I
General-purpose digital I/O / reset input or nonmaskable interrupt input port
DVCC
6
48
DVSS
7
1
XIN
8
2
I
Input terminal of crystal oscillator XT1
XOUT
9
3
O
Output terminal of crystal oscillator XT1
AVSS
AVCC
10
4
11
5
VREF
P6.0/A0+
12
6
I/O
Analog reference voltage
13
7
I/O
General-purpose digital I/O / analog input A0+
P6.1/A0−
14
8
I/O
General-purpose digital I/O / analog input A0−
P6.2/A1+
15
9
I/O
General-purpose digital I/O / analog input A1+
P6.3/A1−
16
10
I/O
General-purpose digital I/O / analog input A1−
P6.4
17
11
I/O
General-purpose digital I/O
P6.5
18
12
I/O
General-purpose digital I/O
P6.6
19
13
I/O
General-purpose digital I/O
P6.7
20
14
I/O
General-purpose digital I/O
P1.7/A2+
21
15
I/O
General-purpose digital I/O / analog input A2+
P1.6/A2−
22
16
I/O
General-purpose digital I/O / analog input A2−
P1.5/TACLK/ACLK/A3+
23
17
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8) / analog input A3+
P1.4/A3−/DAC0
24
18
I/O
General-purpose digital I/O / analog input A3− / DAC12 output
P1.3/TA2/A4+
25
19
I/O
General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output /
analog input A4+
P1.2/TA1/A4−
26
20
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output /
analog input A4−
P1.1/TA0/MCLK
27
21
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an
input on this pin / BSL Receive
P1.0/TA0
28
22
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
Transmit
LCDREF/R13
29
23
External LCD reference voltage input / input port of third most positive analog LCD level (V4
or V3)
LCDCAP/R23
30
24
Capacitor connection for LCD charge pump /
input port of second most positive analog LCD level (V2)
P5.1/S0
31
25
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
32
26
I/O
General-purpose digital I/O / LCD segment output 1
P5.5/S2
33
27
I/O
General-purpose digital I/O / LCD segment output 2
P5.6/S3
34
28
I/O
General-purpose digital I/O / LCD segment output 3
P5.7/S4
35
29
I/O
General-purpose digital I/O / LCD segment output 4
S5
36
30
O
LCD segment output 5
P2.7/S6
37
31
I/O
General-purpose digital I/O / LCD segment output 6
P2.6/S7
38
32
I/O
General-purpose digital I/O / LCD segment output 7
Test data output port. TDO/TDI data output or programming data input terminal
Digital supply voltage, positive terminal
Digital supply voltage, negative terminal
Analog supply voltage, negative terminal
Analog supply voltage, positive terminal
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MSP430F42x0 Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
DL
NO.
RGZ
NO.
I/O
P2.7/S6
37
31
I/O
General-purpose digital I/O / LCD segment output 6
P2.6/S7
38
32
I/O
General-purpose digital I/O / LCD segment output 7
P2.5/S8
39
33
I/O
General-purpose digital I/O / LCD segment output 8
P2.4/S9
40
34
I/O
General-purpose digital I/O / LCD segment output 9
P2.3/S10
41
35
I/O
General-purpose digital I/O / LCD segment output 10
P2.2/S11
42
36
I/O
General-purpose digital I/O / LCD segment output 11
P2.1/S12
43
37
I/O
General-purpose digital I/O / LCD segment output 12
P2.0/S13
44
38
I/O
General-purpose digital I/O / LCD segment output 13
COM0
45
39
O
Common output, COM0−3 are used for LCD backplanes.
P5.2/COM1
46
40
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2
47
41
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3
48
42
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
QFN Pad
NA
None
NA
QFN package pad connection to DVSS recommended.
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
OPERATION
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) —> M(TONI)
Absolute
F F
MOV & MEM, & TCDAT
M(MEM) —> M(TCDAT)
R10
—> R11
M(2+R5)—> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) —> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) —> R11
R10 + 2—> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
—> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control remains active
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control is disabled
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
8
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430F42x0 Configuration
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
15, highest
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
SD16_A
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
Watchdog Timer
WDTIFG
Maskable
0FFF6h
11
0FFF4h
10
0FFF2h
9
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
DAC12
DAC12_0IFG
(see Note 2)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh).
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special function registers
The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable registers 1 and 2
7
Address
6
0h
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
7
6
5
WDTIE
rw–0
WDTIE:
Address
0
4
3
2
1
0
4
3
2
1
0
BTIE
01h
rw–0
BTIE:
Basic timer interrupt enable
interrupt flag registers 1 and 2
7
Address
6
5
02h
NMIIFG
OFIFG
rw–0
rw–1
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
7
Address
03h
6
5
4
3
BTIFG
rw–0
BTIFG:
10
WDTIFG
Basic timer flag
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2
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module enable registers 1 and 2
Address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
04h
Address
05h
Legend: rw:
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430F4250
MSP430F4260
MSP430F4270
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
DL Package Pins
RGZ Package Pins
Data Transmit
28 − P1.0
22 − P1.0
Data Receive
27 − P1.1
21 − P1.1
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n†
Segment A
Information
Memory
Segment B
12
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature
Number SLAU056.
oscillator and system clock
The clock system in the MSP430F42x0 family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However,
VCC may not have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not
changed until VCC reaches VCC(min).
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P5 and P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
DL
RGZ
Device Input
Signal
Module
Input Name
23 - P1.5
17 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
23 - P1.5
17 - P1.5
TACLK
INCLK
28 - P1.0
22 - P1.0
TA0
CCI0A
27 - P1.1
21 - P1.1
TA0
CCI0B
DVSS
DVCC
GND
26 - P1.2
20 - P1.2
TA1
VCC
CCI1A
26 - P1.2
20 - P1.2
TA1
CCI1B
DVSS
DVCC
GND
25 - P1.3
19 - P1.3
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module
Block
Module Output
Signal
Timer
NA
CCR0
CCR1
CCR2
Output Pin Number
DL
RGZ
28 - P1.0
22 - P1.0
26 - P1.2
20 - P1.2
25 - P1.3
19 - P1.3
TA0
TA1
TA2
VCC
SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode.
14
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peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_A3
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
General Control
SD16CTL
0100h
Channel 0 Control
SD16CCTL0
0102h
Interrupt vector word register
SD16IV
0110h
Channel 0 conversion memory
SD16MEM0
0112h
Flash
DAC12
SD16_A
(see also:
Peripherals with
Byte Access)
PERIPHERALS WITH BYTE ACCESS
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 Input Control
SD16INCTL0
0B0h
Analog Enable
SD16AE
0B7h
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDACTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
FLL+Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Basic Timer1
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P6
Port P5
Port P2
Port P1
Special functions
16
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC)
1.8
3.6
V
Supply voltage during flash memory programming,
VCC (AVCC = DVCC = VCC)
2.5
3.6
V
0
0
V
−40
85
°C
Supply voltage, VSS (AVSS = DVSS = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 1)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
32.768
Ceramic resonator
XT2 crystal frequency, f(XT2)
Crystal
VCC = 1.8 V
VCC = 3.6 V
Processor frequency (signal MCLK), f(System)
kHz
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
8
kHz
MHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
MSP430F42x0, during
program execution
4.15 MHz
1.8
3
2.5
Supply Voltage − V
Supply voltage range, MSP430F42x0,
during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, typical characteristic
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SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
TA = −40°C to 85°C
I(LPM0)
Low-power mode, (LPM0)
(see Note 1)
TA = −40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)
TA = −40°C to 85°C
I(AM)
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
(static mode ; fLCD = f(ACLK)/32)
(see Note 2 and Note 3)
I(LPM3)
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1 (see Note 2)
NOM
MAX
VCC = 2.2 V
250
370
VCC = 3 V
400
520
55
70
95
110
VCC = 2.2 V
11
14
VCC = 3 V
17
22
1.0
2.0
1.1
2.0
2.0
3.0
3.5
6.0
1.8
2.8
1.6
2.7
2.5
3.5
4.2
7.5
TA = −40°C
2.5
3.5
TA = 25°C
2.5
3.5
TA = 85°C
3.8
6.0
TA = −40°C
2.9
4.0
2.9
4.0
TA = 85°C
4.4
7.5
TA = −40°C
TA = 25°C
0.1
0.5
0.1
0.5
0.7
1.1
1.7
3.0
0.1
0.8
0.1
0.8
0.8
1.2
1.9
3.5
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
UNIT
A
µA
VCC = 2.2 V
VCC = 3 V
TA = 60°C
TA = 85°C
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
(4-mux mode; fLCD = f(ACLK)/32)
(see Note 2 and Note 3)
MIN
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
µA
A
µA
A
µA
A
µA
A
µA
A
NOTES: 1. Timer_A is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9pF) crystal and OSCCAPx=01h.
Current consumption of active mode versus system frequency, F-version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version:
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
18
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.55
1.5
1.98
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.9
1.3
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t(cap)
Timer_A capture timing
TA0, TA1, TA2
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK: t(H) = t(L)
f(TAint)
Timer_A, clock frequency
SMCLK or ACLK signal selected
VCC
2.2 V
MIN
TYP
MAX
UNIT
62
3V
50
2.2 V
62
3V
50
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1, P2, P5, and P6 (see Note 1)
PARAMETER
Ilkg(Px.y)
Leakage
current
TEST CONDITIONS
Port Px
V(Px.y) (see Note 2)
MIN
TYP
VCC = 2.2 V/3 V
MAX
UNIT
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
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SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P5, and P6
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
See Note 2
See Note 2
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
f(Px.y)
(x = 1, 2, 5, 6; 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ±1.5 mA
f(MCLK)
P1.1/TA0/MCLK
CL = 20 pF
t(Xdc)
20
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
POST OFFICE BOX 655303
MIN
TYP
MAX
UNIT
VCC = 2.2 V / 3 V
DC
fSystem
MHz
40%
fSystem
60%
MHz
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
• DALLAS, TEXAS 75265
50%−
15 ns
50%
50%+
15 ns
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.0
I OL − Typical Low-level Output Current − mA
I OL − Typical Low-level Output Current − mA
30
TA = −40°C
25
TA = 25°C
20
TA = 85°C
15
10
5
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P1.0
45
TA = −40°C
40
TA = 25°C
35
TA = 85°C
30
25
20
15
10
5
0
0.0
2.5
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
2.5
3.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 2.2 V
P1.0
I OH− Typical High-level Output Current − mA
I OH− Typical High-level Output Current − mA
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−5
−10
−15
TA = 85°C
TA = 25°C
−20
−25
0.0
1.5
VOL − Low-Level Output Voltage − V
TA = −40°C
0.5
1.0
1.5
2.0
2.5
VOH − High-Level Output Voltage − V
−5
VCC = 3 V
P1.0
−10
−15
−20
−25
−30
−35
TA = 85°C
TA = 25°C
−40
−45
−50
0.0
TA = −40°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 4
Figure 5
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21
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD_A
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(LCD)
Supply Voltage Range
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
2.2
CLCD
Capacitor on LCDCAP (see Note 1)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
4.7
ICC(LCD)
Average Supply Current (see Note 2)
VLCD(typ)=3V; LCDCPEN = 1;
VLCDx= 1000, all segments on
fLCD= fACLK/32
no LCD connected (see Note 3)
TA = 25°C
fLCD
VLCD
LCD frequency
LCD voltage
VLCDx = 0000
VCC
V
VLCD
VLCD
LCD voltage
VLCDx = 0001
2.60
V
LCD voltage
VLCDx = 0010
2.66
V
VLCD
VLCD
LCD voltage
VLCDx = 0011
2.72
V
LCD voltage
VLCDx = 0100
2.78
V
VLCD
VLCD
LCD voltage
VLCDx = 0101
2.84
V
LCD voltage
VLCDx = 0110
2.90
V
VLCD
VLCD
LCD voltage
VLCDx = 0111
2.96
V
LCD voltage
VLCDx = 1000
3.02
V
VLCD
VLCD
LCD voltage
VLCDx = 1001
3.08
V
LCD voltage
VLCDx = 1010
3.14
V
VLCD
VLCD
LCD voltage
VLCDx = 1011
3.20
V
LCD voltage
VLCDx = 1100
3.26
V
VLCD
VLCD
LCD voltage
VLCDx = 1101
3.32
V
LCD voltage
VLCDx = 1110
3.38
VLCD
LCD voltage
VLCDx = 1111
3.44
RLCD
LCD Driver Output impedance
VLCD = 3V; LCDCPEN = 1;
VLCDx = 1000, ILOAD = ±10µA
2.2 V
3.6
µF
µA
3.8
1.1
2.2 V
V
kHz
V
3.60
V
10
kΩ
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
3. Connecting an actual display will increase the current consumption depending on the size of the LCD.
22
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
td(BOR)
VCC(start)
V(B_IT−)
Vhys(B_IT−)
MIN
dVCC/dt ≤ 3 V/s (see Figure 6)
MAX
UNIT
2000
µs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 6 through Figure 8)
dVCC/dt ≤ 3 V/s (see Figure 6)
Brownout
(see Note 2)
TYP
70
130
V
1.71
V
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.
t(reset)
typical characteristics
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303
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23
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics (continued)
VCC
3V
2
VCC(min)− V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 7. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC(min)− V
2
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 8. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
24
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SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
f(DCOCLK)
TEST CONDITIONS
VCC
2.2 V/3 V
MIN
TYP
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
TAP = 27
1.07
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
f(DCO2)
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 10 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0, (see Note 2)
DV
Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 (see Note 2)
MAX
1
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.11
1.17
%/_C
%/V
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
85
TA − °C
Figure 9. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
POST OFFICE BOX 655303
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SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 10. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 11. Five Overlapping DCO Ranges Controlled by FN_x Bits
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
Integrated input capacitance
(see Note 4)
Integrated output capacitance
(see Note 4)
TEST CONDITIONS
MIN
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
18
OSCCAPx = 0h, VCC = 2.2 V / 3 V
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
VIL
VIH
Input levels at XIN
TYP
OSCCAPx = 0h, VCC = 2.2 V / 3 V
VCC = 2.2 V/3 V (see Note 3)
MAX
UNIT
pF
pF
18
VSS
0.8×VCC
0.2×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’F42x0 and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or
resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER
AVCC
ISD16
fSD16
Analog supply
voltage
Analog supply
current including
internal reference
Analog front-end
input clock
frequency
TEST CONDITIONS
VCC
MIN
AVCC = DVCC
AVSS = DVSS = 0V
TYP
MAX
2.5
3.6
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
SD16BUFx = 00; GAIN: 1,2
3V
650
950
SD16BUFx = 00; GAIN: 4,8,16
3V
730
1100
SD16BUFx = 00; GAIN: 32
3V
1050
1550
SD16LP = 1,
fSD16 = 0.5 MHz,
SD16OSR = 256
SD16BUFx = 00; GAIN: 1
3V
620
930
SD16BUFx = 00; GAIN: 32
3V
700
1060
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
SD16BUFx = 01; GAIN: 1
3V
850
SD16BUFx = 10; GAIN: 1
3V
1130
SD16BUFx = 11; GAIN: 1
3V
1130
SD16LP = 0 (Low power mode disabled)
3V
0.03
1
SD16LP = 1 (Low power mode enabled)
3V
0.03
0.5
UNIT
V
µA
A
1.1
MHz
SD16_A, input range
PARAMETER
VID,FSR
VID
Differential full scale
input voltage range
Differential input
voltage range for
specified
performance
(see Note 1)
TEST CONDITIONS
VCC
Bipolar Mode, SD16UNI = 0
Unipolar Mode, SD16UNI = 1
SD16REFON=1
MIN
TYP
−VREF/2GAIN
0
SD16GAINx = 1
±500
SD16GAINx = 2
±250
SD16GAINx = 4
±125
SD16GAINx = 8
±62
SD16GAINx = 16
±31
ZI
ZID
Input impedance
(one input pin
to AVSS)
Differential
Input impedance
(IN+ to IN−)
fSD16 = 1MHz,
SD16BUFx = 01
fSD16 = 1MHz,
SD16BUFx = 00
fSD16 = 1MHz,
SD16BUFx > 00
UNIT
mV
mV
mV
±15
SD16GAINx = 32
fSD16 = 1MHz,
SD16BUFx = 00
MAX
+VREF/2GAIN
+VREF/2GAIN
SD16GAINx = 1
3V
200
SD16GAINx = 32
3V
75
SD16GAINx = 1
3V
>10
SD16GAINx = 1
3V
300
400
SD16GAINx = 32
3V
100
150
SD16GAINx = 1
3V
kΩ
MΩ
kΩ
>10
MΩ
Absolute input
voltage range
SD16BUFx = 00
VI
AVSS -0.1V
AVCC
SD16BUFx > 00
AVSS
AVCC −1.2V
Common-mode
input voltage range
SD16BUFx = 00
VIC
AVSS -0.1V
AVCC
SD16BUFx > 00
AVSS
AVCC −1.2V
V
V
NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR−.
28
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• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01)
PARAMETER
TEST CONDITIONS
VCC
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 256
MIN
TYP
3V
84
3V
84
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 1024
3V
84
Nominal Gain
SD16GAINx = 1; SD16OSRx = 1024
3V
dG/dT
Gain Temperature
Drift
SD16GAINx = 1; SD16OSRx = 1024 (see Note 1)
3V
dG/dVCC
Gain Supply
Voltage Drift
SD16GAINx = 1; SD16OSRx = 1024; VCC = 2.5V - 3.6V
(see Note 2)
SINAD
Signal-to-Noise +
Distortion Ratio
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 512
fIN = 2.8Hz
0.97
1.00
MAX
UNIT
dB
1.02
15
ppm/_C
0.35
%/V
NOTES: 1. Calculated using the box method: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85C − (−40_C))
2. Calculated using the box method: (MAX(2.5...3.6V) − MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V − 2.5V)
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
SINAD
G
Signal-to-Noise +
Distortion Ratio
Nominal Gain
(see Note 1)
SD16GAINx = 1,Signal Amplitude = 500mV
TEST CONDITIONS
VCC
3V
SD16GAINx = 2,Signal Amplitude = 250mV
MIN
TYP
MAX
83.5
85
3V
81.5
84
3V
76
79.5
3V
73
76.5
SD16GAINx = 16,Signal Amplitude = 31mV
3V
69
73
SD16GAINx = 32,Signal Amplitude = 15mV
3V
62
69
SD16GAINx = 1
3V
0.97
1.00
1.02
SD16GAINx = 2
3V
1.90
1.96
2.02
SD16GAINx = 4
3V
3.76
3.86
3.96
SD16GAINx = 8
3V
7.36
7.62
7.84
SD16GAINx = 16
3V
14.56
15.04
15.52
SD16GAINx = 32
3V
27.20
28.35
29.76
3V
±0.2
±1.5
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
fIN = 50Hz,
100Hz
dB
EOS
Offset Error
(see Note 1)
SD16GAINx = 1
SD16GAINx = 32
3V
Offset Error Temperature Coefficient
(see Note 1)
SD16GAINx = 1
3V
±4
±20
dEOS/dT
SD16GAINx = 32
3V
±20
±100
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
3V
>90
CMRR
Common-Mode
Rejection Ratio
SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
3V
>75
SD16GAINx = 1
3V
>80
PSRR
Power Supply
Rejection Ratio
UNIT
%FSR
ppm
FSR/_C
dB
dB
NOTES: 1. Not production tested, limits characterized.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, temperature sensor
PARAMETER
TEST CONDITIONS
VCC
MIN
TCSensor
Sensor temperature
coefficient
See Note 1
1.18
VOffset,sensor
Sensor offset voltage
See Note 1
−100
VSensor
Sensor output voltage
(see Note 3)
TYP
1.32
MAX
UNIT
1.46
mV/K
100
mV
Temperature sensor voltage at TA = 85°C
3V
435
475
515
Temperature sensor voltage at TA = 25°C
3V
355
395
435
Temperature sensor voltage at TA = 0°C (see Note 1)
3V
320
360
400
mV
NOTES: 1. Not production tested, limits characterized.
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV]
3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
SD16_A, built-in voltage reference
PARAMETER
TEST CONDITIONS
VCC
VREF
Internal reference
voltage
SD16REFON = 1, SD16VMIDON = 0
3V
IREF
Reference supply
current
SD16REFON = 1, SD16VMIDON = 0
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0
CREF
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
ILOAD
VREF load capacitance
VREF(I) maximum load
current
tON
PSRR
MIN
1.14
TYP
MAX
UNIT
1.20
1.26
V
3V
175
260
µA
3V
18
50
ppm/K
100
nF
±200
SD16REFON = 1; SD16VMIDON = 0
3V
nA
Turn on time
SD16REFON = 0−>1; SD16VMIDON = 0;
CREF = 100nF
3V
5
ms
Line regulation
SD16REFON = 1; SD16VMIDON = 0
3V
10
uV/V
NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VREF,BUF
Reference buffer output
voltage
SD16REFON = 1, SD16VMIDON = 1
3V
1.2
IREF,BUF
Reference Supply +
Reference output buffer
quiescent current
SD16REFON = 1, SD16VMIDON = 1
3V
385
CREF(O)
Required load
capacitance on VREF
SD16REFON = 1, SD16VMIDON = 1
ILOAD,Max
Maximum load current
on VREF
SD16REFON = 1, SD16VMIDON = 1
3V
Maximum voltage variation vs. load current
|ILOAD| = 0 to 1mA
3V
Turn on time
SD16REFON = 0−>1; SD16VMIDON = 1;
CREF = 470nF
3V
tON
MAX
UNIT
V
600
470
µA
nF
−15
±1
mA
+15
mV
µs
100
SD16_A, external reference input
PARAMETER
VREF(I)
IREF(I)
30
Input voltage range
SD16REFON = 0
TEST CONDITIONS
VCC
3V
Input current
SD16REFON = 0
3V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
V
50
nA
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, supply specifications
PARAMETER
AVCC
IDD
PSRR
Analog supply voltage
Supply Current
(see Notes 1 and 2)
Power supply
rejection ratio
(see Notes 3 and 4)
TEST CONDITIONS
VCC
AVCC = DVCC,
AVSS = DVSS =0 V
MIN
TYP
2.20
MAX
UNIT
3.60
V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
50
110
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h, VREF,DAC12 = AVCC
2.2V/3V
50
110
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, VREF,DAC12 = AVCC
2.2V/3V
200
440
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, VREF,DAC12 = AVCC
2.2V/3V
700
1500
2.7V
70
DAC12_xDAT = 800h, VREF,DAC12 = 1.2V
∆AVCC = 100mV
µA
A
dB
NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{∆AVCC/∆VDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
POST OFFICE BOX 655303
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31
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 12)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
Resolution
(12-bit Monotonic)
INL
Integral nonlinearity
(see Note 1)
VREF,DAC12 = 1.2V
DAC12AMPx = 7, DAC12IR = 1
2.7V
±2.0
±8.0
LSB
DNL
Differential nonlinearity
(see Note 1)
VREF,DAC12 = 1.2V
DAC12AMPx = 7, DAC12IR = 1
2.7V
±0.4
±1.0
LSB
Offset voltage w/o
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2V
DAC12AMPx = 7, DAC12IR = 1
2.7V
Offset voltage with
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2V
DAC12AMPx = 7, DAC12IR = 1
EO
dE(O)/dT
Offset error
temperature coefficient
(see Note 1)
EG
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
tOffset_Cal
Time for offset calibration
(see Note 3)
12
UNIT
bits
±20
mV
±2.5
2.7V
±30
2.7V
VREF,DAC12 = 1.2V
µV/C
±3.50
2.7V
2.7V
% FSR
ppm of
FSR/°C
10
DAC12AMPx=2
2.7V
100
DAC12AMPx=3,5
2.7V
32
DAC12AMPx=4,6,7
2.7V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VREF,DAC12/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
Ideal transfer
function
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 12. Linearity Test Load Conditions and Gain/Offset Definition
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
INL − Integral Nonlinearity Error − LSB
4
VCC = 2.2 V, VREF = 1.2V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL − Differential Nonlinearity Error − LSB
2.0
VCC = 2.2 V, VREF = 1.2V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
VO
TEST CONDITIONS
Output voltage
range
(see Note 1,
Figure 15)
CL(DAC12)
Max DAC12
load capacitance
IL(DAC12)
Max DAC12
load current
RO/P(DAC12)
Output
Resistance
(see Figure 15)
VCC
MIN
TYP
MAX
No Load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.005
No Load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AVCC−0.05
AVCC
UNIT
V
RLoad= 3 kΩ, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.1
RLoad= 3 kΩ, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AVCC−0.13
AVCC
2.2V/3V
100
2.2V
−0.5
+0.5
3V
−1.0
+1.0
RLoad= 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
2.2V/3V
150
250
RLoad= 3 kΩ,
VO/P(DAC12) > AVCC−0.3 V
DAC12_xDAT = 0FFFh
2.2V/3V
150
250
RLoad= 3 kΩ,
0.3V ≤ VO/P(DAC12) ≤ AVCC − 0.3V
2.2V/3V
1
4
pF
mA
Ω
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
ILoad
RO/P(DAC12_x)
Max
RLoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC−0.3V
VOUT
AV CC
Figure 15. DAC12_x Output Resistance Tests
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
VREF
Reference input
voltage range
Ri(VREF)
Reference input
resistance
NOTES: 1.
2.
3.
4.
5.
DAC12IR=0, (see Notes 1 and 2)
VCC
2.2V/3V
MIN
DAC12IR=1, (see Notes 3 and 4)
2.2V/3V
DAC12IR=0 , (see Note 5)
2.2V/3V
20
DAC12IR=1
2.2V/3V
40
TYP
MAX
AVCC/3
AVCC
AVCC+0.2
AVCC+0.2
48
56
UNIT
V
MΩ
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / [3*(1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / (1 + EG).
Characterized, not production tested
12-bit DAC, dynamic specifications; VREF,DAC12 = AVCC, DAC12IR = 1 (see Figure 16 and Figure 17)
PARAMETER
tON
tS(FS)
tS(C-C)
SR
TEST CONDITIONS
DAC12 ontime
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB
(see Note 1,Figure 16)
Settling
time,full-scale
DAC12_xDAT =
80h→ F7Fh→ 80h
Settling time,
code to code
DAC12_xDAT =
3F8h→ 408h→ 3F8h
BF8h→ C08h→ BF8h
Slew Rate
DAC12_xDAT =
80h→ F7Fh→ 80h
Glitch energy: full-scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx=0 → {2, 3, 4}
VCC
2.2V/3V
MIN
TYP
MAX
60
120
DAC12AMPx=0 → {5, 6}
2.2V/3V
15
30
DAC12AMPx=0 → 7
2.2V/3V
6
12
DAC12AMPx=2
2.2V/3V
100
200
DAC12AMPx=3,5
2.2V/3V
40
80
DAC12AMPx=4,6,7
2.2V/3V
15
30
DAC12AMPx=2
2.2V/3V
5
DAC12AMPx=3,5
2.2V/3V
2
DAC12AMPx=4,6,7
2.2V/3V
1
DAC12AMPx=2
2.2V/3V
0.05
0.12
DAC12AMPx=3,5
2.2V/3V
0.35
0.7
DAC12AMPx=4,6,7
2.2V/3V
1.5
2.7
DAC12AMPx=2
2.2V/3V
10
DAC12AMPx=3,5
2.2V/3V
10
DAC12AMPx=4,6,7
2.2V/3V
15
UNIT
µs
µs
µs
V/µs
nV-s
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 16.
2. Slew rate applies to output voltage steps >= 200mV.
Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kΩ
Glitch
Energy
Conversion 2
Conversion 3
+/− 1/2 LSB
AV CC
2
RO/P(DAC12.x)
+/− 1/2 LSB
CLoad = 100pF
tsettleLH
tsettleHL
Figure 16. Settling Time and Glitch Energy Testing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 17. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted)
PARAMETER
BW−3dB
TEST CONDITIONS
3-dB bandwidth,
VDC=1.5V, VAC=0.1VPP
(see Figure 18)
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
550
NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF
ILoad
Ve REF+
RLoad = 3 kΩ
AV CC
DAC12_x
2
DACx
AC
CLoad = 100pF
DC
Figure 18. Test Conditions for 3-dB Bandwidth Specification
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
MAX
UNIT
kHz
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
ERASE)
VCC
Program and Erase supply voltage
MIN
NOM
2.5
fFTG
IPGM
Flash Timing Generator frequency
257
IERASE
tCPT
Supply current from DVCC during erase
Cumulative program time
see Note 1
2.5V/3.6V
tCMErase
Cumulative mass erase time
see Note 2
2.5V/3.6V
Supply current from DVCC during program
2.5V/3.6V
3
2.5V/3.6V
3
Program/Erase endurance
TJ = 25°C
200
104
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
ms
105
tRetention
Data retention duration
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
5297
Segment erase time
4819
Block program end-sequence wait time
MAX
cycles
100
years
35
30
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64−byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
3V
2.2 V/ 3 V
25
MIN
NOM
MAX
UNIT
0
5
MHz
0
10
MHz
60
90
kΩ
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TDI/TCLK during fuse blow
TA = 25°C
Voltage level on TDI/TCLK for fuse-blow: F versions
VCC
2.5
6
Time to blow fuse
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
input/output schematics
Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
Pad Logic
DV SS
DV SS
DV SS
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
Bus
Keeper
P1SEL.x
P1.0/TA0
P1.1/TA0/MCLK
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Note: x = 0,1
Port P1 (P1.0, P1.1) pin functions
PIN NAME (P1.X)
P1.0/TA0
P1.1/TA0/MCLK
CONTROL BITS / SIGNALS
X
0
1
FUNCTION
P1DIR.x
P1SEL.x
0/1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
0/1
0
Timer_A3.CCI0B
0
1
MCLK
1
1
P1.0† Input/Output
P1.1† Input/Output
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
INCH=4
Pad Logic
0
AV SS
A4−
1
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
P1.2/TA1/A4−
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 2
Port P1 (P1.2) pin functions
PIN NAME (P1.X)
P1.2/TA1/A4−
CONTROL BITS / SIGNALS
X
2
FUNCTION
P1.2† Input/Output
P1DIR.x
P1SEL.x
SD16AE.x
0/1
0
0
Timer_A3.CCI1A
0
1
0
Timer_A3.TA1
1
1
0
A4− (see Notes 3, 4)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A4−) connected to VSS if corresponding SD16AE.x bit is cleared.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
INCH=y
Pad Logic
Ay+
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
P1IRQ.x
D
P1IE.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Note: x = 3,5,7
y = 4,3,2
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P1.3/TA2/A4+
P1.5/TACLK/ACLK/A3+
P1.7/A2+
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 (P1.3, P1.5, P1.7) pin functions
PIN NAME (P1.X)
P1.3/TA2/A4+
P1.5/TACLK/ACLK/A3+
CONTROL BITS / SIGNALS
X
3
5
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
0/1
0
0
Timer_A3.CCI2A
0
1
0
Timer_A3.TA2
1
1
0
A4+ (see Note 3)
X
X
1
P1.3† Input/Output
P1.5† Input/Output
0/1
0
0
Timer_A3.TACLK/INCLK
0
1
0
ACLK
1
1
0
A3+ (see Note 3)
P1.7/A2+
7
P1.5† Input/Output
N/A
X
X
1
0/1
0
0
0
1
0
0
DVSS
1
1
A2+ (see Note 3)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
INCH=3
Pad Logic
0
AV SS
A3−
1
SD16AE.x
DAC12OPS
’1’ if DAC12AMPx>0
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
DVSS
1
P1.4/A3−/DAC0
Bus
Keeper
P1SEL.x
EN
P1IN.x
DAC12OPS
P1IE.x
P1IRQ.x
EN
DAC0
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Note: x = 4
Port P1 (P1.4) pin functions
PIN NAME (P1.X)
P1.4/A3−/DAC0
CONTROL BITS / SIGNALS
X
4
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
DAC12OPS
0/1
0
0
0
N/A
0
1
0
0
DVSS
1
1
0
0
A3− (see Notes 3, 4)
X
X
1
0
P1.4† Input/Output
DAC0 (see Note 5)
X
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A3−) connected to AVSS if corresponding SD16AE.x bit is cleared.
5. Setting the DAC12OPS bit also disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
INCH=2
Pad Logic
0
AV SS
A2−
1
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
DV SS
0
1
P1.6/A2−
Bus
Keeper
P1SEL.x
EN
P1IN.x
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 6
Port P1 (P1.6) pin functions
PIN NAME (P1.X)
P1.6/A2−
CONTROL BITS / SIGNALS
X
6
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
A2− (see Notes 3, 4)
X
X
P1.6† Input/Output
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A2−) connected to AVSS if corresponding SD16AE.x bit is cleared.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P2 pin schematic: P2.0 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
Pad Logic
LCDS4/8/12
Segment Sy
DV SS
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
DV SS
0
1
Bus
Keeper
P2SEL.x
EN
P2IN.x
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Note: x = 0 to 7
y = 13 to 6
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.0/S13
P2.1/S12
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P2 (P2.0 to P2.7) pin functions
PIN NAME (P2.X)
P2.0/S13
P2.1/S12
CONTROL BITS / SIGNALS
X
0
1
FUNCTION
P2DIR.x
P2SEL.x
LCDS12
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S13
X
X
1
P2.0† Input/Output
P2.1† Input/Output
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S12
P2.2/S11
2
P2.2† Input/Output
N/A
P2.3/S10
3
4
P2.6/S7
5
6
7
0
0
1
0
1
1
0
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
P2.3† Input/Output
P2.4† Input/Output
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
S9
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S8
X
X
1
0/1
0
0
0
1
0
P2.5† Input/Output
P2.6† Input/Output
N/A
P2.7/S6
1
0
S11
N/A
P2.5/S8
X
DVSS
S10
P2.4/S9
X
0/1
DVSS
1
1
0
S7
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P2.7† Input/Output
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCD
functions
Pad Logic
LCDS0/4
Segment Sy
DV SS
P5DIR.x
0
1
P5OUT.x
DV SS
P5SEL.x
Direction
0: Input
1: Output
0
1
Bus
Keeper
EN
P5IN.x
Note: x = 0,1,5,6,7
y = 1,0,2,3,4
46
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P5.0/S1
P5.1/S0
P5.5/S2
P5.6/S3
P5.7/S4
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 (P5.0, P5.1, P5.5, P5.6) pin functions
PIN NAME (P5.X)
P5.0/S1
P5.1/S0
CONTROL BITS / SIGNALS
X
0
1
FUNCTION
P5DIR.x
P5SEL.x
LCDS0
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
X
X
1
P5.0† Input/Output
P5.1† Input/Output
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S0
P5.5/S2
5
P5.5† Input/Output
N/A
P5.6/S3
6
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
S2
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
X
X
1
P5.6† Input/Output
S3
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
Port P5 (P5.7) pin functions
PIN NAME (P5.X)
P5.7/S4
CONTROL BITS / SIGNALS
X
7
FUNCTION
P5DIR.x
P5SEL.x
LCDS4
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
P5.7† Input/Output
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
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47
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
Pad Logic
LCD Signal
DV SS
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
DV SS
0
1
Bus
Keeper
P5SEL.x
P5.2/COM1
P5.3/COM2
P5.4/COM3
EN
P5IN.x
Note: x = 2 to 4
Port P5 (P5.2 to P5.4) pin functions
PIN NAME (P5.X)
CONTROL BITS / SIGNALS
X
P5.2/COM1
2
P5.3/COM2
3
FUNCTION
P5.2† Input/Output
COM1
P5.3† Input/Output
COM2
P5.4/COM3
4
P5.4† Input/Output
COM3
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
48
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P5DIR.x
P5SEL.x
0/1
0
X
1
0/1
0
X
1
0/1
0
X
1
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
INCH=0/1 #
Pad Logic
Ay+ #
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.0/A0+
P6.2/A1+
EN
P6IN.x
Note: x = 0,2
y = 0,1
#Signal from or to SD16
Port P6 (P6.0, P6.2) pin functions
PIN NAME (P6.X)
P6.0/A0+
CONTROL BITS / SIGNALS
X
0
FUNCTION
P6.0† Input/Output
A0+ (see Note 3)
P6.2/A1+
2
P6.2† Input/Output
P6DIR.x
P6SEL.x
0/1
0
X
1
0/1
0
A1+ (see Note 3)
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
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49
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
INCH=0/1 #
Pad Logic
Ay−#
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.1/A0−
P6.3/A1−
EN
P6IN.x
Note: x = 1,3
y = 0,1
#Signal from or to SD16
Port P6 (P6.1, P6.3) pin functions
PIN NAME (P6.X)
CONTROL BITS / SIGNALS
X
P6.1/A0−
1
P6.3/A1−
3
FUNCTION
P6.1† Input/Output
A0− (see Note 3)
P6.3† Input/Output
A1− (see Note 3)
P6DIR.x
P6SEL.x
0/1
0
X
1
0/1
0
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
50
POST OFFICE BOX 655303
X
• DALLAS, TEXAS 75265
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
P6DIR.x
Pad Logic
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.4
P6.5
P6.6
P6.7
EN
P6IN.x
Note: x = 4 to 7
Port P6 (P6.4 to P6.7) pin functions
PIN NAME (P6.X)
P6.4
P6.5
CONTROL BITS / SIGNALS
X
4
5
FUNCTION
P6.4† Input/Output
0/1
0
0
1
DVSS
1
1
0/1
0
0
1
P6.5† Input/Output
DVSS
6
P6.6† Input/Output
N/A
DVSS
P6.7
7
P6SEL.x
N/A
N/A
P6.6
P6DIR.x
P6.7† Input/Output
N/A
DVSS
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
1
0/1
0
0
1
1
1
0/1
0
0
1
1
1
51
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
52
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G
D
U
S
G
D
U
S
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 19. Fuse Check Mode Current
POST OFFICE BOX 655303
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53
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F4250IDL
ACTIVE
SSOP
DL
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4250IDLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4250IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4250IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4260IDL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4260IDLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4260IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4260IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4270IDL
ACTIVE
SSOP
DL
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4270IDLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4270IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F4270IRGZT
ACTIVE
QFN
RGZ
48
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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