CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE (TOP VIEW) Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Distributes One Clock Input to Ten Outputs Outputs Have Internal Series Damping Resistor to Reduce Transmission Line Effects Distributed VCC and Ground Pins Reduce Switching Noise State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages Available in Q-Temp Automotive High Reliability Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards GND Y10 VCC Y9 OE A P0 P1 Y8 VCC Y7 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 GND Y1 VCC Y2 GND Y3 Y4 GND Y5 VCC Y6 GND description The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351 operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND. The CDC2351 is characterized for operation from 0°C to 70°C. The CDC2351Q is characterized for operation over the full automotive temperature range of – 40°C to 125°C. FUNCTION TABLE INPUTS A OE OUTPUTS In L H Z H H Z L L L H L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙΒ is a trademark of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 logic symbol† OE 5 EN 23 Y1 21 Y2 19 Y3 18 A Y4 16 6 Y5 14 Y6 11 Y7 9 Y8 4 Y9 2 Y10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE 5 23 21 19 18 Y1 Y2 Y3 Y4 6 A 16 7 8 P0 P1 14 11 9 4 2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y5 Y6 Y7 Y8 Y9 Y10 CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.6 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . 1.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) MIN MAX 3.6 UNIT VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage 5.5 V IOH IOL High-level output current – 12 mA Low-level output current 12 mA fclock Input clock frequency 100 MHz TA V 0.8 Input voltage 0 CDC2351 Operating free free-air air temperature CDC2351Q V 0 70 –40 125 V °C NOTE 3: Unused pins (input or I/O) must be held high or low. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 3 V, VCC = 3 V, II = –18 mA IOH = – 12 mA VOL II IO‡ VCC = 3 V, VCC = 3.6 V, IOL = 12 mA VI = VCC or GND IOZ VCC = 3.6 V, VCC = 3.6 V, VO = 2.5 V VCC = 3 V or 0 ICC VCC = 3.6 V, IO = 0, MIN TYP Ci VI = VCC or GND, VCC = 3.3 V, V V –7 0.8 V ±1 µA –70 mA ± 10 µA 0.3 Outputs low 15 Outputs disabled 0.3 f = 10 MHz Co VO = VCC or GND, VCC = 3.3 V, f = 10 MHz ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 655303 UNIT –1.2 2 Outputs high VI = VCC or GND MAX • DALLAS, TEXAS 75265 mA 4 pF 6 pF 3 CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 switching characteristics, CL = 50 pF (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) CDC2351 CDC2351Q CDC2351 VCC = 3.3 V, TA = 25°C VCC = 3 V to 3.6 V, TA = –40°C to 125°C VCC = 3 V to 3.6 V, TA = 0°C to 70°C MIN TYP MAX MIN MAX MIN 3.8 4.3 4.8 1.1 11 3.6 4.1 4.6 1 9.7 2.4 4.9 6.0 1 12 1.8 6.9 2.4 4.3 6.0 1 11.1 1.8 6.9 2.2 4.4 6.3 1 11.1 2.1 7.1 2.2 4.6 6.3 1 11.5 2.1 7.3 UNIT MAX tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y tsk(o) A Y 0.3 0.5 2.5 0.5 ns tsk(p) A Y 0.2 0.8 3 0.8 ns tsk(pr) tr A Y 1 ns A Y 2.5 2.5 ns tf A Y 2.5 2.5 ns ns 1 ns ns switching characteristics temperature and VCC coefficients over recommended operating free-air temperature and VCC range (see Note 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT ps/10°C ∝tPLH(T) ∝tPHL(T) Average temperature coefficient of low to high propagation delay A Y Average temperature coefficient of high to low propagation delay A Y 85† 50† ∝tPLH(VCC) Average VCC coefficient of low to high propagation delay A Y –145‡ ps/ 100 mV ∝tPHL(VCC) Average VCC coefficient of high to low propagation delay A Y –100‡ ps/ 100 mV † ∝tPLH(T) and ∝tPHL(T) are virtually independent of VCC. ‡ ∝tPLH(VCC) and ∝tPHL(VCC) are virtually independent of temperature. NOTE 4: This data was extracted from characterization material and are not tested at the factory. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ps/10°C CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open GND CL = 50 pF (see Note A) S1 Open 6V GND 500 Ω tw LOAD CIRCUIT 3V Input 3V 1.5 V 1.5 V 0V 1.5 V Timing Input 0V tsu VOLTAGE WAVEFORMS th 3V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS 1.5 V 0V tPHL 2V 0.8 V tr 1.5 V 0V tPLZ 1.5 V tPLH Output 1.5 V tPZL 3V Input 3V Output Control (low-level enabling) 1.5 V VOH 2V 0.8 V VOL tf 3V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH VOLTAGE WAVEFORMS VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 PARAMETER MEASUREMENT INFORMATION A Y1 tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHL5 tPLH5 tPHL6 tPLH6 tPHL7 tPLH7 tPHL8 tPLH8 tPHL9 tPLH9 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 tPHL10 tPLH10 NOTES: A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) – The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10). C. Process skew, tsk(pr), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions – The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDC2351DB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK2351 CDC2351DBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK2351 CDC2351DBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI 0 to 70 CDC2351DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK2351 CDC2351DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK2351 CDC2351DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDC2351 CDC2351DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDC2351 CDC2351DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDC2351 CDC2351DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDC2351 CDC2351PWR OBSOLETE TSSOP PW 24 TBD Call TI Call TI CDC2351PWRG4 OBSOLETE TSSOP PW 24 TBD Call TI Call TI CDC2351QDB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CK2351Q CDC2351QDBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CK2351Q CDC2351QDBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CK2351Q CDC2351QDBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CK2351Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF CDC2351 : • Enhanced Product: CDC2351-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC2351DBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 CDC2351DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CDC2351QDBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 CDC2351QDBRG4 SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC2351DBR SSOP DB 24 2000 367.0 367.0 38.0 CDC2351DWR SOIC DW 24 2000 367.0 367.0 45.0 CDC2351QDBR SSOP DB 24 2000 367.0 367.0 38.0 CDC2351QDBRG4 SSOP DB 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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