ON MC74VHCT126ADR2G Quad bus buffer with 3â state control input Datasheet

MC74VHCT126A
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHCT126A is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves
noninverting high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHCT126A requires the 3−state control input (OE) to be
set Low to place the output into high impedance.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT126A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
1
14
High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
VHCT
126A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
1
14
Features
•
•
•
•
•
•
•
•
•
•
•
•
VHCT126AG
AWLYWW
SOEIAJ−14
M SUFFIX
CASE 965
1
VHCT126
ALYWG
1
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
See Applications Note #AND8004/D for
date code and traceability information.
FUNCTION TABLE
VHCT126A
Inputs
Outputs
A
OE
Y
H
L
X
H
H
L
H
L
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 7
1
Publication Order Number:
MC74VHCT126A/D
MC74VHCT126A
2
A1
3
Y1
1
OE1
5
A2
6
OE1
1
14
VCC
A1
2
13
OE4
Y1
3
12
A4
OE2
4
11
Y4
A2
5
10
Y2
6
9
A3
GND
7
8
Y3
Y2
4
OE2
9
A3
8
Y3
10
OE3
12
A4
11
OE3
Y4
13
OE4
Figure 2. PIN ASSIGNMENT
Figure 1. LOGIC DIAGRAM
Active−High Output Enables
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MAXIMUM RATINGS
Rating
DC Supply Voltage
DC Input Voltage
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin
– 0.5 to + 7.0
V
Vout
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
Input Diode Current
IIK
− 20
mA
Output Diode Current (VOUT < GND; VOUT > VCC)
IOK
± 20
mA
DC Output Current, per Pin
Iout
± 25
mA
DC Supply Current, VCC and GND Pins
ICC
± 75
mA
Power Dissipation in Still Air,
PD
500
450
mW
Tstg
– 65 to + 150
_C
DC Output Voltage
Output in 3−State
High or Low State
SOIC Packages†
TSSOP Package†
Storage Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
DC Supply Voltage
VCC
4.5
5.5
V
DC Input Voltage
Vin
0
5.5
V
Output in 3−State
High or Low State
Vout
0
0
5.5
VCC
V
TA
− 40
+ 85
_C
VCC = 5.0 V ±0.5 V
tr, tf
0
20
ns/V
DC Output Voltage
Operating Temperature
Input Rise and Fall Time
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
MC74VHCT126A
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ÎÎ
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DC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Symbol
TA = 25°C
VCC
(V)
Min
1.2
2.0
2.0
Typ
Minimum High−Level Input
Voltage
VIH
3.0
4.5
5.5
Maximum Low−Level Input
Voltage
VIL
3.0
4.5
5.5
VOH
3.0
4.5
2.9
4.4
3.0
4.5
2.58
3.94
Minimum High−Level Output
Voltage
VIN = VIH or VIL
Maximum Low−Level Output
Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = − 50 mA
VIN = VIH or VIL
IOH = − 4.0 mA
IOH = − 8.0 mA
VOL
VIN = VIH or VIL
IOL = 50 mA
Max
Min
Max
1.2
2.0
2.0
0.53
0.8
0.8
3.0
4.5
VIN = VIH or VIL
IOL = 4.0 mA
IOL = 8.0 mA
TA ≤ 85°C
3.0
4.5
0.0
0.0
TA ≤ 125°C
Min
Max
1.2
2.0
2.0
0.53
0.8
0.8
V
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
Maximum Input Leakage Current
VIN = 5.5 V or GND
IIN
0 to 5.5
± 0.1
± 1.0
± 1.0
mA
Maximum Quiescent Supply
Current
VIN = VCC or GND
ICC
5.5
2.0
20
40
mA
Quiescent Supply Current
Input: VIN = 3.4 V
ICCT
5.5
1.35
1.50
1.65
mA
Maximum 3−State Leakage
Current
VIN = VIH or VI
VOUT = VCC or GND
IOZ
5.5
±0.2
5
±2.5
±2.5
mA
Output Leakage Current
VOUT = 5.5 V
IOPD
0.0
0.5
5.0
10
mA
TA = ≤ 85°C
TA ≤ 125°C
Min
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Parameter
Maximum Propagation Delay,
A to Y
Test Conditions
Symbol
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
tPLH,
tPHL
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
Maximum Output Enable
TIme,OE to Y
tPZL,
tPZH
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
RL = 1.0 kW
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
RL = 1.0 kW
Maximum Output
Disable Time,OE to Y
tPLZ,
tPHZ
VCC = 3.3 ± 0.3 V CL = 50 pF
RL = 1.0 kW
VCC = 5.0 ± 0.5 V CL = 50 pF
RL = 1.0 kW
Output−to−Output Skew
Min
Typ
Max
Min
Max
Max
Unit
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
12.0
16.0
ns
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
9.5
13.2
1.0
15.0
18.0
6.1
8.8
1.0
10.0
12.0
1.5
1.5
2.0
1.0
1.0
1.5
10
10
10
tOSLH,
tOSHL
VCC = 3.3 ± 0.3 V CL = 50 pF
(Note 1)
VCC = 5.0 ± 0.5 V CL = 50 pF
(Note 1)
Maximum Input Capacitance
Cin
4
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
Cout
6
ns
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0V
Power Dissipation Capacitance (Note 2)
CPD
15
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHCT126A
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Typ
Max
Unit
Quiet Output Maximum Dynamic VOL
VOLP
0.3
0.8
V
Quiet Output Minimum Dynamic VOL
VOLV
− 0.3
− 0.8
V
Minimum High Level Dynamic Input Voltage
VIHD
3.5
V
Maximum Low Level Dynamic Input Voltage
VILD
1.5
V
Characteristic
SWITCHING WAVEFORMS
3.0V
OE
3.0V
A
1.5V
GND
1.5V
tPZL
GND
tPHL
tPLH
Y
Y
VOH
1.5V
tPLZ
HIGH
IMPEDANCE
1.5V
tPZH
VOL
VOL + 0.3V
tPHZ
VOH - 0.3V
Y
1.5V
Figure 3.
HIGH
IMPEDANCE
Figure 4.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
ORDERING INFORMATION
Package
Shipping†
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT126AMG
SOEIAJ−14
(Pb−Free)
50 Units / Rail
MC74VHCT126AMELG
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
MC74VHCT126ADTRG
TSSOP−14*
(Pb−Free)
Device
MC74VHCT126ADR2G
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHCT126A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
7
1
G
−T−
0.25 (0.010)
M
T B
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
M
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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5
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74VHCT126A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
6
MC74VHCT126A
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
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