CAT24C32 32-Kb I2C CMOS Serial EEPROM FEATURES DEVICE DESCRIPTION ■ Supports Standard and Fast I2C Protocol The CAT24C32 is a 32-Kb CMOS Serial EEPROM devices, internally organized as 128 pages of 32 bytes each. ■ 1.8 V to 5.5 V Supply Voltage Range ■ 32-Byte Page Write Buffer It features a 32-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. ■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA). External address pins make it possible to address up to eight CAT24C32 devices on the same bus. ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and TDFN packages For Ordering Information details, see page 15. PIN CONFIGURATION FUNCTIONAL SYMBOL PDIP (L) SOIC (W) TSSOP (Y) TDFN (ZD2, VP2) A0 1 8 VCC A1 A2 2 7 WP 3 6 SCL VSS 4 5 SDA VCC SCL A2, A1, A0 For the location of Pin 1, please consult the corresponding package drawing. Device Address SDA Serial Data SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice SDA WP PIN FUNCTIONS A0, A1, A2 CAT24C32 VSS * The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu pre-plated lead frames. 1 Doc. No. 1101, Rev. G CAT24C32 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground(2) -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS(3) Symbol Parameter Min Units NEND(4) Endurance 1,000,000 Program/ Erase Cycles 100 Years TDR Data Retention D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions ICCR Read Current ICCW Min Max Units Read, fSCL = 400 kHz 1 mA Write Current Write, fSCL = 400 kHz 1 mA ISB Standby Current All I/O Pins at GND or VCC 1 μA IL I/O Pin Leakage Pin at GND or VCC 1 μA VIL Input Low Voltage VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V Max Units -0.5 PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Conditions CIN(3) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN(3) Input Capacitance (other pins) VIN = 0 V 6 pF IWP(5) WP Input Current VIN < VIH 100 VIN > VIH 1 μA Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. Doc. No. 1101, Rev. G 2 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C. Standard Symbol FSCL tHD:STA Min Parameter Max Clock Frequency Fast Min 100 START Condition Hold Time Max Units 400 kHz 4 0.6 μs tLOW Low Period of SCL Clock 4.7 1.3 μs tHIGH High Period of SCL Clock 4 0.6 μs 4.7 0.6 μs tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 μs tSU:DAT Data In Setup Time 250 100 ns tR SDA and SCL Rise Time 1000 300 ns tF(2) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 4 0.6 μs 4.7 1.3 μs 3.5 100 0.9 100 100 μs ns 100 ns tSU:WP WP Setup Time 0 0 μs tHD:WP WP Hold Time 2.5 2.5 μs tWR tPU(2, 3) Write Cycle Time 5 5 ms Power-up to Ready Mode 1 1 ms Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1101, Rev. G CAT24C32 POWER-ON RESET (POR) FUNCTIONAL DESCRIPTION Each CAT24C32 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. The CAT24C32 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24C32 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAT24C32, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/ R/W W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 2). SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Doc. No. 1101, Rev. G 4 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 Figure 1. Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1101, Rev. G CAT24C32 WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/ R/W W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 6). Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Acknowledge Polling As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C32 is shipped erased, i.e., all bytes are FFh. Doc. No. 1101, Rev. G 6 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 Figure 5. Byte Write Sequence BUS ACTIVITY: MASTER S T A R T SLAVE ADDRESS S ADDRESS BYTE DATA BYTE DATA BYTE a15 ÷ a8 a7 ÷ a0 d7 ÷ d0 S T O P P ** * * A C K SLAVE A C K A C K A C K * a15 ÷ a12 are don't care bits. Figure 6. Write Cycle Timing SCL 8th Bit Byte n SDA ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Page Write Sequence BUS ACTIVITY: MASTER S T A R T ADDRESS BYTE SLAVE ADDRESS DATA BYTE n ADDRESS BYTE DATA BYTE n+1 S T O P DATA BYTE n+P S P A C K SLAVE n=1 P ≤ 31 A C K A C K A C K A C K A C K A C K Figure 8. WP Timing ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1101, Rev. G CAT24C32 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/ R/W W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/ R/W W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. Doc. No. 1101, Rev. G 8 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 Figure 9. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T N O S AT CO KP SLAVE ADDRESS S P A C K SLAVE SCL 8 DATA BYTE 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Selective Read Sequence BUS ACTIVITY: MASTER S T A R T ADDRESS BYTE SLAVE ADDRESS S T A R T ADDRESS BYTE S N O S AT CO KP SLAVE ADDRESS S A C K SLAVE A C K P A C K A C K DATA BYTE Figure 11. Sequential Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice A C K DATA BYTE n DATA BYTE n+1 9 DATA BYTE n+2 DATA BYTE n+x Doc No. 1101, Rev. G CAT24C32 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A A1 L e eB b2 b SYMBOL A A1 A2 b b2 D E E1 e eB L MIN NOM MAX 4.57 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115 0.46 7.87 6.35 2.54 BSC 0.130 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C32_64_8-LEAD_DIP_(300P).eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1101, Rev. G 10 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 8-LEAD 150 MIL WIDE SOIC (W) E1 E h x 45 D C A θ1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L θ1 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C32_64_8-LEAD_SOIC.eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012 dimensions. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1101, Rev. G CAT24C32 8-LEAD TSSOP (Y) D 5 8 SEE DETAIL A c E E1 E/2 GAGE PLANE 4 1 PIN #1 IDENT. 0.25 θ1 L A2 SEATING PLANE SEE DETAIL A A e A1 b SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM 0.90 3.00 6.4 4.40 0.65 BSC 0.60 MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153. Doc. No. 1101, Rev. G 12 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 8-PAD TDFN 3X4.9 PACKAGE (ZD2) SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.45 0.55 0.65 A3 0.20 R E F b 0.25 0.30 0.35 D 2.90 3.00 3.10 D2 0.90 1.00 1.10 E 4.80 4.90 5.00 E2 0.90 1.00 1.10 e L 0.65 T Y P 0.50 0.60 0.70 For current Tape and Reel information, download the PDF file from: Notes: http://www.catsemi.com/documents/tapeandreel.pdf. (1) All dimensions are in millimeters. Angles in degree. (2) Complies with JEDEC MO-229. Notes: 1. All dimensions are in millimeters. Angles in degree. 2. Complies with JEDEC MO-229. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc No. 1101, Rev. G CAT24C32 CAT4004 8-LEAD TDFN 2x3 (VP2) PACKAGE OUTLINES 8 LEAD TDFN (VP2) 2mm x 3mm A E PIN 1 INDEX AREA A1 D D2 A2 A3 SYMBOL MIN NOM MAX A A1 A2 A3 b D D2 E E2 e L 0.70 0.00 0.45 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 0.80 0.05 0.65 0.20 1.90 1.30 2.90 1.20 0.20 E2 0.30 2.10 1.50 3.10 1.40 PIN 1 ID L 0.40 b e 3xe For current Tape & Reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters, angles in degrees. Notes: (2) Complies with JEDEC Standard 1. All dimensions are in millimeters, angles in degrees. 2. Complies with JEDEC Standard MO-229. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1101, Rev. G 9 14 Doc. No. 5024 Rev. A © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 EXAMPLE OF ORDERING INFORMATION Prefix Device # CAT Company ID Suffix 24C32 Y Product Number 24C32 L: W: Y: ZD2: VP2: I – G Temperature Range I = Industrial (-40°C to +85°C) Package PDIP SOIC, JEDEC TSSOP TDFN (3x4.9)(5) TDFN (2x3) T3 T: Tape & Reel 2: 2000/Reel 3: 3000/Reel Lead Finish G: NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu on pre-plated (PPF) lead frames. (3) The device used in the above example is a CAT24C32YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. (5) TDFN, ZD2 is only available in 2000 pcs/reel, i.e., CAT24C32ZD2I-T2. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc No. 1101, Rev. G CAT24C32 REVISION HISTORY Date Revision Comments 10/07/05 A Initial Issue 11/15/05 B Update Ordering Information Add Tape and Reel Specifications 02/02/06 C Update Ordering Information 08/23/06 D Updated device description, supporting text and figures, package outlines, package marking and ordering information. Updated and re-formatted D.C. Characteristics presentation. Updated and re-formatted A.C. Characteristics presentation to reflect Standard (100 kHz) and Fast (400 kHz) operation over the full voltage range. 09/08/06 E Remove Package Markings 02/12/07 F UpdateTDFN 8 Lead (3x4.9mm) package 03/20/07 G Add TDFN 8 Lead (2x3mm) package Doc. No. 1101, Rev. G 16 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C32 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory ™, DPP ™, EZDim ™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 17 Doc No. 1101, Rev. G Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1101 G 03/20/07