Revised March 2003 FIN1049 LVDS Dual Line Driver with Dual Line Receiver General Description Features This dual Driver-Receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The Driver accepts LVTTL inputs and translates them to LVDS outputs. The Receiver accepts LVDS inputs and translates them to LVTTL outputs. The LVDS levels have a typical differential output swing of 350mV which provide for low EMI at ultra low power dissipation even at high frequencies. The FIN1049 can accept LVPECL inputs for translating from LVPECL to LVDS. The En and Enb inputs are ANDed together to enable/disable the outputs. The enables are common to all four outputs. A single line driver and single line receiver function is also available in the FIN1019. ■ Greater than 400 Mbps data rate ■ 3.3V power supply operation ■ Low power dissipation ■ Fail safe protection for open-circuit conditions ■ Meets or exceeds the TIA/EIA-644-A LVDS standard ■ 16-pin TSSOP package saves space ■ Flow-through pinout simplifies PCB layout ■ Enable/Disable for all outputs ■ Industrial operating temperature range: −40°C to +85°C Ordering Code: Order Number FIN1049MTC Package Number Package Description MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pin Descriptions Pin Name Connection Diagram Description RIN1+, RIN2+ Non-Inverting LVDS Inputs RIN1−, RIN2− Inverting LVDS Inputs DOUT1+, DOUT2+ Non-Inverting Driver Outputs DOUT1−, DOUT2− Inverting Driver Outputs EN, ENb ROUT1, ROUT2 DIN2, DIN2 Driver Enable Pins for All Outputs LVTTL Output Pins for ROUT1 and ROUT2 LVTTL Input Pins for DIN1 and DIN2 VCC Power Supply (3.3V) GND Ground © 2003 Fairchild Semiconductor Corporation DS500846 www.fairchildsemi.com FIN1049 LVDS Dual Line Driver with Dual Line Receiver March 2003 FIN1049 Function Table Inputs Outputs (LVTTL) EN ENb ROUT1 ROUT2 H L ON H H L Inputs (LVDS) (Note 1) RIN#+ Outputs (LVDS) DOUT#+ DOUT#− ON ON ON Z Z Z Z H Z Z Z Z L L Z Z Z Z H L H H Open Current Fail Safe Condition H = HIGH Logic Level L = LOW Logic Level or OPEN X = Don’t Care Z = High Impedance Note 1: Any unused Receiver Inputs should be left Open. Functional Diagram www.fairchildsemi.com RIN#− 2 Supply Voltage (VCC) −0.5V to +4.6V LVDS DC Input Voltage (VIN) −0.5V to +4.6V LVDS DC Output Voltage (VOUT) −0.5V to +4.6V Driver Short Circuit Current (IOSD) Recommended Operating Conditions Supply Voltage (VCC) Continuous 10mA (|VID|) −65°C to +150°C Storage Temperature Range (TSTG) 100mV to VCC −40°C to +85°C Operating Temperature (TA) 150°C Max Junction Temperature (TJ) 3.0V to 3.6V Magnitude of Differential Voltage Lead Temperature (TL) (Soldering, 10 seconds) 260°C ESD (Human Body Model) >7000V Note 2: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. >250V ESD (Machine Model) DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ Max (Note 3) Units LVDS Input DC Specifications (RIN1+, RIN1−, RIN2 +, RIN2−) See Figure 1 and Table 1 VTH Differential Input Threshold HIGH VTL Differential Input Threshold LOW VIC Common Mode Voltage Range VID = 100mV, VCC = 3.3V IIN Input Current VCC = 0V or 3.6V, VIN = 0V or 2.8V VIH Input High Voltage (LVTTL) VIL Input Low Voltage (LVTTL) IIN Input Current VCM = 1.2V, 0.05V, 2.35V 0.0 −100 35.0 0.0 mV mV VCC − (VID/2) V ±20.0 mA 2.0 VCC V GND 0.8 V ±20.0 µA VID/2 CMOS/ LVTTL Input DC Specifications (EN, ENb, DIN1, DIN2) (EN, ENb, DIN1, DIN2, RINx+, and RINx−) VIK VIN = 0V or VCC VIK = −18mA Input Clamp Voltage −1.5 −0.7 V LVDS Output DC Specifications (DOUT1+, DOUT1−, DOUT2+, DOUT2−) VOD Output Differential Voltage ∆VOD VOD Magnitude Change from RL = 100Ω, 250 450 mV 35.0 mV 1.375 V 25.0 mV DOUT+ = 0V & DOUT− = 0V, Driver Enabled −9.0 mA VOD = 0V, Driver Enabled −9.0 mA ±20.0 µA ±10.0 µA Differential LOW-to-HIGH Driver Enabled, VOS Offset Voltage See Figure 2 ∆VOS Offset Magnitude Change from 1.125 350 1.25 Differential LOW-to-HIGH IOS IOSD Short Circuit Output Current IOFF Power-Off Input or Output Current VCC = 0V, VOUT = 0V or VCC IOZD Disabled Output Leakage Current Driver Disabled, DOUT+ = 0V or VCC or DOUT− = 0V or VCC CMOS/LVTTL Output DC Specifications (ROUT1, ROUT2) VOH Output High Voltage IOH = −2mA, VID = 200mV VOL Output Low Voltage IOL = 2mA, VID = 200mV 0.250 V IOZ Disabled Output Leakage Current Driver Disabled, ROUTn = 0V or VCC ±10.0 µA ICC Power Supply Current (Note 4) Drivers Enabled, Any Valid Input Condition 25.0 mA ICCZ Power Supply Current Drivers Disabled 10.0 mA CIND Input Capacitance LVDS Input 3.0 pF COUT Output Capacitance LVDS Output 4.0 pF CINT Input Capacitance LVTTL Input 3.5 pF 2.7 V Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. Note 4: Both driver and receiver inputs are static. All LVDS outputs have 100Ω load. None of the outputs have any lumped capacitive load. 3 www.fairchildsemi.com FIN1049 Absolute Maximum Ratings(Note 2) FIN1049 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ Max (Note 5) Units Switching Characteristics - LVDS Outputs tPLHD Differential Propagation Delay LOW-to-HIGH 2.0 ns tPHLD Differential Propagation Delay HIGH-to-LOW 2.0 ns tTLHD Differential Output Rise Time (20% to 80%) 0.2 1.0 ns tTHLD Differential Output Fall Time (80% to 20%) 0.2 1.0 ns tSK(P) Pulse Skew |tPLH - tPHL| 0.35 ns tSK(LH), Channel-to-Channel Skew (Note 6) 0.35 ns See Figures 3, 4 tSK(HL) tSK(PP) Part-to-Part Skew (Note 7) 1.0 ns tPZHD Differential Output Enable Time from Z-to-HIGH 6.0 ns tPZLD Differential Output Enable Time from A-to-LOW 6.0 ns tPHZD Differential Output Disable Time from HIGH-to-Z 3.0 ns tPLZD Differential Output Disable Time from LOW-to-Z fMAXD Maximum Frequency (Note 8) tPHL Propagation Delay HIGH-to-LOW Measured from 20% to 80% signal 0.5 1.0 3.5 ns tPLH Propagation Delay LOW-to-HIGH VID = 200mV; 0.5 1.0 3.5 ns tSK1 Pulse Skew Distributed Load 0.0 35.0 400 ps tSK2 Channel-to-Channel Skew CL = 15pF and 50Ω; 0.0 50.0 500 ps tSK3 Part-to-Part Skew RL = 1KΩ; 0.0 1.0 ns tLHR Transition Time LOW-to-HIGH VOS = 1.2V; 0.1 0.25 1.4 ns tHLR Transition Time HIGH-to-LOW See Figures 7, 8 0.1 0.18 1.4 ns tPHZ Disable Time HIGH-to-Z 2.2 4.5 8.0 ns tPLZ Disable Time LOW-to-Z 1.3 3.5 8.0 ns tPZH Enable Time Z-to-HIGH 1.8 3.0 7.0 ns tPZL Enable Time Z-to-LOW 0.9 1.4 7.0 fMAXT Maximum Frequency (Note 9) See Figures 5, 6 3.0 See Figure 3 200 ns MHz Switching Characteristics - LVTTL Outputs See Figures 9, 10 See Figure 7 200 ns MHz Note 5: All typical values are at TA = 25°C and with VCC = 3.3V. Note 6: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 7: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 8: fMAX generator input conditions: tr = tf < 1ns (10% to 90%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45% / 55%, VOD > 250mV, all channels switch. Note 9: fMAXT generator input conditions: tr = tf < 1ns (10% to 90%), 50% duty cycle, VID = 200mV, VCM = 1.2V. Output criteria: duty cycle = 45% / 55%, VOH > 2.7V. VOL < 0.25V, all channels switching. www.fairchildsemi.com 4 1. Human Body Model ESD and Machine Model ESD should be measured using MIL-STD-883C method 3015.7 standard. 2. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78). Note: CL = 15pF, includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Resulting Common Voltage (mV) Mode Input Voltage (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 −100 1.2 VCC VCC - 0.1 100 VCC - 0.05 VCC - 0.1 VCC −100 VCC - 0.05 0.1 0.0 100 0.05 0.0 0.1 −100 0.05 1.75 0.65 1100 1.2 0.65 1.75 −1100 1.2 VCC VCC - 1.1 1100 VCC - 0.55 VCC - 1.1 VCC −1100 VCC - 0.55 1.1 0.0 1100 0.55 0.0 1.1 −1100 0.55 Note: RL = 100Ω FIGURE 2. LVDS Output Circuit for DC Test 5 www.fairchildsemi.com FIN1049 Required Specifications FIN1049 Required Specifications (Continued) Note A: RL = 100Ω Note B: ZO = 50Ω and CT = 15 pF Distributed FIGURE 3. LVDS Output Propagation Delay and Transition Time Test Circuit FIGURE 4. LVTTL Input to LVDS Output AC Waveform www.fairchildsemi.com 6 FIN1049 Required Specifications (Continued) Note A: RL = 100Ω Note B: ZO = 50Ω and CT = 15 pF Distributed Note: R1 = 1000Ω, RS = 950Ω Note: VTST = 2.4V FIGURE 5. LVDS Output Enable / Disable Delay Test Circuit FIGURE 6. LVDS Output Enable / Disable Timing Waveforms 7 www.fairchildsemi.com FIN1049 Required Specifications (Continued) Note A: ZO = 50Ω and CT = 15 pF Distributed Note: RL = 100Ω and RS = 950Ω FIGURE 7. LVTTL Output Propagation Delay and Transition Time Test Circuit FIGURE 8. LVDS Input to LVTTL Output Propagation Delay and Transition Time Waveforms www.fairchildsemi.com 8 FIN1049 Required Specifications (Continued) Note A: ZO = 50Ω and CT = 15 pF Distributed Note: RL = 100Ω, R1 = 1000Ω, and RS = 950Ω FIGURE 9. LVTTL Output Enable / Disable Test Circuit FIGURE 10. LVTTL Output Enable / Disable Timing Waveforms 9 www.fairchildsemi.com FIN1049 LVDS Dual Line Driver with Dual Line Receiver Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10