Fairchild FQB6P25 250v p-channel mosfet Datasheet

FQB6P25 / FQI6P25
April 2000
QFET
TM
FQB6P25 / FQI6P25
250V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
•
•
•
•
•
•
-6.0A, -250V, RDS(on) = 1.1Ω @VGS = -10 V
Low gate charge ( typical 21 nC)
Low Crss ( typical 20 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
S
D
!
G!
G
S
D2-PAK
G D S
FQB Series
I2-PAK
FQI Series
!
D
Absolute Maximum Ratings
Symbol
VDSS
TC = 25°C unless otherwise noted
Parameter
ID
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
IDM
Drain Current
FQB6P25 / FQI6P25
- Continuous (TC = 100°C)
- Pulsed
A
-24
A
Single Pulsed Avalanche Energy
540
mJ
Avalanche Current
(Note 1)
-6.0
A
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
(Note 1)
9.0
-5.5
3.13
mJ
V/ns
W
90
0.72
-55 to +150
W
W/°C
°C
300
°C
EAR
(Note 3)
Power Dissipation (TC = 25°C)
TL
-3.8
V
IAR
TJ, TSTG
A
±30
Gate-Source Voltage
PD
V
-6.0
(Note 2)
VGSS
EAS
dv/dt
(Note 1)
Units
-250
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8 from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Typ
Max
Thermal Resistance, Junction-to-Case
Parameter
--
1.39
Units
°CW
RθJA
Thermal Resistance, Junction-to-Ambient *
--
40
°CW
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°CW
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Symbol
C
= 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-250
--
--
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS
/ ∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
--
-0.1
--
V/°C
-1
µA
µA
IDSS
Zero Gate Voltage Drain Current
VDS = -250 V, VGS = 0 V
--
--
VDS = -200 V, TC = 125°C
--
--
-10
IGSSF
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
IGSSR
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-3.0
--
-5.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -3.0 A
--
0.82
1.1
Ω
gFS
Forward Transconductance
VDS = -40 V, ID = -3.0 A
--
3.3
--
S
--
600
780
pF
--
115
150
pF
--
20
25
pF
--
13
35
ns
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -125 V, ID = -6.0 A,
RG = 25 Ω
(Note 4, 5)
VDS = -200 V, ID = -6.0 A,
VGS = -10 V
(Note 4, 5)
--
75
160
ns
--
40
90
ns
--
50
110
ns
--
21
27
nC
--
4.7
--
nC
--
10.7
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-6.0
ISM
--
--
-24
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -6.0 A
Drain-Source Diode Forward Voltage
--
--
-5.0
V
trr
Reverse Recovery Time
--
170
--
ns
Qrr
Reverse Recovery Charge
--
1.1
--
µC
VGS = 0 V, IS = -6.0 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 24mH, IAS = -6.0A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD -6.0A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, April 2000
FQB6P25 / FQI6P25
Electrical CharacteristicsT
VGS
-15 V
-10 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
Top :
-ID , Drain Current [A]
1
10
-ID , Drain Current [A]
1
10
0
10
150
0
10
25
-55
Notes :
1. 250s Pulse Test
2. TC = 25
-1
10
Notes :
1. VDS = -40V
2. 250s Pulse Test
-1
-1
0
10
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS , Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
3.0
1
10
-IDR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
2.5
VGS = - 10V
2.0
VGS = - 20V
1.5
0
10
1.0
0.5
150
25
Notes :
1. VGS = 0V
2. 250s Pulse Test
Note : TJ = 25
0.0
-1
0
4
8
12
16
20
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
1400
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1200
12
VDS = -50V
Ciss
Coss
800
600
Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
400
200
-VGS, Gate-Source Voltage [V]
10
1000
Capacitance [pF]
FQB6P25 / FQI6P25
Typical Characteristics
VDS = -125V
VDS = -200V
8
6
4
2
Note : ID = -6.0 A
0
-1
10
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
4
8
12
16
20
24
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, April 2000
FQB6P25 / FQI6P25
Typical Characteristics
(Continued)
3.0
1.2
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
RDS(ON) , (Normalized)
Drain-Source On-Resistance
1.1
1.0
0.9
Notes :
1. VGS = 0 V
2. ID = -250 A
0.8
-100
-50
0
50
100
2.0
1.5
1.0
Notes :
1. VGS = -10 V
2. ID = -3.0 A
0.5
150
0.0
-100
200
-50
0
o
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
2
6
10
Operation in This Area
is Limited by R DS(on)
5
1
10
-I D, Drain Current [A]
-I D, Drain Current [A]
100 µs
1 ms
10 ms
DC
0
10
Notes :
4
3
2
o
1. TC = 25 C
1
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
1
10
0
25
2
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
N o te s :
1 . Z J C ( t) = 1 .3 9 / W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z J C ( t)
0 .2
0 .1
10
-1
0 .0 5
PDM
0 .0 2
JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature []
-VDS, Drain-Source Voltage [V]
t1
0 .0 1
Z
s i n g le p u ls e
10
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, April 2000
FQB6P25 / FQI6P25
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50K
Qg
200nF
12V
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
t on
VDD
VGS
RG
td(on)
VGS
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
tp
ID
VDD
RG
VDD
DUT
-10V
tp
©2000 Fairchild Semiconductor International
Time
VDS (t)
ID (t)
IAS
BVDSS
Rev. A, April 2000
FQB6P25 / FQI6P25
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
I SD
( DUT )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
di/dt
IFM , Body Diode Forward Current
VDS
( DUT )
VSD
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2000 Fairchild Semiconductor International
Rev. A, April 2000
4.50 ±0.20
9.90 ±0.20
+0.10
2.00 ±0.10
(0.75)
3°
~
0°
0.80 ±0.10
1.27 ±0.10
2.54 TYP
2.54 ±0.30
15.30 ±0.30
0.10 ±0.15
2.40 ±0.20
4.90 ±0.20
9.20 ±0.20
1.30 –0.05
1.20 ±0.20
(0.40)
D2PAK
1.40 ±0.20
+0.10
0.50 –0.05
2.54 TYP
4.90 ±0.20
(2XR0.45)
9.20 ±0.20
10.00 ±0.20
(7.20)
(1.75)
10.00 ±0.20
(8.00)
(4.40)
15.30 ±0.30
FQB6P25 / FQI6P25
Package Dimensions
0.80 ±0.10
©2000 Fairchild Semiconductor International
Rev. A, April 2000
(Continued)
I2PAK
4.50 ±0.20
(0.40)
9.90 ±0.20
+0.10
MAX13.40
9.20 ±0.20
(1.46)
1.20 ±0.20
1.30 –0.05
0.80 ±0.10
2.54 TYP
2.54 TYP
10.08 ±0.20
1.47 ±0.10
MAX 3.00
(0.94)
13.08 ±0.20
)
5°
(4
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, April 2000
FQB6P25 / FQI6P25
Package Dimensions
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
E2CMOS™
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench®
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A, January 2000