MOTOROLA MMDF2N02E Dual tmos mosfet 3.6 amperes 25 volt Datasheet

 Order this document
by MMDF2N02E/D
SEMICONDUCTOR TECHNICAL DATA
 Medium Power Surface Mount Products
MiniMOS devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
•
•
•
•
•
•
•

DUAL TMOS MOSFET
3.6 AMPERES
25 VOLTS
RDS(on) = 0.1 OHM
D
G
CASE 751–05, Style 11
SO–8
S
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
IDSS Specified at Elevated Temperatures
Avalanche Energy Specified
Mounting Information for SO–8 Package Provided
Source–1
1
8
Drain–1
Gate–1
2
7
Drain–1
Source–2
3
6
Drain–2
Gate–2
4
5
Drain–2
Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Symbol
Value
Unit
VDSS
VGS
25
Vdc
± 20
Vdc
Adc
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C (1)
ID
ID
IDM
PD
3.6
2.5
18
2.0
W
Operating and Storage Temperature Range
TJ, Tstg
EAS
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 6.0 mH, RG = 25 Ω)
Thermal Resistance, Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds
Apk
mJ
245
RθJA
62.5
°C/W
TL
260
°C
DEVICE MARKING
F2N02
(1) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
MMDF2N02ER2
Reel Size
Tape Width
Quantity
13″
12 mm embossed tape
2500
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 5
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MMDF2N02E
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
25
—
—
—
—
—
—
1.0
10
—
—
100
1.0
2.0
3.0
—
—
0.083
0.110
0.100
0.200
gFS
1.0
2.6
—
Mhos
Ciss
—
380
532
pF
Coss
—
235
329
Crss
—
55
110
td(on)
—
7.0
21
tr
—
17
30
td(off)
—
27
48
tf
—
18
30
td(on)
—
10
30
tr
—
35
70
td(off)
—
19
38
tf
—
25
50
QT
—
10.6
30
Q1
—
1.3
—
Q2
—
2.9
—
Q3
—
2.7
—
VSD
—
1.0
1.4
Vdc
trr
—
34
66
ns
ta
—
17
—
tb
—
17
—
QRR
—
0.03
—
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
µAdc
nAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc
VGS(th)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 2.2 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
RDS(on)
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)
Vdc
Ohm
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0 Ω)
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage(1)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
See Figure 11
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Storage Charge
ns
nC
µC
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2N02E
TYPICAL ELECTRICAL CHARACTERISTICS
7
VGS = 10 V
4.5 V
4.3 V
4.1 V
6
5
3.7 V
3.5 V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
7
3.9 V
3.3 V
4
3.1 V
3
2.9 V
2
2.7 V
2.5 V
1
0
5
4
100°C
3
25°C
2
1
TJ = 25°C
0
VDS ≥ 10 V
TJ = 25°C
6
0.5
0.25
0.75
1.5
1
1.25
1.75
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ = –55°C
0
1.5
2
0.6
ID = 3.5 A
TJ = 25°C
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
3.5
4
TJ = 25°C
VGS = 4.5
0.1
10 V
0.05
0
0
1
2
3
4
5
6
7
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.0
10000
VGS = 10 V
ID = 3.5 A
VGS = 0 V
1.5
I DSS , LEAKAGE (nA)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
3
0.15
Figure 3. On–Resistance versus
Gate–to–Source Voltage
1.0
0.5
0
– 50
2.5
Figure 2. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 1. On–Region Characteristics
0.5
2
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
– 25
0
25
50
75
100
125
150
TJ = 125°C
1000
100°C
100
25°C
10
1
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
25
3
MMDF2N02E
POWER MOSFET SWITCHING
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
1200
VDS = 0 V
C, CAPACITANCE (pF)
1000
VGS = 0 V
TJ = 25°C
Ciss
800
Crss
600
Ciss
400
Coss
200
Crss
0
10
5
0
5
10
15
20
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
12
QT
8
Q1
4
Q3
0
2
4
6
8
Qg, TOTAL GATE CHARGE (nC)
10
0
12
7
6
td(off)
tf
IS, SOURCE CURRENT (AMPS)
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25°C
tr
t, TIME (ns)
ID = 2.3 A
TJ = 25°C
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
100
10
td(on)
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
4
Q2
3
Figure 7. Capacitance Variation
1
12
6
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1
VGS
VDS
9
0
25
16
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
100
TJ = 25°C
VGS = 0 V
5
4
3
2
1
0
0.5
0.6
0.7
0.8
0.9
1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1.1
Figure 10. Diode Forward Voltage
versus Current
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2N02E
di/dt = 300 A/µs
I S , SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
280
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max.
100 µs
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
10 ms
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
I pk = 9 A
240
200
160
120
80
40
0
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Motorola TMOS Power MOSFET Transistor Device Data
25
50
75
100
150
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
5
MMDF2N02E
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
Normalized to θja at 10s.
Chip
0.0175 Ω
0.0710 Ω
0.2706 Ω
0.0154 F
0.0854 F
0.3074 F
0.5776 Ω
0.7086 Ω
0.01
0.01
SINGLE PULSE
0.001
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
t, TIME (s)
1.0E+00
1.7891 F
1.0E+01
107.55 F
1.0E+02
Ambient
1.0E+03
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2N02E
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to insure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO–8 POWER DISSIPATION
The power dissipation of the SO–8 is a function of the input
pad size. These can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from the
device junction to ambient; and the operating temperature, TA.
Using the values provided on the data sheet for the SO–8
package, PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 2.0 Watts.
PD =
150°C – 25°C
= 2.0 Watts
62.5°C/W
The 62.5°C/W for the SO–8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.0 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad.
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
Motorola TMOS Power MOSFET Transistor Device Data
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
7
MMDF2N02E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
12 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 –189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SPIKE”
“SOAK”
170°C
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
160°C
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
8
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2N02E
PACKAGE DIMENSIONS
–A–
M
1
4
R
0.25 (0.010)
4X
–B–
X 45 _
B
M
5
P
8
NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J
M_
C
F
G
–T–
K
SEATING
PLANE
8X
D
0.25 (0.010)
M
T B
S
A
S
CASE 751–05
SO–8
ISSUE P
Motorola TMOS Power MOSFET Transistor Device Data
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
9
MMDF2N02E
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10
◊
*MMDF2N02E/D*
Motorola TMOS Power MOSFET TransistorMMDF2N02E/D
Device Data
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