Digital Power Monitor
with Clear Pin and ALERT Output
ADM1192
FEATURES
Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
ALERT output allows basic P-channel FET hot swap
up to 26 V
SETV input for setting overcurrent alert threshold
Programmable overcurrent filtering via TIMER pin
CLRB input pin
I2C® fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
FUNCTIONAL BLOCK DIAGRAM
ADM1192
SDA
V
VCC
0
12-BIT
ADC
I
I2C
SCL
1
A
SENSE
ADR
MUX
CURRENT
SENSE
AMPLIFIER
ALERT
ALERT
SETV
COMPARATOR
Power monitoring/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
CLRB
GND
05754-001
APPLICATIONS
TIMER
Figure 1.
3.15V TO 26V
RSENSE
GENERAL DESCRIPTION
An internal current sense amplifier senses voltage across the sense
resistor in the power path via the VCC pin and the SENSE pin.
A 12-bit ADC can measure the current seen in the sense resistor
and in the supply voltage on the VCC pin. An industry-standard
I2C interface allows a controller to read current and voltage
data from the ADC. Measurements can be initiated by an I2C
command. Alternatively, the ADC can run continuously, and
the user can read the latest conversion data whenever it is
required. Up to four unique I2C addresses can be created,
depending on the way the ADR pin is connected.
A SETV pin is also included. A voltage applied to this pin is
internally compared to the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier output exceeds the SETV voltage. This
event is detected at the ALERT block. The ALERT block then
charges up the external TIMER capacitor with a fixed current.
When this timing cycle is complete, the ALERT output asserts.
VCC
SENSE
ALERT
CONTROLLER
ALERT
ADM1192
SDA
SCL
SETV
CLRB
P = VI
SDA
SCL
CLRB
TIMER
GND
ADR
05754-013
The ADM1192 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip,
12-bit analog-to-digital converter (ADC), communicated
through an I2C interface.
Figure 2. Applications Diagram
The ALERT output can be used as a flag to warn a microcontroller or field programmable gate array (FPGA) of an
overcurrent condition. ALERT outputs of multiple ADM1192
devices can be tied together and used as a combined alert.
A basic P-channel FET hot swap circuit can be implemented
with the ALERT output. The value of the TIMER capacitor
should be set so that the charging time of this capacitor is much
longer than the period where a higher than nominal inrush
current may be flowing.
The ADM1192 is packaged in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADM1192
TABLE OF CONTENTS
Features .............................................................................................. 1
Identifying the ADM1192 on the I2C Bus............................... 10
Applications....................................................................................... 1
General I2C Timing.................................................................... 10
General Description ......................................................................... 1
Timing Diagrams ....................................................................... 11
Functional Block Diagram .............................................................. 1
Write and Read Operations ...................................................... 12
Revision History ............................................................................... 2
Quick Command........................................................................ 12
Specifications..................................................................................... 3
Write Command Byte ................................................................ 12
Absolute Maximum Ratings............................................................ 5
Write Extended Byte .................................................................. 13
Thermal Characteristics .............................................................. 5
Read Voltage and/or Current Data Bytes ................................ 14
ESD Caution.................................................................................. 5
ALERT Output............................................................................ 15
Pin Configuration and Function Descriptions............................. 6
SETV Pin ..................................................................................... 15
Typical Performance Characteristics ............................................. 7
Kelvin Sense Resistor Connection ........................................... 16
Voltage and Current Readback ..................................................... 10
Outline Dimensions ....................................................................... 17
Serial Bus Interface..................................................................... 10
Ordering Guide .......................................................................... 17
REVISION HISTORY
9/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADM1192
SPECIFICATIONS
VCC = 3.15 V to 26 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
VCC PIN
Operating Voltage Range, VVCC
Supply Current, ICC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis, VUVLOHYST
MONITORING ACCURACY 1
Current Sense Absolute Accuracy
Min
3.15
1.7
2.8
80
Unit
26
2
V
mA
V
mV
+1.45
−1.8
−2.8
Conditions
VCC rising
%
VSENSE = 75 mV
+1.8
%
VSENSE = 50 mV
0°C to +70°C
+2.8
%
VSENSE = 25 mV
0°C to +70°C
−5.7
+5.7
%
VSENSE = 12.5 mV
0°C to +70°C
−1.5
+1.5
%
VSENSE = 75 mV
0°C to +85°C
−1.8
+1.8
%
VSENSE = 50 mV
0°C to +85°C
−2.95
+2.95
%
VSENSE = 25 mV
0°C to +85°C
−6.1
+6.1
%
VSENSE = 12.5 mV
0°C to +85°C
−1.95
+1.95
%
VSENSE = 75 mV
−40°C to +85°C
−2.45
+2.45
%
VSENSE = 50 mV
−40°C to +85°C
−3.85
+3.85
%
VSENSE = 25 mV
−40°C to +85°C
−6.7
+6.7
%
VSENSE = 12.5 mV
−40°C to +85°C
mV
This is an absolute value to be used when
converting ADC codes to current readings;
any inaccuracy in this value is factored into
absolute current accuracy values (see
specs for Current Sense Absolute
Accuracy)
0°C to +70°C
VVCC = 3.0 V to 5.5 V
(low range)
0°C to +70°C
VVCC = 10.8 V to
16.5 V (high range)
0°C to +85°C
VVCC = 3.0 V to 5.5 V
(low range)
0°C to +85°C
VVCC = 10.8 V to
16.5 V (high range)
−40°C to +85°C
VVCC = 3.0 V to 5.5 V
(low range)
−40°C to +85°C
VVCC = 10.8 V to
16.5 V (high range)
These are absolute values to be used when
converting ADC codes to voltage readings;
any inaccuracy in these values is factored
into voltage accuracy values (see specs for
Voltage Accuracy)
105.84
−0.85
+0.85
%
−0.9
+0.9
%
−0.85
+0.85
%
−0.9
+0.9
%
−0.9
+0.9
%
−1.15
+1.15
%
VCC for ADC Full Scale,
Low Range (VRANGE = 1)
VCC for ADC Full Scale,
High Range (VRANGE = 0)
CLRB PIN
Logic Low Threshold, VCLRBL
Input Current for Logic Low Input, ICLRBL
Logic High Threshold, VCLRBH
Input Current for Logic High Input, ICLRBH
SENSE PIN
Input Current, ISENSE
Max
−1.45
VSENSE for ADC Full Scale
Voltage Sense Accuracy
Typ
6.65
V
26.52
V
0.8
−40
1.6
3
−1
6
V
μA
mV
μA
VCLRB = 1.6 V to 5.5 V
+1
μA
VSENSE = VVCC
−22
Rev. 0 | Page 3 of 20
VCLRB = 0 V to 0.8 V
0°C to +70°C
ADM1192
Parameter
SETV PIN
Overcurrent Trip Threshold
Overcurrent Trip, Gain {VSETV/(VVCC − VSENSE)}
Input Current, ISETVLEAK
Glitch Filter, tSETVGLITCH
TIMER PIN
Pull-Up Current (Overcurrent Fault), ITIMERUPOC
Pull-Down Current, ITIMERDN
Pin Threshold High, VTIMERH
ALERT PIN
Output Low Voltage, VALERTOL
Input Current, IALERT
ADR PIN
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
Set Address to 10, IADRHIGHZ
Set Address to 11, VADRHIGHV
Input Current for 00 Decode, IADRLOW
Input Current for 11 Decode, IADRHIGH
I2C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
Output Fall Time on SDA from VIHMIN to VILMAX
Maximum Width of Spikes Suppressed by Input
Filtering on SDA and SCL Pins
Input Current, II, on SDA/SCL When not Driving
Out a Logic Low
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, tSU;STA
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
Capacitive Load for Each Bus Line
1
Min
Typ
Max
Unit
Conditions
98
49.5
100
50
18
102
50.5
mV
mV
+1
μA
μs
VSETV = 1.8 V
VSETV = 0.9 V
VSETV = 0.9 V to 1.9 V
VSETV = 0.9 V to 1.9 V
−62
100
1.3
−78
1.325
μA
μA
V
(18.125 × VSENSE) > VSETV, VTIMER = 1 V
Normal Operation, VTIMER = 1 V
TIMER rising
0.05
1
0.1
1.5
+1
V
mA
μA
IALERT = −100 μA
IALERT = −2 mA
VALERT = VCC; ALERT asserted
0.8
160
V
kΩ
+0.3
μA
5.5
6
V
μA
μA
Low state
Resistor to ground state, load pin with
specified resistance for 01 decode
Open state, maximum load allowed on
ADR pin for 10 decode
High state
VADR = 2.0 V to 5.5 V
VADR = 0 V to 0.8 V
0.3 VBUS
IOL = 3 mA
CB = bus capacitance from SDA to GND
−1
3
−46
1.275
−1
0
80
120
−0.3
2
−40
3
−25
20 +
0.1 CB
50
0.4
250
V
V
V
ns
250
ns
−10
+10
μA
0.7 VBUS
5
400
600
1300
600
100
600
1300
900
400
pF
kHz
ns
ns
ns
ns
ns
ns
pF
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
Rev. 0 | Page 4 of 20
ADM1192
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC Pin
SENSE Pin
TIMER Pin
CLRB Pin
SETV Pin
ALERT Pin
SDA Pin, SCL Pin
ADR Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
THERMAL CHARACTERISTICS
Rating
30 V
30 V
−0.3 V to +6 V
−0.3 V to +6 V
30 V
30 V
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 20
θJA
137.5
Unit
°C/W
ADM1192
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
ALERT
SENSE 2
9
CLRB
8
ADR
GND 4
7
SDA
TIMER 5
6
SCL
SETV 3
TOP VIEW
(Not to Scale)
05754-003
ADM1192ARM
VCC 1
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VCC
2
SENSE
3
SETV
4
5
GND
TIMER
6
7
8
SCL
SDA
ADR
9
10
CLRB
ALERT
Description
Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout
(UVLO) circuit resets the ADM1192 when a low supply voltage is detected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
Input Pin. The voltage driven onto this pin is compared to the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert.
Chip Ground Pin.
Timer Input Pin. An external capacitor, CTIMER, sets the timing period for masking overcurrent conditions. This
timing period should be sufficient to allow the load charge up completely with maximum current at startup
without tripping an overcurrent fault.
I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four
different I2C addresses.
Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low.
Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition
is present. The level at which an overcurrent condition is detected depends on the voltage on the SETV pin.
Rev. 0 | Page 6 of 20
ADM1192
TYPICAL PERFORMANCE CHARACTERISTICS
1000
2.0
900
HITS PER CODE (1000 READS)
1.8
1.6
ICC (mA)
1.4
1.2
1.0
0.8
0.6
800
700
600
500
400
300
200
0.4
100
0
0
4
8
12
16
20
24
28
VCC (V)
2046
05754-021
0
Figure 4. Supply Current vs. Supply Voltage
2047
2048
2049
2050
CODE
05754-060
0.2
Figure 7. ADC Noise, Current Channel, Midcode Input, 1000 Reads
1000
2.0
900
HITS PER CODE (1000 READS)
1.8
1.6
ICC (mA)
1.4
1.2
1.0
0.8
0.6
800
700
600
500
400
300
200
0.4
100
0
–20
0
20
40
60
779
05754-022
80
TEMPERATURE (°C)
10 DECODE
782
783
Figure 8. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads
1000
01 DECODE 00 DECODE
HITS PER CODE (1000 READS)
900
800
700
600
500
400
300
200
100
0
–30
–25
–20
–15
–10
–5
0
5
IADR (µA)
10
3078
05754-026
VADR
11 DECODE
781
CODE
Figure 5. Supply Current vs. Temperature
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–35
780
3079
3080
3081
3082
CODE
Figure 9. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads
Figure 6. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options
Rev. 0 | Page 7 of 20
05754-062
0
–40
05754-061
0.2
ADM1192
0.60
4
0.55
3
0.50
0.45
ALERT LOW (V)
2
INL (LSB)
1
0
–1
0.40
0.35
0.30
0.25
0.20
0.15
–2
0.10
–3
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
–40
05754-023
0
–20
0
20
40
60
05754-047
0.05
–4
80
TEMPERATURE (°C)
Figure 10. INL for ADC
Figure 13. ALERT Output Low Voltage vs. Temperature @ 1 mA
1.0
4
3
0.8
OUTPUT LOW (V)
DNL (LSB)
2
1
0
–1
0.6
0.4
–2
0.2
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
05754-024
4
6
8
10
12
14
16
18
20
22
24
26
28
Figure 14. ALERT Output Low Voltage vs. Supply @ 1 mA
2.0
100
1.8
90
1.6
70
1.4
OUTPUT LOW (V)
80
60
50
40
1.2
1.0
0.8
30
0.6
20
0.4
10
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
VSETV (V)
1.4
1.6
1.8
2.0
05754-046
VLIM (mV)
2
VCC (V)
Figure 11. DNL for ADC
0
0
Figure 12. VLIM vs. VSETV
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
LOAD CURRENT (mA)
Figure 15. ALERT Output Low Voltage vs. Load Current
Rev. 0 | Page 8 of 20
05754-049
–4
05754-048
–3
2.0
1.8
1.8
1.6
1.6
HIGH
1.2
1.0
0.8
0.6
0.4
0.2
0
HIGH
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VCC (V)
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 17. Timer Threshold vs. Temperature
Figure 16. Timer Threshold vs. Supply Voltage
Rev. 0 | Page 9 of 20
80
05754-039
1.4
TIMER HIGH THRESHOLD (V)
2.0
05754-038
TIMER THRESHOLD (V)
ADM1192
ADM1192
VOLTAGE AND CURRENT READBACK
The ADM1192 contains the components to allow voltage and
current readback over an Inter-IC (I2C) bus. The voltage output
of the current sense amplifier and the voltage on the VCC pin
are fed into a 12-bit ADC via a multiplexer. The device can be
instructed to convert voltage and/or current at any time during
operation via an I2C command. When all conversions are
complete, the voltage and/or current values can be read out to
12-bit accuracy in two or three bytes.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
it or written to it. If the R/W bit is 0, the master writes to
the slave device. If the R/W bit is 1, the master reads from
the slave device.
SERIAL BUS INTERFACE
Control of the ADM1192 is carried out via the serial system
management bus (I2C). This interface is compatible with I2C
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.
2.
IDENTIFYING THE ADM1192 ON THE I2C BUS
The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four different
configurations available on the ADR pin that correspond to four
different I2C addresses for the two LSBs (see Table 5). This
scheme allows four ADM1192 devices to operate on a single I2C.
If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the
slave device what to expect next. It can be an instruction,
such as telling the slave device to expect a block write, or
it can be a register address that tells the slave where subsequent data is to be written.
Table 5. Setting I2C Addresses via the ADR Pin
ADR Configuration
Low state
Resistor to GND
Floating (unconnected)
High state
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a
slave device during a read operation. Before doing a read
operation, it may first be necessary to do a write operation
to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
Address
0x68
0x69
0x6A
0x6B
GENERAL I2C TIMING
3.
Figure 18 and Figure 19 show timing diagrams for general read
and write operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed later. The general I2C protocol operates as follows:
1.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-tohigh transition when the clock is high can be interpreted
as a stop signal.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream follows. All slave peripherals
connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
address (MSB first) plus an R/W bit that determines the
direction of the data transfer; that is, whether data is written
to or read from the slave device (0 = write, 1 = read).
Rev. 0 | Page 10 of 20
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is known
as a no acknowledge. The master then takes the data line
low during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
ADM1192
TIMING DIAGRAMS
9
1
9
1
SCL
0
SDA
0
1
1
A1
1
A0
D7
R/W
D6
D5
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D4
D2
D3
D0
D1
ACKNOWLEDGE BY
SLAVE
FRAME 2
COMMAND CODE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
FRAME 3
DATA BYTE
D3
D2
D1
D0
ACKNOWLEDGE BY STOP
BY
SLAVE
MASTER
FRAME N
DATA BYTE
05754-004
SDA
(CONTINUED)
2
Figure 18. General I C Write Timing Diagram
9
1
9
1
SCL
0
SDA
0
1
1
A1
1
A0
D7
R/W
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D2
D3
D0
D1
ACKNOWLEDGE BY
MASTER
FRAME 2
DATA BYTE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
FRAME 3
DATA BYTE
D2
D1
D0
D7
D6
D5
ACKNOWLEDGE BY
MASTER
D4
D3
FRAME N
DATA BYTE
D2
D1
D0
NO ACKNOWLEDGE STOP
BY
MASTER
2
Figure 19. General I C Read Timing Diagram
tLOW
tR
tHD;STA
tF
SCL
tHD;STA
tSU;STA
tHIGH
tHD;DAT
tSU;DAT
tSU;STO
tBUF
P
S
S
Figure 20. Serial Bus Timing Diagram
Rev. 0 | Page 11 of 20
P
05754-006
SDA
05754-005
SDA
(CONTINUED)
ADM1192
WRITE COMMAND BYTE
WRITE AND READ OPERATIONS
The I C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1192 are discussed in the sections that follow. Table 6
shows the abbreviations used in the command diagrams.
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
Table 6. I2C Abbreviations
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB =1 indicates an
extended register write (see the Write Extended Byte
section).
QUICK COMMAND
5.
The slave asserts an acknowledge on SDA.
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
6.
The master asserts a stop condition on SDA to end the
transaction.
Abbreviation
S
P
R
W
A
N
1.
Condition
Start
Stop
Read
Write
Acknowledge
No acknowledge
The master device asserts a start condition on SDA.
1
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
2
3
SLAVE
S ADDRESS W A
05754-007
1
2
3
4
5 6
SLAVE
COMMAND
S ADDRESS W A
A P
BYTE
05754-008
2
Figure 22. Write Command Byte
The seven LSBs of the command byte are used to configure and
control the ADM1192. Table 7 provides details of the function
of each bit.
Figure 21. Quick Command
Table 7. Command Byte Operations
Bit
Default
Name
Function
C0
0
V_CONT
Set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1192 asserts an acknowledge and returns all 0s in the returned data.
C1
0
V_ONCE
C2
0
I_CONT
C3
0
I_ONCE
C4
0
VRANGE
C5
C6
0
0
N/A
STATUS_RD
Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until ADC
conversion is complete.
Set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1192 asserts an acknowledge and returns all 0s in the returned data.
Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until ADC
conversion is complete.
Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage
divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for
an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
Unused.
Status Read. When this bit is set, the data byte read back from the ADM1192 is the STATUS byte. This contains
the status of the device alerts. See Table 15 for full details of the STATUS byte.
Rev. 0 | Page 12 of 20
ADM1192
WRITE EXTENDED BYTE
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
5.
The slave asserts an acknowledge on SDA.
6.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write.
7.
The slave asserts an acknowledge on SDA.
8.
The master asserts a stop condition on SDA to end the
transaction.
1
2
3
4
5
6
7 8
SLAVE
REGISTER
REGISTER
S ADDRESS W A ADDRESS A
A P
DATA
05754-009
In the write extended byte operation, the master device writes
to one of the three extended registers of the slave device, as follows:
Figure 23. Write Extended Byte
Table 9, Table 10, and Table 11 give details of each extended
register.
Table 8. Extended Register Addresses
A6
0
0
0
A5
0
0
0
A4
0
0
0
A3
0
0
0
A2
0
0
0
A1
0
1
1
A0
1
0
1
Extended Register
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit
0
Default
0
Name
EN_ADC_OC1
1
0
EN_ADC_OC4
2
1
EN_OC_ALERT
3
0
EN_OFF_ALERT
4
0
CLEAR
Function
Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register.
Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present and the TIMER pin has charged to
1.3 V, the OC_ALERT register captures and latches this condition.
Enables an alert if the HS operation is turned off by an operation that writes the SWOFF bit high. This
allows software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
Clears the OC_ALERT and ADC_ALERT status bits in the status register. These may immediately reset if
the source of the alert has not been cleared or disabled with the other bits in this register. This bit selfclears to 0 after the status register bits have been cleared.
Table 10. ALERT_TH Register Operations
Bit
7:0
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
number corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
Forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. 0 | Page 13 of 20
ADM1192
The ADM1192 can be set up to provide information in three
different ways (see the Write Command Byte section). Depending
on how the device is configured, the following data can be read
out of the device after a conversion (or conversions).
For cases where the master is reading voltage only or current
only, only two data bytes are read. Step 7 and Step 8 are not
required.
1
2
8
9 10
2
3
4
5
6
7 8
SLAVE
REGISTER
REGISTER
S ADDRESS R A ADDRESS A
N P
DATA
B7
V11
B6
V10
B5
V9
B4
V8
B3
V7
B2
V6
B1
V5
B0
V4
I11
I10
I9
I8
I7
I6
I5
I4
Converting ADC Codes to Voltage and Current Readings
V3
V2
V1
V0
I3
I2
I1
I0
The following equations can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.
Voltage Readback
Figure 25. Two-Byte Read from ADM1192
The ADM1192 digitizes voltage only. Two bytes are read out of
the device in the format shown in Table 13.
Table 13. Voltage Only Readback Format
Byte Contents
1
Voltage MSBs
2
Voltage LSBs
B7 B6 B5 B4 B3 B2
V11 V10 V9 V8 V7 V6
V3 V2 V1 V0 0
0
B1
V5
0
B0
V4
0
Voltage = (VFULLSCALE/4096) × Code
where:
VFULLSCALE = 6.65 (7:2 range) or 26.35 (14:1 range).
Code is the ADC voltage code read from the device (Bit V0
to Bit V11).
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor
Current Readback
The ADM1192 digitizes current only. Two bytes are read out of
the device in the format shown in Table 14.
Table 14. Current Only Readback Format
Byte Contents
1
Current MSBs
2
Current LSBs
7
B7
I11
I3
B6
I10
I2
B5 B4 B3 B2
I9 I8 I7 I6
I1 I0 0
0
B1
I5
0
B0
I4
0
The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
read bit (high).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master receives the first data byte.
5.
The master asserts an acknowledge on SDA.
6.
The master receives the second data byte.
7.
The master asserts an acknowledge on SDA.
8.
The master receives the third data byte.
9.
The master asserts a no acknowledge on SDA.
10. The master asserts a stop condition on SDA, and the
transaction ends.
where:
IFULLSCALE = 105.84 mV.
Code is the ADC current code read from the device (Bit I0 to
Bit I11).
Read Status Register
A single register of status data can also be read from the
ADM1192.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
read bit (high).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master receives the status byte.
5.
The master asserts an acknowledge on SDA.
1
2
3
4
5
SLAVE
S ADDRESS R A DATA 1 A
05754-012
3
6
05754-011
1
Table 12. Voltage and Current Readback Format
2
5
Figure 24. Three-Byte Read from ADM1192
The ADM1192 digitizes both voltage and current. Three bytes
are read out of the device in the format shown in Table 12.
Contents
Voltage
MSBs
Current
MSBs
LSBs
4
SLAVE
S ADDRESS R A DATA 1 A DATA 2 A DATA 3 N P
Voltage and Current Readback
Byte
1
3
05754-010
READ VOLTAGE AND/OR CURRENT DATA BYTES
Figure 26. Status Read from ADM1192
Table 15 shows the ADM1192 status registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the
ALERT_EN register (CLEAR).
Rev. 0 | Page 14 of 20
ADM1192
Table 15. Status Byte Operations
Name
ADC_OC
ADC_ALERT
2
OC
3
OC_ALERT
4
5
OFF_STATUS
OFF_ALERT
Function
An ADC-based overcurrent comparison has been detected on the last three conversions.
An ADC-based overcurrent trip has occurred, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN
register.
An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the
SETV input).
An overcurrent condition has caused the ALERT block to latch a fault, and the ALERT output has asserted. Cleared by
writing to Bit 4 of the ALERT_EN register.
Set to 1 by writing to the SWOFF bit of the CONTROL register.
An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
RSENSE
3.15V TO 26V
ALERT OUTPUT
The ALERT output is an open-drain pin with 30 V tolerance.
There are two uses for this output.
VCC
SENSE
Overcurrent Flag
CONTROLLER
ALERT
ADM1192
The ALERT pin can be connected to the general-purpose logic
input of a controller. Under normal operation, the ADM1192
drives this output low. When an overcurrent condition occurs,
the output asserts high. An external pull-up resistor should
be used.
3.15V TO 26V
P-CHANNEL FET
P = VI
SDA
SCL
SETV
SDA
SCL
CLRB
CLRB
TIMER
GND
RSENSE
ADR
05754-014
Bit
0
1
Figure 28. P-Channel FET Hot Swap Implementation
SETV PIN
VCC
SENSE
ALERT
CONTROLLER
ALERT
ADM1192
SDA
SCL
SETV
CLRB
P = VI
SDA
SCL
CLRB
GND
ADR
05754-013
TIMER
The SETV pin allows the user to adjust the current level that
trips the ALERT output. The output of the current sense amplifier
is compared with the voltage driven onto the SETV pin. If the
current sense amplifier output is higher than the SETV voltage,
the output of the comparator asserts. By driving a different voltage
onto the SETV pin, the ADM1192 detects an overcurrent condition
at a different current level, with a gain of 18. See Figure 12 for
an illustration of this relationship.
Figure 27. Using the ALERT Output as an Interrupt
ILOAD
RSENSE
Implementing a Basic Hot Swap Circuit
VCC
SENSE
ADM1192
A
CURRENT
SENSE
AMPLIFIER
APPLIED
VOLTAGE
SETV
ALERT
COMPARATOR
1.3V
Figure 29. SETV Operation
Rev. 0 | Page 15 of 20
ALERT
60µA
TIMER
05754-015
A basic P-channel FET hot swap circuit can be created. The
ALERT output should be connected to the GATE pin of a
P-channel FET connected in series with the power path. A pullup from GATE to source ensures that the P-channel FET GATE
is pulled up and the device held off as soon as power is applied.
When the ADM1192 powers up, the GATE is pulled low by the
ALERT output. A capacitor on the TIMER pin determines the
slew rate of the GATE at turn-on. Note that if a current fault
occurs at any point in operation, the ALERT output asserts
high, turning off the P-channel FET.
ADM1192
When the output of the SETV comparator asserts, this tells the
ALERT block to begin charging the external TIMER capacitor
with a 60 μA charging current. When the voltage on the TIMER
capacitor reaches 1 V, the charging cycle is complete. The ALERT
output then asserts (goes high). Different values of TIMER
capacitor generate different time delays between current faults
occurring and the ALERT output asserting. When using the
ALERT output to implement a hot swap circuit, the TIMER
capacitor should be chosen to generate a large enough startup
delay to allow the maximum inrush current to completely
charge up the load without tripping an ALERT fault.
This problem can be avoided by using a Kelvin sense connection.
This type of connection separates the current path through the
resistor and the voltage drop across the resistor. Figure 30 shows
the correct way to connect the sense resistor between the VCC
pin and the SENSE pin of the ADM1192.
SENSE RESISTOR
CURRENT
FLOW FROM
SUPPLY
CURRENT
FLOW TO
LOAD
KELVIN SENSE RESISTOR CONNECTION
KELVIN SENSE TRACES
VCC
SENSE
ADM1192
Figure 30. Kelvin Sense Connections
Rev. 0 | Page 16 of 20
05754-016
When using a low value sense resistor for high current measurement, the problem of parasitic series resistance can arise. The
lead resistance can be a substantial fraction of the rated resistance,
making the total resistance a function of lead length.
ADM1192
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
3.10
3.00
2.90
1
5.15
4.90
4.65
5
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.05
1.10 MAX
0.33
0.17
SEATING
PLANE
0.23
0.08
0.80
0.60
0.40
8°
0°
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 31. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1192-1ARMZ-R7 1
EVAL-ADM1192EBZ1
1
Temperature Range
−40°C to +85°C
Package Description
10-Lead MSOP
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 17 of 20
Package Option
RM-10
Branding
M5M
ADM1192
NOTES
Rev. 0 | Page 18 of 20
ADM1192
NOTES
Rev. 0 | Page 19 of 20
ADM1192
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05754-0-9/06(0)
Rev. 0 | Page 20 of 20