LINER LTC1040 Dual micropower comparator Datasheet

LTC1040
Dual Micropower
Comparator
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FEATURES
■
■
■
■
■
■
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DESCRIPTIO
Micropower
1.5µW (1 Sample/Second)
Power Supply Flexibility
Single Supply 2.8V to 16V
Split Supply ±2.8V to ±8V
Guaranteed Max Offset 0.75mV
Guaranteed Max Tracking Error Between Input
Pairs ± 0.1%
Input Common Mode Range to Both Supply Rails
TTL/CMOS Compatible with ±5V or Single 5V
Supply
Input Errors are Stable with Time and Temperature
■
■
■
In addition to switching power ON, a switched output is
provided to drive external loads during the comparator’s
active time. This allows not only low comparator power,
but low total system power.
Sampling is controlled by an external strobe input or an
internal oscillator. The oscillator frequency is set by an
external RC network.
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APPLICATIO S
■
The LTC®1040 is a monolithic CMOS dual comparator
manufactured using Linear Technology’s enhanced
LTCMOSTM silicon gate process. Extremely low operating
power levels are achieved by internally switching the
comparator ON for short periods of time. The CMOS
output logic holds the output information continuously
while not consuming any power.
Battery-Powered Systems
Remote Sensing
Window Comparator
BANG-BANG Controllers
Each comparator has a unique input structure, giving two
differential inputs. The output of the comparator will be
high if the algebraic sum of the inputs is positive and low
if the algebraic sum of the inputs is negative.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS™ is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
Window Comparator with Symmetric Window Limits
Typical LTC1040 Supply Current
vs Sampling Frequency
1000
VIN
+
–
+
–
COMP A
A OUT = “1” WHEN
VIN > VC + ∆
A + B = “1” WHEN
VC – ∆ ≤ VIN ≤ VC + ∆
VC
∆
+
–
+
–
COMP B
B OUT = “1” WHEN
VIN < VC – ∆
SUPPLY CURRENT, IS (µA)
LTC1040
VS = ±5V
100
10
1
0.10
0.01
0.1
REXT = 10M
EXTERNALLY STROBED
1
100
1,000
10
SAMPLING FREQUENCY, fS (Hz)
10,000
LTC1040 • TA02
LTC1040 • TA01
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LTC1040
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Total Supply Voltage (V+ to V –) ............................... 18V
lnput Voltage ........................ (V+ + 0.3V) to (V – – 0.3V)
Operating Temperature Range
LTC1040C ..................................... – 40°C ≤ TA ≤ 85°C
LTC1040M (OBSOLETE) .................... – 55°C to 125°C
Storage Temperature Range ................. – 55°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Output Short-Circuit Duration .......................Continuous
STROBE
1
18 V+
ON/OFF
2
17 VP-P
A+B
3
16 OSC
A OUT
4
15 BOUT
A1+
5
14 B1+
A1–
6
13 B1–
A2+
7
12 B2+
–
A2
8
11 B2–
GND
9
10 V–
N PACKAGE
18-LEAD PDIP
ORDER PART
NUMBER
LTC1040CN
LTC1040CSW
SW PACKAGE
18-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 120°C/W (N)
TJMAX = 125°C, θJA = 85°C/W (SW)
LTC1040MJ
LTC1040CJ
J PACKAGE
18-LEAD CERDIP
TJMAX = 150°C, θJA = 80°C/W
OBSOLETE PACKAGE
Consider the N18 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions: V+ = 5V, V – = – 5V, unless otherwise noted.
PARAMETER
CONDITIONS
VOS
Offset Voltage (Note 2)
Split Supplies ±2.8V to ±6V
Single Supply (V – = GND) 2.8V to 6V
●
±0.3
± 0.75
mV
Split Supplies ±6V to ±8V
Single Supply (V – = GND) 6V to 15V
●
±1
±4.5
mV
Tracking Error Between
Input Pairs (Notes 2 and 3)
Split Supplies ±2.8V to ±8V
Single Supplies (V – = GND) 2.8 to 16V
●
0.05
0.1
%
Input Bias Current
OSC = GND
RIN
Average Input Resistance
fS = 1kHz (Note 4)
CMR
Common Mode Range
PSR
Power Supply Range
IBIAS
MIN
LTC1040M/LTC1040C
TYP
MAX
SYMBOL
±0.3
UNITS
nA
●
20
●
V–
V+
Split Supplies
●
±2.8
±8
V
Single Supplies (V – = GND)
●
2.8
16
V
Power Supply ON Current (Note 5)
V + = 5V, VP-P On
●
1.2
3
mA
IS(OFF)
Power Supply OFF Current (Note 5)
V+
●
●
0.001
0.001
0.5
5
µA
µA
tD
Response Time (Note 6)
60
80
100
µs
VOH
VOL
A, B, A + B and
ON/OFF Outputs (Note 7)
Logic “1” Output Voltage
Logic “0” Output Voltage
2.4
4.4
0.25
0.4
V
V
IS(ON)
= 5V, VP-P Off
LTC1040C
LTC1040M
V + = 4.75V, lOUT = – 360µA
V + = 4.75V, lOUT = 1.6mA
●
●
30
MΩ
V
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LTC1040
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25°C. Test conditions: V+ = 5V, V – = – 5V, unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
VIL
STROBE Input (Note 7)
Logic “1” Input Voltage
Logic “0” Input Voltage
V + = 5.25V
V + = 4.75V
●
REXT
External Timing Resistor
Resistor Tied Between V + and OSC Pin
●
fS
Sampling Frequency
REXT = 1M, CEXT = 0.1µF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Applies over input voltage range limit and includes gain
uncertainty.
Note 3: Tracking error = (VIN1 – VIN2)/ VIN1.
Note 4: RIN is guaranteed by design and is not tested.
RIN = 1/(fS • 33pF).
LTC1040M/LTC1040C
TYP
MAX
2.0
1.6
1.0
UNITS
V
V
0.8
100
10,000
kΩ
5
Hz
Note 5: Average supply current = tD • lS(ON) • fS + (1 – tD x fS) • lS(OFF).
Note 6: Response time is set by an internal oscillator and is independent
of overdrive voltage.
Note 7: Inputs and outputs also capable of meeting EIA/JEDEC B series
CMOS specifications.
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TYPICAL PERFOR A CE CHARACTERISTICS
Peak Supply Current
vs Supply Voltage
Normalized Sampling Frequency
vs Supply Voltage and Temperature
NORMALIZED SAMPLING FREQUENCY
(fS/fS AT 5V, 25°C)
18
16
IS(ON) (mA)
14
12
25°C
10
–55°C
8
6
125°C
4
2
0
2
10
8
6
12
SUPPLY VOLTAGE, V+ (V)
4
14
R = 1M
C = 0.1µF
2.0
1.8
TA = 125°C
1.6
1.4
1.2
TA = 25°C
1.0
TA = –55°C
0
2
8
10 12
4
6
SUPPLY VOLTAGE, V+ (V)
14
10
CEXT = 0.1µF
1
0.1
100k
16
150
100
50
0
10
14
8
12
6
SUPPLY VOLTAGE, V+ (V)
1M
REXT (Ω)
16
LTL1040 • TPC04
VP-P Output Voltage
vs Load Current
1011
1010
109
108
107
1
10M
LT1040 • TPC03
TYPICAL OUTPUT VOLTAGE DROP, V+ –VP-P (V)
200
AVERAGE INPUT RESISTANCE, RIN (1/fS • 33pF) (Ω)
250
RESPONSE TIME, tD (µs)
CEXT = 0.05µF
Input Resistance
vs Sampling Frequency
TA = 25°C
4
CEXT = 0.01µF
LTC1040 • TPC02
Response Time
vs Supply Voltage
2
102
CEXT = 1µF
LTC1040 • TPC01
300
CEXT = 1000pF
0.8
0.6
16
Sampling Rate vs REXT, CEXT
103
2.2
SAMPLE RATE, fS (Hz)
20
10
102
103
SAMPLING FREQUENCY, fS (Hz)
104
LTC1040 • TPC05
0
0.2
0.4
0.6
V+ = 10V
0.8
V+ = 2.8V
1.0
V+ = 16V
1.2
1.4
V+ = 5V
1.6
1.8
2.0
0
1
2
3 4 5 6 7 8
LOAD CURRENT, IL (mA)
9
10
LTC1040 • TPC06
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LTC1040
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TYPICAL PERFOR A CE CHARACTERISTICS
Quick Hookup Guide
Response Time
vs Temperature
130
Self-Oscillating
V+ = 5V
1
RESPONSE TIME, t D (µs)
120
18
17
110
16
External Strobe
V+
EXTERNAL
STROBE
INPUT
REXT
1
18
V+
17
16
100
90
CEXT
LTC1040
LTC1040
80
70
60
9
50
40
–50
0
25
–25
50
75 100
AMBIENT TEMPERATURE, TA (°C)
10
9
10
125
LTC1040 • TPC08
LTC1040 • TPC07
TEST CIRCUIT
V+ (18)
+
–
+
–
VIN
OUTPUT
GND (9)
V– (10)
ALL INPUTS ON OPPOSITE COMPARATOR AT GROUND
LTC1040 • TA01
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BLOCK DIAGRA
VIN1
A1+ 5
A1– 6
VIN2
V+
18
A2+ 7
+
–
+
–
COMP A
VIN2
2 ON/OFF
4
A2– 8
VIN1
4 AOUT
B1+ 14
B1– 13
B2+ 12
B2– 11
+
–
+
–
3 A+B
COMP B
15 BOUT
4
V+
STROBE 1
TIMING
SWITCH
GENERATOR TIMING
OSC 16
POWER ON
80µs
VP-P
CIRCUIT
17 VP-P
9
GND
10
V–
LTC1040 • BD01
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LTC1040
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APPLICATIO S I FOR ATIO
The LTC1040 uses sampled data techniques to achieve its
unique characteristics. Some of the experience acquired
using classic linear comparators does not apply to this
circuit, so a brief description of internal operation is
essential to proper application.
For RS > 1OkΩ
The most obvious difference between the LTC1040 and
other comparators is the dual differential input structure.
Functionally, when the sum of inputs is positive, the
comparator output is high and when the sum of the inputs
is negative, the output is low. This unique input structure
is achieved with CMOS switches and a precision capacitor
array. Because of the switching nature of the inputs, the
concept of input current and input impedance needs to be
examined.
CIN
CIN + CS
This represents an error and can be made arbitrarily small
by increasing CS.
The equivalent input circuit is shown in Figure 1. Here, the
input is being driven by a resistive source, RS, with a
bypass capacitor, CS. The bypass capacitor may or may
not be needed, depending on the size of the source
resistance and the magnitude of the input voltage, VIN.
RS
VIN
CIN
≈ 33pF
S1
+
CS
∆V = VIN •
With the addition of CS, a second error term caused by the
finite input resistance of the LTC1040 must be considered.
Switches S1 and S2 alternately open and close, charging
and discharging CIN between VIN and ground. The
alternate charge and discharge of CIN causes a current to
flow into the positive input and out of the negative input.
The magnitude of this current is:
IIN = q • fS = VIN CIN fS
where fS is the sampling frequency. Because the input
current is directly proportional to input voltage, the LTC1040
can be said to have an average input resistance of:
RIN =
S2
–
For RS greater than 10kΩ, CIN cannot fully charge and a
bypass capacitor, CS, is needed. When switch S1 closes,
charge is shared between CS and CIN. The change in
voltage on CS because of this charge sharing is:
V–
LTC1040 DIFFERENTIAL INPUT
LTC1040 • AI01
Figure 1. Equivalent Input Circuit
For RS < 1Ok
Assuming CS is zero, the input capacitor, CIN, charges to
VIN with a time constant of RS CIN. When RS is too large,
CIN does not have a chance to fully charge during the
sampling interval (≈ 80µs) and errors will result. If RS
exceeds 10kΩ, a bypass capacitor is necessary to minimize errors.
VIN
1
1
=
=
IIN fS CIN fS • 33pF
(see typical curve of Input Resistance vs Sampling Frequency). A voltage divider is set up between RS and RIN
causing error.
The input voltage error caused by these two effects is:
CIN
RS
+
VERROR = VIN
CIN + CS RS + RIN
(
)
Example: fS = 10Hz, RS = 1MΩ,
CS = 1µF, VIN = 1V
VERROR = 1V
106
+
( 331 •• 1010–12
–6
6
10 + 3 • 109 )
= 33µV + 330µV = 363µV.
Notice that most of the error is caused by RIN. If the
sampling frequency is reduced to 1Hz, the voltage error is
reduced to 66µV.
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LTC1040
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APPLICATIO S I FOR ATIO
Minimizing Comparison Errors
Tracking Error
The two differential input voltages, V1 and V2, are converted to charge by the input capacitors CIN1 and CIN2 (see
Figure 2). The charge is summed at the virtual ground
point; if the net charge is positive, the comparator output
is high and if negative, it is low. There is an optimum way
to connect these inputs, in a specific application, to
minimize error.
Tracking error is caused by the ratio error between CIN1
and CIN2 and is expressed as a percentage. For example,
consider Figure 3a with VREF = 1V. Then at null,
VIN = VREF
CIN1
= 1V ± 1mV
CIN2
because CIN1 is guaranteed to equal CIN2 to within 0.1%.
CIN1
S1
+
VIRTUAL
GROUND
+
–
+
–
VREF
V1
–
S2
VIN
CIN2
+
–
+
–
VREF
VIN
+
V2
(a) OK
–
(b) Optimum
Figure 3. Two Ways to Do It
LTC1040 • TA03
LTC1040 DUAL DIFFERENTIAL INPUT
LTC1040 • AI02
Figure 2. Dual Differential Equivalent Input Circuit
Ignoring internal offset, the LTC1040 will be at its switching point when:
V1 • CIN1 + V2 • CIN2 = 0.
Optimum error will be achieved when the differential
voltages, V1 and V2, are individually minimized. Figure 3
shows two ways to connect the LTC1040 to compare an
input voltage, VIN, to a reference voltage, VREF. Using the
above equation, each method will be at null when:
Common Mode Range
The input switches of the LTC1040 are capable of
switching to either the V + or V – supply. This means that the
input common mode range includes both supply rails.
Many applications, not feasible with conventional comparators, are possible with the LTC1040. In the load
current detector shown in Figure 4, a 0.1Ω resistor is used
to sense the current in the V + supply. This application
requires the dual differential input and common mode
capabilities of the LTC1040.
(a) (VREF – 0V) CIN1 – (0V – VIN) CIN2 = 0
or VIN = VREF (CIN1/CIN2)
IL
(b) (VREF – VIN) CIN1 – (0V – 0V) CIN2 = 0
or VIN = VREF.
Notice that in method (a) the null point depends on the
ratio of CIN1/CIN2, but method (b) is independent of this
ratio. Also, because method (b) has zero differential input
voltage, the errors due to finite input resistance are
negligible. The LTC1040 has a high accuracy capacitor
array and even the non-optimum connection will only
result in ± 0.1% more error, worst-case compared to the
optimum connection.
0.1Ω
+
VS
100mV
–
+ 1/2
– LTC1040
+
RL
OUT
OUT = HI IF IL > 1A
OUT = LO IF IL < 1A
LTC1040 • AI04
Figure 4. Load Current Detector
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LTC1040
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APPLICATIO S I FOR ATIO
Offset Voltage Error
The errors due to offset, common mode, power supply
variation, gain and temperature are all included in the
offset voltage specification. This makes it easy to compute
the error when using the LTC1040.
The VP-P output voltage is not precise (see VP-P Output
Voltage versus Load Current curve). There are two ways
VP-P can be used to power external networks without
excessive errors: (1) ratiometric networks and (2) fast
settling references.
Example: error computation for Figure 4.
Assume: 2.8V ≤ VS ≤ 6V.
In a ratiometric network, the inputs are all proportional to
VP-P (see Figure 6). Consequently, for small changes, the
absolute value of VP-P does not affect accuracy.
Then total worst-case error is:
It is critical that the inputs to the LTC1040 completely
settle within 4µs of the start of the comparison cycle and
that they do not change during the 80µs ON time. When
driving resistive networks with VP-P, capacitive loading on
IL (ERROR) = ± (100mV • 0.001 + 0.5mV) •
↑
↑
Tracking Error
VOS
6mA
IL (ERROR)% =
• 100 = ± 0.6%.
1A
1A
= ±6mA
100mV
VP-P OUTPUT
Note: If source resistance exceeds 10k, bypass
capacitors should be used and the associated errors must
be included.
–
VIN
+
VTRIP
OUTPUT
LTC1040 • AI06
Pulsed Power (VP-P) Output
It is often desirable to use comparators with resistive
networks such as bridges. Because of the extremely low
power consumption of the LTC1040, the power consumed
by these resistive networks can far exceed that of the
device itself.
At low sample rates the LTC1040 spends most of its time
off. To take advantage of this, a pulsed power (VP-P) output
is provided. VP-P is switched to V + when the comparator
is on and to a high impedance (open circuit) when the
comparator is off. The ON time is nominally 80µs.
Figure 5 shows the VP-P output circuit.
Figure 6. Ratiometric Network Driven by VP-P
the network should be minimized to meet the 4µs settling
time requirement. It is not recommended that VP-P be used
to drive networks with source impedances, as seen by the
inputs, of greater than 10kΩ.
In applications where an absolute reference is required,
the VP-P output can be used to drive a fast settling
reference. The LT1009 2.5V reference, ideal in this
application, settles in approximately 2µs (see Figure 7).
The current through R1 must be large enough to supply
the LT1009 minimum bias current (≈1mA) and the load
current, IL.
V+
18
VP-P OUTPUT
R1
Q1 P1
VIN
R2
80µs
COMPARATOR ON TIME
LT1009
9
GND
+
– 1/2
+ LTC1040
–
IL
R3
+
– 1/2
+ LTC1040
–
17
VP-P
LTC1040 • AI05
Figure 5. VP-P Output Switch
LTC1040 • AI07
Figure 7. Driving Reference with VP-P Output
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LTC1040
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APPLICATIO S I FOR ATIO
Output Logic
In addition to the normal outputs (AOUT and BOUT), two
additional outputs, A + B and ON/0FF, are provided (see
Figure 8 and Table 1). All logic is powered from V+ and
ground, thus input and output logic levels are independent
of the V – supply. The LTC1040 is directly compatible with
CMOS logic and is TTL compatible for 4.75V ≤ V + ≤ 5.25V.
No external pull-up resistors are required.
Table 1. Output Logic Truth Table
ΣA INPUTS
+
+
–
–
ΣB INPUTS
AOUT
BOUT
A+B
ON/OFF
+
–
+
–
H
H
L
L
H
L
H
L
L
L
L
H
L
L
H
I*
*I = indeterminate. When both A and B outputs are low, the ON/OFF output
remains in the state it was in prior to entering AOUT = BOUT = L.
Because of the sampling nature of the LTC1040, some
sensitivity exists between the offset voltage and the falling
edge of the input strobe. When the falling edge of the
strobe signal falls within the comparator’s active time
(80µs after rising edge), offset changes of as much as 2mV
can occur. To eliminate this problem, make sure the strobe
pulse width is greater than the response time, tD.
Using Internal Strobe
An internal oscillator allows the LTC1040 to strobe itself.
The frequency of oscillation, and hence sampling rate, is
set by an external RC network (see typical curve of
Sampling Rate vs REXT, CEXT).
For self-oscillation, the STROBE pin must be tied to
ground. The external RC network is connected as shown
in Figure 9.
Using External Strobe
To assure oscillation, REXT must be between 100k and
10M. There is no limit to the size of CEXT.
A positive pulse on the strobe input, with the 0SC input tied
to ground, will initiate a comparison cycle. The STROBE
input is edge-sensitive and pulse widths of 50ns will
typically trigger the device.
REXT is very important in determining the power
consumption. The average voltage at the oscillator pin is
approximately V +/2. The power consumed by REXT is then:
PREXT = (V +/2)2/REXT.
1
18
2 ON/OFF
V+
17
REXT
16
CEXT
LTC1040
COMPARATOR A
OUTPUT
D
C
COMPARATOR B
OUTPUT
Q
4
A OUT
3
A+B
9
10
D
C
Q
15 BOUT
LTC1040 • AI09
Figure 9. External RC Connection
STROBE
Example: REXT = 1M, V + 5V, PREXT = (2.5)2/106 =
6.25 • 10–6W.
80µs
LTC1040 • AI08
Figure 8. LTC1040 Logic Diagram
This is about four times the power consumed by the
LTC1040 at V + = 5V and fS = 1 sample/second. Where
power is a premium REXT should be made as large as
possible. Note that the power consumed by REXT is not a
function of fS or CEXT.
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LTC1040
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TYPICAL APPLICATIO S
Complete Heating/Cooling Automatic Thermostat
5V AT 0.85µA
17
18
20M
4.32k
LTC1040
4.99k
5
6
7
8
†
+
–
+
–
4
COMP A
82k*
3
5k
TEMP
ADJUST
14
13
12
11
6.81k
+
–
+
–
15
COMP B
16
0.1µF
THERMISTOR # 44007
YELLOW SPRINGS INSTRUMENT CO., INC.
* HYSTERESIS = 5V • 82k = 20mV
20M
COOL
10M
82k*
†
HEAT
9
SEPARATION
(20mV)
10
20M
LTC1040 • TA03
AIRCONDITIONING ON
28°C
TEMPERATURE
HYSTERESIS
AIRCONDITIONING OFF
HEATER OFF
SEPARATION
HYSTERESIS
HEATER ON
27°C
HEAT
COOL
TIME
Window Comparator with Independent Window Limits and
Fully Floating Differential Input
LTC1040 • TA04
Hysteresis Comparator with Fully Floating Differential Input
V+
LTC1040
VIN
VU
+
–
+
–
COMP A
VIN
A OUT = “1” WHEN
VIN > VU
VTRIP
R1
10k
*
A+B = “1” WHEN
VU ≥ VIN ≥ VL
VL
+
–
+
–
COMP B
B OUT = “1” WHEN
VIN < VL
OUT
R2
2.49MΩ
V
R2 + (5V) R1
OUT = “0” WHEN VIN > VU = TRIP
= 0.996 VTRIP + 20mV
R1 + R2
OUT = “1” WHEN VIN < V1 =
LTC1040 • TA05
+
–1/2 LTC1040
+
–
VTRIP R2
R1 + R2
= 0.996VTRIP
* TO CENTER HYSTERESIS ABOUT VTRIP, FORCE THIS INPUT TO
HYSTERESIS/2 (10mV)
LTC1040 • TA06
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LTC1040
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TYPICAL APPLICATIO S
The LTC1040 as a Linear Amplifier
With a simple RC filter, the LTC1040 can be made to
function as a linear amplifier. By filtering the logic output
and feeding it back to the negative input, the loop forces
the output duty cycle [tON/(tON + tOFF)] so that VOUT equals
VIN (Figure 10).
should be set to 0.5mV to 1mV for best results. Notice that
the higher the sampling frequency, fS, the lower RC can be.
This is important because the RC filter also sets the loop
response. A convenient way to keep fS as high as possible
under all conditions is to connect a 100k resistor to pin 16
(OSC) with no capacitance to ground.
The RC time constant is set to keep the ripple on the output
small. The maximum output ripple is: ∆V = V +/fSRC and
V+
VIN
+
–1/2 LTC1040
+
–
V+
R
VOUT
0V
C
VOUT = V+
t OFF
t ON
tON
tON + tOFF
LTC1040 • TA08
LTC1040 • TA07
Figure 10. The LTC1040 as a Linear Amplifier
2-Wire 0°C to 100°C Temperature Transducer with 4mA to 20mA Output
12V TO 40V
0°C = 4mA
100°C = 20mA
V+
R
LM134
V–
43
1N914
1k
ZERO
ADJUST
3200
6
430Ω
100k
6250
6
5
7
8
LT1019-5
†
†
4
18k
16
–
+ 1/2
– LTC1040
+
18
4 1M
9
2N6657
+
1µF
10
50Ω
+
10µF
5k
† YELLOW
SPRINGS INSTRUMENT
PART NO. 44201
ACCURACY =
182Ω
RETURN
FULL-SCALE
ADJUST
±0.1°C
+
= ±0.3°C
±0.2°C
CIRCUIT ERROR
TRANSDUCER
AT 25°C
ERROR
LTC1040 • TA09
1040fa
10
LTC1040
U
PACKAGE DESCRIPTIO
J Package
18-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
.960
(24.384)
MAX
.005
(0.127)
MIN
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
18
17
16
15
14
13
12
11
10
.220 – .310
(5.590 – 7.870)
.025
(0.635)
RAD TYP
.045 – .065
(1.143 – 1.650)
FULL LEAD
OPTION
3
2
1
5
4
6
7
8
9
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
.015 – .060
(0.380 – 1.520)
.008 – .018
(0.203 – 0.457)
0° – 15°
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.045 – .065
(1.143 – 1.651)
.125
(3.175)
MIN
.100
(2.54)
BSC
.014 – .026
(0.360 – 0.660)
J18 0801
OBSOLETE PACKAGE
N Package
18-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.900*
(22.860)
MAX
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
.255 ± .015*
(6.477 ± 0.381)
.130 ± .005
(3.302 ± 0.127)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.020
(0.508)
MIN
.065
(1.651)
TYP
.120
(3.048)
MIN
.005
(0.127)
MIN
.100
(2.54)
BSC
.018 ± .003
(0.457 ± 0.076)
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
N18 1002
1040fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1040
U
TYPICAL APPLICATIO S
Analog Multiplier/Divider
Single + 5V Voltage-to-Frequency Converter
5V
VREF (5V)
4
VC
15
18
5
6
7
8
VIN
100k
10k
3
V1
V2
VA
5
6
7
8
16
+
– 1/2
+ LTC1040
–
9
fOUT
1
1/4 74C00
100k
10µF
16
4
1/4 74C00
4
9
VOUT
+
18
18
+
– 1/2
+ LTC1040
–
10
LTC1043
fIN
+
10
VB*
1µF
14
13
fOUT (AVERAGE) = fIN
10k
12
VIN
±0.1% FS
VREF
LTC1040 • TA11
+
10µF
17
ACCURACY = ±10mV NO TRIM
* VB MUST BE > VA + (V1 – V2)
VOUT = (VA + V1 – V2) • VC
VB
LTC1040 • TA10
U
PACKAGE DESCRIPTIO
SW Package
18-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.447 – .463
(11.354 – 11.760)
NOTE 4
N
18
17
16
15
14
13
12
11
10
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
1
2
3
4
5
6
7
.093 – .104
(2.362 – 2.642)
8
9
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
.050
(1.270)
BSC
NOTE 3
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S18 (WIDE) 0502
1040fa
12
Linear Technology Corporation
LW/TP 1202 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 1991