A1225, A1227, and A1229 Hall Effect Latch for High Temperature Operation Features and Benefits Description ▪ Symmetrical switchpoints ▪ Superior temperature stability ▪ Operation from unregulated supply ▪ Open-drain 25 mA output ▪ Reverse Battery protection ▪ Activate with small, commercially available permanent magnets ▪ Solid-state reliability ▪ Small size ▪ Resistant to physical stress ▪ Enhanced ESD structures result in 8 kV HBM ESD performance without external protection components ▪ Internal protection circuits enable 40 V load dump compliance without external protection components These Hall-effect latches are extremely temperature-stable and stress resistant sensor ICs especially suited for operation over extended temperature ranges to 150°C. Superior hightemperature performance is made possible through a novel Schmitt trigger circuit that maintains operate and release point symmetry by compensating for temperature changes in the Hall element. Additionally, internal compensation provides magnetic switchpoints that become more sensitive with temperature, hence offsetting the usual degradation of the magnetic field with temperature. The symmetry capability makes these devices ideal for use in pulse-counting applications where duty cycle is an important parameter. The three basic devices (A1225, A1227, and A1229) are identical except for magnetic switchpoints. Each device includes on a single silicon chip a voltage regulator, Hall-voltage generator, temperature compensation circuit, signal amplifier, Schmitt trigger, and a buffered open-drain output to sink up to 25 mA. The on-board regulator permits operation with supply voltages of 3.8 to 24 V. Packages: 3-pin SOT89 (suffix LT) and 3-pin SIP (suffix UA) The first character of the part number suffix determines the device operating temperature range. Suffix L is for –40°C to 150°C. Two package styles provide a magnetically optimized package for most applications. Suffix LT is a miniature SOT89/ TO-243AA transistor package for surface-mount applications, suffix UA is a three-lead ultra-mini-SIP. Both packages are lead (Pb) free with 100% matte tin leadframe plating. Not to scale Functional Block Diagram Regulator VCC To All Subcircuits Hall Chopping Logic Clock / Logic VOUT AMP Anti-aliasing LP-Filter Tuned Filter GND A1225-DS A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Selection Guide Packing* Part Number Package A1225LLTTR-T 7-in. reel, 1000 pieces/reel 3-pin SOT89 surface mount A1225LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1227LLTTR-T 7-in. reel, 1000 pieces/reel 3-pin SOT89 surface mount A1227LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1229LLTTR-T 7-in. reel, 1000 pieces/reel 3-pin SOT89 surface mount A1229LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole Ambient Temperature, TA BRP(min) (G) BOP(max) (G) –40°C to 150°C –300 300 –40°C to 150°C –175 175 –40°C to 150°C –200 200 *Contact Allegro® for additional packaging options. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 30 V Reverse Supply Voltage VRCC –30 V Output Off Voltage VOUT 30 V Reverse Output Voltage VROUT –0.5 V Continuous Output Current IOUT(SINK) 25 mA –40 to 150 ºC TJ(max) 165 ºC Tstg –65 to 170 ºC Operating Ambient Temperature TA Maximum Junction Temperature Storage Temperature Range L Pin-out Diagrams Package LT 1 2 Package UA Terminal List Table Number Name Function 1 VCC Input power supply 2 GND Ground 3 VOUT Output signal 3 1 2 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation ELECTRICAL CHARACTERISTICS Valid at TA = –40°C to 150°C, CBYPASS = 0.1 μF, VCC = 12 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ.1 Max. Unit2 Electrical Characteristics Supply Voltage Supply Current VCC ICC Operating; TJ ≤ 165°C B < BRP (Output off) 3.8 – – 24 V 6 mA B > BOP (Output on) – – 6 mA Supply Zener Voltage VZ(sup) ICC = 9 mA, TA = 25°C 28 – – V Reverse Battery Current IZ(sup) VRCC = –28 V, TA = 25°C –5 – – mA – – 12 μs – HIGH – – – 400 – kHz Power-On Time3 tPO Power-On State POS Chopping Frequency fchop B < BOP Output Stage Characteristics Output Saturation Voltage Output Leakage Current Output Rise Time3,4 Output Fall Time3,4 Output Zener Voltage IOUT = 20 mA – 175 400 mV IOFF VOUT = 24 V, B < BRP – <1 10 μA tr RL= 820 Ω, CL= 20 pF – 200 2000 ns tf RL= 820 Ω, CL= 20 pF – 200 2000 ns VZ(out) IOUT = 3 mA, TA = 25°C 30 – – V VOUT(sat) Magnetic Characteristics A1225 Operate Point BOP A1227 A1229 A1225 Release Point BRP A1227 A1229 A1225 Hysteresis (BOP – BRP) BHYS A1227 A1229 TA = 25°C 170 – 270 G Over operating temperature range 140 – 300 G 50 – 150 G TA = 25°C Over operating temperature range TA = 25°C Over operating temperature range 50 – 175 G 100 – 180 G 80 – 200 G TA = 25°C –270 – –170 G Over operating temperature range –300 – –140 G TA = 25°C –150 – –50 G Over operating temperature range –175 – –50 G TA = 25°C –180 – –100 G Over operating temperature range G –200 – –80 TA = 25°C 340 – 540 G Over operating temperature range 280 – 600 G 300 G – 350 G TA = 25°C 100 Over operating temperature range 100 TA = 25°C 200 – 360 G Over operating temperature range 160 – 400 G 1Typical data are at TA = 25°C and VCC = 12 V, and are for design estimations only. G (gauss) = 0.1 mT (millitesla). 3Minimum and maximum specifications verified by bench characterization and not guaranteed by Allegro final test. 4C = oscilloscope probe capacitance. L 21 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* RθJA Package Thermal Resistance Value Units Package LT, 1-layer PCB with copper limited to solder pads 180 ºC/W Package LT, 2-layer PCB with 0.94 in2 copper each side 78 ºC/W Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W *Additional thermal information available on Allegro website. Maximum Allowable VCC (V) Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VCC(max) 1-layer PCB, Package LT (RθJA = 180 ºC/W) 1-layer PCB, Package UA (RθJA = 165 ºC/W) 2-layer PCB, Package LT (RθJA = 78 ºC/W) VCC(min) 20 40 60 80 100 120 140 160 180 160 180 TA (ºC) Power Dissipation, PD (m W) Power Dissipation 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 2 (R -lay θJ A er = PC 78 B ºC , Pa /W ck ) ag 1-la (R yer P CB θJA = 165 , Pac 1-la ºC/ kage W) (R yer P UA CB θJA = 180 , Pac ºC/ kage W) LT 20 40 60 e LT 80 100 120 Temperature (°C) 140 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Characteristic Performance A1225, A1227, and A1229 Electrical Characteristics Average Supply Current (On) versus Ambient Temperature Average Supply Current (On) versus Supply Voltage 6.0 6.0 5.5 5.5 5.0 5.0 4.5 4.0 VCC (V) 3.5 3.8 4.5 12 24 3.0 2.5 2.0 ICC(av) (mA) ICC(av) (mA) 4.5 4.0 –40 3.0 25 2.5 2.0 1.5 1.5 1.0 1.0 0.5 0.5 150 0 0 - 60 TA (°C) 3.5 - 40 - 20 0 20 40 60 80 2 100 120 140 160 6 10 TA (°C) Average Supply Current (Off) versus Ambient Temperature 5.5 5.5 5.0 5.0 VCC (V) 4.0 3.5 3.8 4.5 12 24 3.0 2.5 2.0 ICC(av) (mA) ICC(av) (mA) 26 4.5 4.5 4.0 TA (°C) 3.5 –40 3.0 25 2.5 2.0 1.5 1.5 1.0 1.0 0.5 0.5 150 0 0 - 40 - 20 0 20 40 60 80 2 100 120 140 160 6 10 TA (°C) 14 18 22 26 VCC (V) Average Output Saturation Voltage versus Supply Voltage Average Output Saturation Voltage versus Ambient Temperature 300 300 250 250 200 VCC (V) 3.8 4.5 12 24 150 100 VOUT(sat) (mV) VOUT(sat) (mV) 22 Average Supply Current (Off) versus Supply Voltage 6.0 200 TA (°C) –40 150 25 100 150 50 50 0 0 - 60 18 VCC (V) 6.0 - 60 14 - 40 - 20 0 20 40 60 TA (°C) 80 100 120 140 160 2 6 10 14 18 22 26 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation A1225 Magnetic Characteristics Operate Point versus Ambient Temperature Operate Point versus Supply Voltage 300 300 280 280 260 VCC (V) 240 3.8 12 24 220 200 BOP (G) BOP (G) 260 –40 220 25 150 200 180 180 160 160 140 - 60 - 40 - 20 TA (°C) 240 140 0 20 40 60 80 100 120 140 160 2 6 10 TA (°C) 22 26 Release Point versus Supply Voltage - 140 -140 - 160 -160 - 180 -180 - 200 VCC (V) - 220 3.8 12 24 - 240 BRP (G) BRP (G) 18 VCC (V) Release Point versus Ambient Temperature -200 TA (°C) -220 –40 25 -240 150 - 260 -260 - 280 -280 - 300 -300 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 TA (°C) 18 22 Switchpoint Hysteresis versus Supply Voltage 600 560 560 520 520 480 VCC (V) 440 3.8 12 24 400 BHYS (G) 600 480 TA (°C) 440 –40 25 400 360 360 320 320 280 - 60 - 40 - 20 14 VCC (V) Switchpoint Hysteresis versus Ambient Temperature BHYS (G) 14 150 280 0 20 40 60 TA (°C) 80 100 120 140 160 2 6 10 14 18 22 26 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation A1227 Magnetic Characteristics Operate Point versus Ambient Temperature Operate Point versus Supply Voltage 175 175 163 163 150 150 VCC (V) 125 3.8 12 24 113 100 138 BOP (G) BOP (G) 138 –40 113 25 100 150 88 88 75 75 63 63 50 - 60 - 40 - 20 TA (°C) 125 50 0 20 40 60 80 100 120 140 160 2 6 10 TA (°C) 22 26 Release Point versus Supply Voltage -50 -50 -63 -63 -75 -75 -88 -100 VCC (V) -113 3.8 12 24 -125 -138 BRP (G) -88 BRP (G) 18 VCC (V) Release Point versus Ambient Temperature -100 TA (°C) -113 –40 -125 25 -138 150 -150 -150 -163 -163 -175 -175 - 60 - 40 - 20 0 20 40 60 2 80 100 120 140 160 6 10 TA (°C) 18 22 26 Switchpoint Hysteresis versus Supply Voltage 350 350 325 325 300 300 275 VCC (V) 225 3.8 12 24 200 175 BHYS (G) 275 250 250 TA (°C) 225 –40 150 125 20 40 60 TA (°C) 80 100 120 140 160 150 175 125 0 25 200 150 100 - 60 - 40 - 20 14 VCC (V) Switchpoint Hysteresis versus Ambient Temperature BHYS (G) 14 100 2 6 10 14 18 22 26 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation A1229 Magnetic Characteristics Operate Point versus Ambient Temperature Operate Point versus Supply Voltage 200 200 190 190 180 180 170 170 VCC (V) 150 3.8 12 24 140 130 120 160 BOP (G) BOP (G) 160 TA (°C) 150 –40 140 25 130 150 120 110 110 100 100 90 90 80 - 60 - 40 - 20 80 0 20 40 60 80 100 120 140 2 6 10 TA (°C) Release Point versus Ambient Temperature 22 26 Release Point versus Supply Voltage -80 - 90 -90 - 100 - 100 - 110 - 110 - 120 VCC (V) - 130 3.8 12 24 - 140 - 150 - 160 BRP (G) BRP (G) 18 VCC (V) - 80 - 120 - 130 TA (°C) - 140 –40 - 150 25 - 160 150 - 170 - 170 - 180 - 180 - 190 - 190 - 200 - 60 - 40 - 20 - 200 0 20 40 60 80 100 120 140 2 6 10 TA (°C) 380 380 360 360 340 340 320 300 VCC (V) 280 3.8 12 24 260 240 BHYS (G) 400 TA (°C) 280 –40 260 25 240 150 220 200 180 180 160 - 60 - 40 - 20 160 40 60 26 300 200 TA (°C) 22 320 220 20 18 Switchpoint Hysteresis versus Supply Voltage 400 0 14 VCC (V) Switchpoint Hysteresis versus Ambient Temperature BHYS (G) 14 80 100 120 140 160 2 6 10 14 18 22 26 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Functional Description and Application Information Switching Behavior The output of the A1225, A1227, and A1229 devices switches low (turns on) when a magnetic field perpendicular to the Hall element exceeds the operate point threshold, BOP (see figure 1). After turn-on, the output is capable of sinking 25 mA and the output voltage is VOUT(sat). Notice that the device latches; that is, a south pole of sufficient strength towards the branded surface of the device turns the device on, and the device remains on with removal of the south pole. Application Information The simplest form of magnet that will operate these devices is a ring magnet, as shown in figure 2. Other methods of operation are possible. In three-wire applications the device output is connected through a pull-up resistor to the supply pin or separate battery voltage (figure 3). Switching of the output signal indicates sufficient change of the magnetic field. When the magnetic field is reduced below the release point, BRP , the device output goes high (turns off). The difference between the magnetic operate point and release point is the hysteresis, BHYS, of the device. This built-in hysteresis allows clean switching of the output, even in the presence of external mechanical vibration and electrical noise. When the device is powered-on in the hysteresis range, less than BOP and higher than BRP, the device output goes high. The correct output state is attained after the first excursion beyond BOP or BRP . V+ VOUT Figure 2. Typical magnetic target configuration using a ring magnet Switch to Low Switch to High VCC RPULLUP VOUT(sat) BOP B– BRP 0 VPULLUP V+ A122x B+ VOUT VCC CBYPASS GND Device Output CL (Optional) BHYS Figure 1. Output switching characteristics Figure 3. Typical 3-wire application circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the Hall sensor IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high-frequency sampling clock. For the demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signalprocessing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-Aliasing LP Filter Tuned Filter Figure 4. Chopper stabilization technique Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Package LT 3-Pin SOT-89 +0.13 4.47 –0.08 1.73 ±0.10 2.50 2.00 +0.03 0.41 –0.06 E 2.24 B D 0.38 MIN 0.80 E 6° REF 1.14 +0.10 4.14 –0.20 +0.03 2.57 –0.28 2.16 REF 2.60 Parting Line 4.60 1.20 10° REF 1 2 3 1.04 ±0.15 10° REF 1.50 C Branded Face Basic pads for low-stress, not self-aligning Additional pad for low-stress, self-aligning Additional area for IPC reference layout +0.15 1.45 –0.05 +0.05 0.43 –0.07 0.70 PCB Layout Reference View +0.05 0.51 –0.07 NN 2X 1.50 NOM 1 A Standard Branding Reference View = Supplier emblem N = Last two digits of device part number Updated package drawing only. Allegro package assembly tooling has not changed. For Reference Only; not for tooling use (reference DWG-9064) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Branding scale and appearance at supplier discretion B Gate and tie bar burr area C Reference land pattern layout; All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances D Active Area Depth, 0.77 mm E Hall element; not to scale Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A1225, A1227 and A1229 Hall Effect Latch for High Temperature Operation Package UA 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.04 1.52 ±0.5 1.44 E Mold Ejector Pin Indent +0.08 3.02 –0.05 E Branded Face NN 45° 1 2.16 MAX D Standard Branding Reference View = Supplier emblem N = Last two digits of device part number 0.79 REF A 0.51 REF 1 2 3 +0.03 0.41 –0.06 15.75 ±0.51 For Reference Only; not for tooling use (reference DWG-9049) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar pro Exact case and lead configuration at supplier discretion within l A Dambar removal protrusion (6X) B Gate burr area C Active Area Depth, 0.50 mm REF +0.05 0.43 –0.07 D Branding scale and appearance at supplier discretion E Hall element, not to scale 1.27 NOM Copyright ©2009-2010, Allegro MicroSystems, Inc. The products described herein are manufactured under one or more of the following U.S. patents: 5,619,137; 5,621,319; 7,425,821 and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12