Revised March 2002 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate General Description Features The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. ■ Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range All inputs are protected against static discharge with diodes to VDD and VSS. Ordering Code: Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4001BC Top View © 2002 Fairchild Semiconductor Corporation Pin Assignments for DIP and SOIC CD4011BC Top View DS005939 www.fairchildsemi.com CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate October 1987 CD4001BC/CD4011BC Schematic Diagrams CD4001BC 1 /4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4011BC 1 /4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to VDD +0.5V Voltage at any Pin Operating Range (VDD) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW −65°C to +150°C Storage Temperature (TS) Lead Temperature (TL) DC Electrical Characteristics IDD VOL Note 2: All voltages measured with respect to VSS unless otherwise specified. 260°C (Soldering, 10 seconds) Parameter (Note 2) −55°C Conditions Min VIH IOL IOH IIN Min +125°C Typ Max Min Max Quiescent Device VDD = 5V, VIN = VDD or VSS 0.25 0.004 0.25 VDD = 10V, VIN = VDD or VSS 0.5 0.005 0.50 15 VDD = 15V, VIN = VDD or VSS 1.0 0.006 1.0 30 LOW Level VDD = 5V 0.05 0 0.05 0.05 Output Voltage VDD = 10V 0.05 0 0.05 0.05 0.05 0 0.05 0.05 |IO| < 1 µA HIGH Level VDD = 5V Output Voltage VDD = 10V 4.95 5 9.95 9.95 10 9.95 14.95 14.95 15 14.95 µA V 4.95 V LOW Level VDD = 5V, VO = 4.5V 1.5 2 1.5 Input Voltage VDD = 10V, VO = 9.0V 3.0 4 3.0 3.0 VDD = 15V, VO = 13.5V 4.0 6 4.0 4.0 1.5 HIGH Level VDD = 5V, VO = 0.5V 3.5 3.5 3 3.5 Input Voltage VDD = 10V, VO = 1.0V 7.0 7.0 6 7.0 VDD = 15V, VO = 1.5V 11.0 11.0 9 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 Current VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 (Note 3) VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 (Note 3) VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current Units 7.5 4.95 |IO| < 1 µA VDD = 15V VIL +25°C Max Current VDD = 15V VOH −55°C to +125°C CD4001BC, CD4011BC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. −0.5 VDC to +18 VDC VDD Range Symbol 3 VDC to 15 VDC Operating Temperature Range V V mA mA VDD = 15V, VIN = 0V −0.10 −10−5 −0.10 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.10 1.0 µA Note 3: IOL and IOH are tested one output at a time. AC Electrical Characteristics (Note 4) CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C. Symbol tPHL tPLH tTHL, tTLH Typ Max Propagation Delay Time, Parameter VDD = 5V 120 250 HIGH-to-LOW Level VDD = 10V 50 100 VDD = 15V 35 70 Propagation Delay Time, VDD = 5V 110 250 LOW-to-HIGH Level VDD = 10V 50 100 VDD = 15V 35 70 VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 Transition Time Conditions CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 14 Units ns ns ns pF pF Note 4: AC Parameters are guaranteed by DC correlated testing. 3 www.fairchildsemi.com CD4001BC/CD4011BC Absolute Maximum Ratings(Note 1) CD4001BC/CD4011BC AC Electrical Characteristics (Note 5) CD4011BC: TA= 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical Temperature Coefficient is 0.3%/°C. Symbol tPHL tPLH Parameter Conditions Typ Max 120 250 VDD = 10V 50 100 VDD = 15V 35 70 Propagation Delay, VDD = 5V 85 250 LOW-to-HIGH Level VDD = 10V 40 100 VDD = 15V 30 70 VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 Propagation Delay, VDD = 5V HIGH-to-LOW Level tTHL, tTLH Transition Time CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 14 Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics www.fairchildsemi.com 4 Units ns ns ns pF pF CD4001BC/CD4011BC Typical Performance Characteristics (Continued) Typical Transfer Characteristics 5 www.fairchildsemi.com CD4001BC/CD4011BC Typical Performance Characteristics www.fairchildsemi.com (Continued) 6 CD4001BC/CD4011BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 7 www.fairchildsemi.com CD4001BC/CD4011BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 8 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued)