Maxim MAX547BEQH Octal, 13-bit voltage-output dac with parallel interface Datasheet

19-0257; Rev 3; 12/95
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
_____________________________Features
The MAX547 contains eight 13-bit, voltage-output digital-toanalog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The MAX547 operates
from a ±5V supply. Bipolar output voltages with up to ±4.5V
voltage swing can be achieved with no external components. The MAX547 has four separate reference inputs;
each is connected to two DACs, providing different fullscale output voltages for every DAC pair.
The MAX547 features double-buffered interface logic with a
13-bit parallel data bus. Each DAC has an input latch and a
DAC latch. Data in the DAC latch sets the output voltage. The
eight input latches are addressed with three address lines.
Data is loaded to the input latch with a single write instruction.
–——–
An asynchronous load (LD_ ) input transfers data from the
–——
–
input latch to the DAC latch. The four LD_ inputs each control
two DACs, and all DAC latches can be updated simultane–——–
–——–
ously by asserting all LD_ pins. An asynchronous clear (CLR)
input resets the output of all eight DACs to AGND_. Asserting
–——–
CLR resets both the DAC and the input latch to bipolar zero
(1000hex). On power-up, reset circuitry performs the same
–——–
function as CLR. All logic inputs are TTL/CMOS compatible.
The MAX547 is available in 44-pin plastic quad flat pack
and 44-pin PLCC packages.
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
________________________Applications
Automatic Test Equipment
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Arbitrary Function Generators
Industrial Process Controls
Avionics Equipment
Full 13-Bit Performance without Adjustments
8 DACs in One Package
Buffered Voltage Outputs
Calibrated Linearity
Guaranteed Monotonic to 13 Bits
±5V Supply Operation
Unipolar or Bipolar Outputs Swing to ±4.5V
Fast Output Settling (5µs to ±1⁄2LSB)
Double-Buffered Digital Inputs
Asynchronous Load Inputs Load Pairs of DAC Latches
–——–
Asynchronous C L R Input Resets DACs to Analog
Ground
♦ Power-On Reset Circuit Resets DACs to Analog Ground
♦ Microprocessor and TTL/CMOS Compatible
________________Ordering Information
PIN-PACKAGE
INL
(LSBs)
PART
TEMP. RANGE
MAX547ACQH
0°C to +70°C
44 PLCC
±2
MAX547BCQH
MAX547ACMH
MAX547BCMH
MAX547BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
44 PLCC
44 Plastic FP
44 Plastic FP
Dice*
±4
±2
±4
±4
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
32
3
31
4
30
5
29
6
28
MAX547
7
8
27
26
9
25
24
10
11
22
20
21
VOUTF
44 43 42 41 40
VOUTE
1
VSS
2
REFEF
AGNDEF
3
AGNDCD
4
CLR
VSS
REFCD
VOUTD
5
VOUTG
VOUTH
VDD
REFGH
AGNDGH
GND
LDGH
LDEF
D0
D1
D2
VOUTB
7
39 VOUTG
VOUTA
8
38 VOUTH
VDD
9
37 VDD
REFAB
10
36 REFGH
AGNDAB
11
LDAB
12
LDCD
13
33 LDGH
CS
14
32 LDEF
WR
15
31 D0
A2
16
30 D1
A1
17
29 D2
35 AGNDGH
MAX547
34 GND
PLASTIC FP
D3
D4
D5
D6
D7
D8
D9
A0
D10
19 20 21 22 23 24 25 26 27 28
D11
18
D12
A0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
17
18
19
23
14
15
16
6
34
35
36
37
38
39
40
42
41
33
2
12
LDAB
LDCD
CS
WR
A2
A1
1
13
VOUTB
VOUTA
VDD
REFAB
AGNDAB
43
44
VOUTC
VOUTD
VSS
REFCD
AGNDCD
CLR
AGNDEF
REFEF
VSS
VOUTE
VOUTF
TOP VIEW
VOUTC
_______________________________________________________________Pin Configurations
PLCC
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX547
_________________General Description
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VSS to GND...............................................................-6V to +0.3V
Digital Input Voltage to GND ......................-0.3V to (VDD + 0.3V)
REF_ ..........................................(AGND_ - 0.3V) to (VDD + 0.3V)
AGND_ .............................................(VSS - 0.3V) to (VDD + 0.3V)
VOUT_ ........................................................................VDD to VSS
Maximum Current into REF_ Pin .......................................±10mA
Maximum Current into Any Other Signal Pin ....................±50mA
Continuous Power Dissipation (TA = +70°C)
PLCC (derate 13.33mW/°C above +70°C)...................1067mW
Plastic FP (derate 11.11mW/°C above +70°C )..............889mW
Operating Temperature Ranges
MAX547–C–H.........................................................0°C to +70°C
MAX547–E–H ......................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL = 10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
Relative Accuracy
INL
Differential Nonlinearity
DNL
13
Bits
MAX547A
±0.5
±2
MAX547B
±0.5
±4
Guaranteed monotonic
LSB
±1
LSB
Bipolar Zero-Code Error
±5
±20
LSB
Gain Error
±1
±8
LSB
Power-Supply Rejection Ratio
PSRR
∆Gain/∆VDD (Note 1)
±0.0025
∆Gain/∆VSS (Note 1)
±0.0025
RL = ∞ to 10kΩ
Load Regulation
0.3
%/%
LSB
REFERENCE INPUT (Note 2)
Reference Input Range
Reference Input Resistance
REF
RREF
(Notes 2, 3)
Each REF– pin (Note 3)
AGND–
VDD
5
V
kΩ
ANALOG OUTPUT
Maximum Output Voltage
VDD - 0.5
V
Minimum Output Voltage
VSS + 0.5
V
3
V/µs
DYNAMIC PERFORMANCE—ANALOG SECTION
Voltage-Output Slew Rate
To ±1⁄2 LSB of full scale (Note 4)
Output Settling Time
5
µs
Digital Feedthrough
5
nV-s
Digital Crosstalk
5
nV-s
DIGITAL INPUTS (VDD = 5V ±5%)
Input Voltage High
VIH
Input Voltage Low
VIL
0.8
V
Input Current
IIN
VIN = 0V or VDD
1.0
µA
Input Capacitance
CIN
(Note 5)
10
pF
2
2.4
_______________________________________________________________________________________
V
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL = 10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply Range
VDD
(Note 6)
4.75
5.25
V
Negative Supply Range
VSS
(Note 6)
-5.25
-4.75
V
Positive Supply Current
IDD
TA = TMIN to TMAX
14
44
mA
Negative Supply Current
ISS
TA = TMIN to TMAX
11
40
mA
Note 1: PSRR is tested by changing the respective supply voltage by ±5%.
Note 2: For best performance, REF_ should be greater than AGND_ + 2V and less than VDD - 0.6V. The device operates with
reference inputs outside this range, but performance may degrade. For further information on the reference, see the
Reference and Analog-Ground Inputs section in the Detailed Description.
Note 3: Reference input resistance is code dependent. See Reference and Analog-Ground Inputs section in the Detailed
Description.
Note 4: Typical settling time with 1000pF capacitive load is 10µs.
Note 5: Guaranteed by design. Not production tested.
Note 6: Guaranteed by supply-rejection test.
TIMING CHARACTERISTICS
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
–—–
CS Pulse Width Low
–—–
WR Pulse Width Low
–——
–
LD– Pulse Width Low
–——–
CLR Pulse Width Low
–—–
–—–
CS Low to WR Low
–—–
–—–
CS High to WR High
–—–
Data Valid to WR Setup
–—–
Data Valid to WR Hold
–—–
Address Valid to WR Setup
–—–
Address Valid to WR Hold
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t1
50
ns
t2
50
ns
t3
50
ns
t4
100
ns
t5
0
ns
t6
0
ns
t7
50
ns
t8
0
ns
t9
10
ns
t10
0
ns
_______________________________________________________________________________________
3
MAX547
ELECTRICAL CHARACTERISTICS (continued)
__________________________________________Typical Operating Characteristics
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA = +25°C, unless otherwise noted.)
0.2
0.1
0
-0.1
-0.2
1
0
-0.3
20
15
5
0
-5
ISS
-10
-15
-20
-2
1
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
SETTLING TIME
vs. LOAD CAPACITANCE
REF– = 2Vp-p
INPUT CODE = ALL 1s
0.060
0.050
0.040
0.080
0.070
REF– = 4Vp-p
INPUT CODE = ALL 1s
0.060
0.050
0.040
0.030
0.030
0.020
0.020
0.010
0.010
1000
SETTLING TIME (µs)
0.070
0.090
THD + NOISE (%)
0.080
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
REFERENCE INPUT SMALL-SIGNAL
FREQUENCY RESPONSE
REFERENCE INPUT LARGE-SIGNAL
FREQUENCY RESPONSE
100
1
1000
2
0
MAX547-Fg TOC-1
6
0
-2
RELATIVE OUTPUT (dB)
SINE WAVE AT REF–
2V ±100mV
CODE ALL 1s
-6
-12
-18
-24
-14
-22
100
FREQUENCY (kHz)
1000
10,000
1
10
100
0
-10
-20
-30
-40
SINE WAVE AT REF_
2V ±2V
-50
-60
-70
-36
10
0.1
REFERENCE FEEDTHROUGH
-10
-18
1
0.01
LOAD CAPACITANCE (nF)
SINE WAVE AT REF_
2V ±2V
CODE ALL 1s
-6
-30
0.1
10
1000
RELATIVE OUTPUT (dB)
10
MAX547-Fg TOC-6
1
100
1
0
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
MAX547-Fg TOC-3
0.090
-60 -40 -20 0
5
4
0.100
MAX547-Fg TOC-4
0.100
3
REFERENCE VOLTAGE (V)
DIGITAL INPUT CODE (DECIMAL)
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
2
MAX547-Fg TOC-9
0
MAX547-Fg TOC-7
8191
7168
6144
5120
3072
4096
2048
1024
0
-0.5
THD + NOISE (%)
IDD
10
-1
-0.4
4
MAX547-Fg TOC-2
2
RELATIVE ACCURACY (LSB)
0.3
3
MAX547-Fg TOC-11
0.4
SUPPLY CURRENT (mA)
MAX547-Fg TOC-5
0.5
RELATIVE ACCURACY (LSB)
SUPPLY CURRENT
vs. TEMPERATURE
RELATIVE ACCURACY vs.
REFERENCE VOLTAGE
RELATIVE ACCURACY
vs. DIGITAL INPUT CODE
RELATIVE OUTPUT (dB)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
-80
-90
0.1
1
10
100
1000
FREQUENCY (kHz)
10,000
0.1
1
10
100
FREQUENCY (kHz)
_______________________________________________________________________________________
1000
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
VDD = VSS = 5V ±200mV
NO LOAD
NEGATIVE
FULL-SCALE
1.0
-30
VSS
ERROR (LSB)
PSRR (dB)
-20
1.5
VDD
-40
-50
MAX547-Fg TOC-8
-10
2.0
MAX547-Fg TOC-10
0
FULL-SCALE ERROR
vs. LOAD RESISTANCE
0.5
0
REF_ = 4.096V
-0.5
-60
-1.0
-70
-1.5
POSITIVE
FULL-SCALE
-2.0
-80
0.01
0.1
1
10
100
1000
1
FREQUENCY (kHz)
100
10
1000
LOAD RESISTANCE (kΩ)
NEGATIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS ON TO ALL BITS OFF)
POSITIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS OFF TO ALL BITS ON)
DIGITAL
INPUTS
(5V/div)
DIGITAL
INPUTS
(5V/div)
OUTPUT
(1mV/div)
OUTPUT
(1mV/div)
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
DYNAMIC RESPONSE
(ALL BITS OFF, ON, OFF)
DIGITAL FEEDTHROUGH
(GLITCH IMPULSE)
DIGITAL
INPUTS
(5V/div)
+5V
0V
10mV
0V
-10mV
OUTPUT
(2V/div)
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
200ns/div
TOP: DIGITAL TRANSITION ON ALL DATA BITS
BOTTOM: DAC OUTPUT WITH WR HIGH 10mV/div
_______________________________________________________________________________________
5
MAX547
____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA = +25°C, unless otherwise noted.)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA = +25°C, unless otherwise noted.)
ADJACENT-CHANNEL CROSSTALK
ADJACENT-CHANNEL CROSSTALK
A:
5V/div
A
5V/div
B
5mV/div
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A: DIGITAL INPUTS, DAC A, DATA BITS from ALL Os to OAAAhex
B: OUTPUT, DAC B
B:
5mV/div
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A: DIGITAL INPUTS, DAC A, DATA BITS from OAAAhex to ALL Os
B: OUTPUT, DAC B
______________________________________________________________Pin Description
PIN
6
NAME
FUNCTION
PLCC
FLAT
PACK
1
39
–——–
CLR
2
40
AGNDCD
3
41
REFCD
4, 42
42, 36
VSS
5
43
VOUTD
DAC D Output Voltage
6
44
VOUTC
DAC C Output Voltage
7
1
VOUTB
DAC B Output Voltage
8
2
VOUTA
DAC A Output Voltage
9, 37
3, 31
VDD
Positive Power Supply, 5V (2 pins). Connect both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1µF to 1µF capacitor.
10
4
REFAB
Reference Voltage Input for DAC A and DAC B. Bypass to AGNDAB with a 0.1µF to 1µF capacitor.
11
5
AGNDAB
12
6
–———–
LDAB
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
A and B to the respective DAC latches.
13
7
–———–
LDCD
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
C and D to the respective DAC latches.
14
8
15
9
–—–
CS
–—–
WR
Clear Input (active low). Driving this asynchronous input low sets the content of all latches to
1000hex. All DAC outputs are reset to AGND_.
Analog Ground for DAC C and DAC D
Reference Voltage Input for DAC C and DAC D. Bypass to AGNDCD with a 0.1µF to 1µF capacitor.
Negative Power Supply, -5V (2 pins). Connect both pins to the supply voltage. Bypass each pin
to the system analog ground with a 0.1µF to 1µF capacitor.
Analog Ground for DAC A and DAC B
Chip Select (active low)
–—–
–—–
Write Input (active low). WR, along with CS, loads data into the DAC input latch selected by A0–A2.
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
PIN
PLCC
FLAT
PACK
NAME
FUNCTION
16
10
A2
Address Bit 2
17
11
A1
Address Bit 1
18
12
A0
Address Bit 0
19–31
13–25
D12–D0
Data Bits 12–0
32
26
–———–
LDEF
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
E and F to the respective DAC latches.
33
27
–———–
LDGH
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
G and H to the respective DAC latches.
34
28
GND
Digital Ground
35
29
AGNDGH
36
30
REFGH
Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a 0.1µF to 1µF capacitor.
38
32
VOUTH
DAC H Output Voltage
39
33
VOUTG
DAC G Output Voltage
40
34
VOUTF
DAC F Output Voltage
41
35
VOUTE
DAC E Output Voltage
43
37
REFEF
44
38
AGNDEF
Analog Ground for DAC G and DAC H
Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a 0.1µF to 1µF capaciAnalog Ground for DAC E and DAC F
_______________Detailed Description
Analog Section
The MAX547 contains eight 13-bit, voltage-output
DACs. These DACs are “inverted” R-2R ladder networks that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied reference voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different fullscale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
amplifier is connected to the respective reference
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
R
R
2R
R
R
R
VDAC
2R
2R
2R
2R
D0
D10
D11
D12
OUT
REF–
AGND–
Figure 1. DAC Simplified Circuit Diagram
_______________________________________________________________________________________
7
MAX547
_________________________________________________Pin Description (continued)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
Reference and Analog-Ground Inputs
The REF_ inputs can range between AGND_ and VDD.
However, the DAC outputs will operate to VDD - 0.6V
and VSS + 0.6V, due to the output amplifiers’ voltageswing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the Digital Code
and Analog Output Voltage section in the Applications
Information.
The input impedance of the REF_ inputs is code dependent. It is at its lowest value (5kΩ min) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50kΩ, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load impedance is 1.25kΩ. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
important. For more information, see Reference
Selection in the Applications Information section.
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer Amplifiers
The MAX547’s voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/µs. With a full-scale transition at its output,
the typical settling time to ±1⁄2LSB is 5µs when loaded
with 10kΩ in parallel with 50pF, or 6µs when loaded
with 10kΩ in parallel with 100pF.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microprocessors using a data bus at least 13 bits wide. The interface is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC’s input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asynchronous LD_ signal. Each DAC’s analog output
reflects the data held in its DAC latch. All control inputs
are level triggered.
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch and LD_ transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low, and
8
Table 1. MAX547 DAC Addressing
A2
A1
A0
FUNCTION
0
0
0
DAC A input latch
0
0
1
DAC B input latch
0
1
0
DAC C input latch
0
1
1
DAC D input latch
1
0
0
DAC E input latch
1
0
1
DAC F input latch
1
1
0
DAC G input latch
1
1
1
DAC H input latch
TO INPUT LATCH OF DAC H
TO INPUT LATCH OF DAC G
A2
A1
TO INPUT LATCH OF DAC F
TO INPUT LATCH OF DAC E
TO INPUT LATCH OF DAC D
A0
TO INPUT LATCH OF DAC C
TO INPUT LATCH OF DAC B
CS
TO INPUT LATCH OF DAC A
WR
LDGH
TO DAC LATCHES OF DAC G AND DAC H
LDEF
TO DAC LATCHES OF DAC E AND DAC G
LDCD
TO DAC LATCHES OF DAC C AND DAC D
LDAB
TO DAC LATCHES OF DAC C AND DAC B
CLR
TO ALL INPUT AND DAC LATCHES
Figure 2. Input Control Logic
the DAC latch is transparent when LD_ is low. The
address lines (A0, A1, A2) must be valid throughout the
time CS and WR are low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CS or WR is
high. Taking LD_ high latches data into the DAC latches.
If LD_ is brought low when WR and CS are low, it must
be held low for t3 or longer after WR and CS are high
(Figure 3).
Pulling the asynchronous CLR input low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, and LD_. Taking CLR high latches 1000hex into
all input latches and DAC latches.
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
–——–
CLR
1
–——–
LD–
0
–—–
WR
0
–—–
CS
0
1
1
1
1
X
Both latches latched
1
X
1
Both latches latched
1
X
0
0
Input latch transparent
1
X
1
X
Input latch latched
1
X
X
1
Input latch latched
1
0
X
X
DAC latch transparent
0
X
X
X
All input and DAC latches at
1000hex, outputs at AGND–
FUNCTION
Both latches transparent
__________Applications Information
Multiplying Operation
The MAX547 can be used for multiplying applications.
Its reference accepts both DC and AC signals. The voltage at each REF_ input sets the full-scale output voltage
for its respective DACs. Since the reference inputs
accept only positive voltages, multiplying operation is
limited to two quadrants. Do not bypass the reference
inputs when applying AC signals to them. Refer to the
graphs in the Typical Operating Characteristics for
dynamic performance of the DACs and output buffers.
Digital Code and Analog Output Voltage
The MAX547 uses offset binary coding. A 13-bit twoscomplement code can be converted to a 13-bit offset
binary code by adding 212 = 4096.
Bipolar Output Voltage Range (AGND_ = 0V)
For symmetrical bipolar operation, tie AGND_ to the
system ground. Table 3 shows the relationship between
digital code and output voltage. The following paragraphs give a detailed explanation of this mode.
t1
CS
t5
t6
The DAC ladder output voltage (VDAC) is multiplied by
2 and level shifted by the reference voltage, which is
internally connected to the output amplifiers (Figure 1).
Since the feedback resistors are the same size, the
amplifier’s output voltage is 2 times the voltage at its
noninverting input, minus the reference voltage.
t2
WR
t9
t10
VOUT = 2(VDAC ) − REF–
A0–A2
t7
where VDAC is the voltage at the amplifier’s noninverting input (DAC ladder output voltage), and REF_ is the
voltage applied to the reference input of the DAC.
With AGND_ connected to the system ground, the DAC
ladder output voltage is:
t8
D0–D12
t3
t3
LD–
VDAC =
D
2
n
D
(REF– ) =
(REF– )
213
where D is the numeric value of the DAC’s binary input
code and n is the DAC’s resolution (13 bits). Replace
VDAC in the equation and calculate the output voltage.
 D 
VOUT_ = 2 
 REF– − REF–
 213 
 D

 D

= REF– 
– 1 = REF– 
– 1
 4096 
 212

(
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. tr = tf = 5ns.
2. MEASUREMENT REFERENCE LEVEL IS
(VINH + VINL)/2.
3. IF LD– IS ACTIVATED WHILE WR IS LOW THEN LD– MUST STAY LOW
FOR t3 OR LONGER AFTER WR GOES HIGH.
)
D ranges from 0 (20) to 8191 (213 - 1).
 1 
1LSB = REF– 

 4096 
Figure 3. Write-Cycle Timing
_______________________________________________________________________________________
9
MAX547
Table 2. Interface Truth Table
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
Table 4. MAX547 Positive Unipolar Code Table
Table 3. MAX547 Bipolar Code Table
(AGND_ = REF _)
2
(AGND_ = 0V)
INPUT
OUTPUT
INPUT
OUTPUT
1 1111 1111 1111
4095
+REF_ ———
4096
1 1111 1111 1111
8191
+REF_ ———
8192
1 0000 0000 0001
1
+REF_ ———
4096
1 0000 0000 0000
1 0000 0000 0000
0V
0 1111 1111 1111
1
-REF_ ———
4096
0 0000 0000 0001
4095
-REF_ ———
4096
0 0000 0000 0000
-REF_
(
(
)
)
(
(
+5V
1µF
Customizing the Output Voltage Range
The AGND_ inputs can be offset by any voltage within the
supply rails if the voltage at the referring REF_ input is
higher than the voltage at the AGND_ input. Select the
reference voltage and the voltage at AGND_ so the
resulting output voltages do not come within ±0.6V of the
supply rails. Figure 4’s circuit shows one way to add positive offset to AGND_; make sure that the op amp used
has sufficient current-sink capability to take up the
remaining AGND_ current:
)
)
1µF
REFAB
1µF
VOUTA
R1
DAC A
AGNDAB
VOUTB
REF
DAC B
R2
1µF
1µF
-5V
Figure 4. Offsetting AGND–
Positive Unipolar Output Voltage Range
(AGND_ = REF_/2)
For positive unipolar output operation, set AGND_ to
(REF_/2). For example, if you use Figure 4’s circuit with,
a 4.096V reference and offset AGND_ by 2.048V with
matched resistors (R1 = R2) and an op amp, it results in
a 0V to 4.0955V (nominal) unipolar output voltage,
where 1LSB = 500µV. In general, the maximum current
flowing out of any AGND_ pin is given by:


I AGND_ =  REF_ − AGND_ 


5kΩ


10


I AGND_ =  REF_ − AGND_ 


5kΩ


Another way is to digitally offset AGND_ by connecting
the output of one DAC to one or more AGND_ inputs. Do
not connect a DAC output to its own AGND_ input.
Table 5 summarizes the relationship between the reference and AGND_ potentials and the output voltage in
the different modes of operation.
Power-Supply Sequencing
MAX547
VSS
VSS
DIGITAL INPUTS NOT SHOWN.
NOT ALL DACS SHOWN.
)
+REF– /2
0V
0 0000 0000 0000
VDD
VDD
(
The sequence in which the supply voltages come up is
not critical. However, we recommend that on power-up,
VSS comes up first, VDD next, followed by the reference
voltages. If you use other sequences, limit the current
into any reference pin to 10mA. Also, make sure that
VSS is never more than 300mV above ground. If there is
a risk that this can occur at power-up, connect a
Schottky diode between VSS and GND, as shown in
Figure 5. We recommend that you not power up the
logic input pins before establishing the supply voltages. If this is not possible and the digital lines can
drive more than 10mA, you should place current-limiting resistors (e.g., 470Ω) in series with the logic pins.
Reference Selection
If you want a ±2.5V full-scale output voltage swing, you
can use the MAX873 reference. It operates from a single 5V supply and is specified to drive up to 10mA.
Therefore, it can drive all four reference inputs simultaneously. Because the maximum load impedance can
vary from 1.25kΩ to 12.5kΩ (four reference inputs in
parallel), the reference load current ranges from 2mA to
0.2mA (1.8mA maximum load step). The MAX873’s
______________________________________________________________________________________
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
MAX547
Table 5. Reference, AGND– and Output Relationships
PARAMETER
BIPOLAR OPERATION
(AGND_ = 0V)
Bipolar Zero Level, or
Unipolar Mid-scale,
(Code = 1000000000000)
AGND_ (=0V)
POSITIVE UNIPOLAR
OPERATION
(AGND_ = REF_/2)
CUSTOM OPERATION
(
AGND–
AGND–
)
REF_
= ———
2
Differential Reference Voltage
(VDR)
REF–
REF–/2
REF– - AGND–
Negative Full-scale Output
(Code = All 0s)
-REF–
0V
AGND– - VDR
(
Positive Full-Scale Output
(Code = All 1s)
)( )
4095
———
4096
REF_
REF_
———
4096
LSB Weight
VOUT– as a Function of
Digital Code (D, 0 to 8191)
(
)( )
( )
( )( )
8191
———
8192
(
4095
AGND _ + ———
4096
REF_
REF_
———
8192
)( )
D -1
———
4096
(
REF_
load regulation is specified to 20ppm/mA max over
temperature, resulting in a maximum error of 36ppm
(90µV). This corresponds to a maximum error caused
by reference load regulation of only 0.147LSB
[0.147LSB = 90µV/(5V/8192)LSB] over temperature.
If you want a ±4.096V full-scale output swing (1LSB =
1mV), you can use the calibrated, low-drift, low-dropout
MAX676. Operating from a 5V supply, it is fully specified to drive two REF_ inputs with less than 60.4µV error
(0.0604LSB) over temperature, caused by the maximum load step.
D
———
8192
(
)( )
D
-1
AGND _ + —--—4096
VDR
VSS
MAX547
1N5817
Reference Buffering
Another way to obtain high accuracy is to buffer a reference with an op amp. When driving all reference inputs
simultaneously, keep the closed-loop output impedance of the op amp below 0.03Ω to ensure an error of
less than 0.1LSB. The op amp must also drive the
capacitive load (typically 500pF to 1200pF).
Each reference input can also be buffered separately
by using the circuit in Figure 6. A reference load step
caused by a digital transition only affects the DAC pair
where the code transition occurs. It also allows the use
of references with little drive capability. Keep the
closed-loop output impedance of each op amp below
0.12Ω, to ensure an error of less than 0.1LSB. Figure 6
shows the op amp’s inverting input directly connected
to the MAX547’s reference terminal. This eliminates the
VDR
VDR
———
4096
REF_
VSS
)( )
GND
SYSTEM GND
Figure 5. Optional Schottky Diode between VSS and GND
influence of board lead resistance by sensing the voltage with a low-current path sense line directly at the
reference input.
Adding feedback resistors to individual reference
buffer amplifiers enables different reference voltages to
be generated from a single reference.
______________________________________________________________________________________
11
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
MAX547
_Ordering Information (continued)
PART
TEMP. RANGE
MAX547AEQH
MAX547BEQH
MAX547AEMH
MAX547BEMH
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
REFAB
REFCD
44 PLCC
44 PLCC
44 Plastic FP
44 Plastic FP
MAX547
REFEF
+
REFGH
-
MAX494
Figure 6. Reference Buffering
Power-Supply Bypassing and
Ground Management
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal operation, when all AGND_ pins are at the same potential,
connect the four AGND_ pins directly to the ground
plane or connect them together in a “star” configuration. The center of this star point is a good location to
connect the digital system ground with the analog
ground.
If you are using a single common reference voltage,
you can connect the reference inputs together using a
“star” configuration. If you are using DC reference voltages, bypass each reference input with a 0.1µF to 1µF
capacitor to AGND_.
12
______________________________________________________________________________________
INL
(LSBs)
±2
±4
±2
±4
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
VDD
REFAB
9, 37
REFCD
10
3
REFEF
REFGH
43
36
8
INPUT
LATCH A
DAC
LATCH A
INPUT
LATCH B
DAC
LATCH B
DAC B
INPUT
LATCH C
DAC
LATCH C
DAC C
INPUT
LATCH D
DAC
LATCH D
DAC D
INPUT
LATCH E
DAC
LATCH E
DAC E
INPUT
LATCH F
DAC
LATCH F
DAC F
INPUT
LATCH G
DAC
LATCH G
DAC G
INPUT
LATCH H
DAC
LATCH H
DAC H
DAC A
11
7
6
2
5
D12–D0
AGNDAB
VOUTB
VOUTC
AGNDCD
VOUTD
DATA BUS
41
44
40
39
35
38
CS
WR
VOUTA
14
15
CONTROL
LOGIC
16, 18
A0–A2
VOUTE
AGNDEF
VOUTF
VOUTG
AGNDGH
VOUTH
MAX547
12, 13
32, 33
LDAB
LDCD
LDEF
LDGH
1
CLR
4, 42
VSS
34
GND
Pin numbers shown for PLCC package.
______________________________________________________________________________________
13
MAX547
_________________________________________________________Functional Diagram
VOUTF
V SS
VOUTE
REFEF
AGNDEF
CLR
AGNDCD
REFCD
VOUTD
V SS
VOUTC
____________________________________________________________Chip Topography
VOUTB
VOUTG
VOUTA
VOUTH
V DD
V DD
REFGH
REFAB
AGNDAB
AGNDGH
0.242"
(6.147mm)
LDAB
GND
LDCD
LDGH
CS
LDEF
WR
D0
A2
D1
A1
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D2
A0
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
0.199"
(5.055mm)
TRANSISTOR COUNT: 8987
SUBSTRATE CONNECTED TO VDD
14
______________________________________________________________________________________
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
DIM
A2
C
e
D1 D
B1
D2
B
A
A1
A2
A3
B
B1
C
D
D1
D2
D3
e
INCHES
MAX
MIN
0.180
0.165
0.110
0.100
0.156
0.145
–
0.020
0.021
0.013
0.032
0.026
0.011
0.009
0.695
0.685
0.655
0.650
0.630
0.590
0.500 REF
0.050 REF
MILLIMETERS
MIN
MAX
4.19
4.57
2.54
2.79
3.68
3.96
0.51
–
0.33
0.53
0.66
0.81
0.23
0.28
17.40
17.65
16.51
16.64
14.99
16.00
12.70 REF
1.27 REF
21-350A
A3
D3
D1
D
A1
A
44-PIN PLASTIC
LEADED CHIP
CARRIER
PACKAGE
______________________________________________________________________________________
15
MAX547
________________________________________________________Package Information
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
Similar pages