EMC EM39LV80090M 8m bits (512kx16) flash memory Datasheet

EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
General Description
The EM39LV800 is an 8M bits Flash memory organized as 512K x 16 bits. The EM39LV800
uses 2.7-3.6V power supply for Program and Erase. Featuring high performance Flash
memory technology, the EM39LV800 provides a typical Word-Program time of 14 µsec and a
typical Sector/Block-Erase time of 18 ms. The device uses Toggle Bit or Data# Polling to
detect the completion of the Program or Erase operation. To protect against inadvertent
write, the device has on-chip hardware and software data protection schemes. The device
offers typical 100,000 cycles endurance and a greater than 10 years data retention. The
EM39LV800 conforms with the JEDEC standard pin outs for x16 memories. The
EM39LV800 is offered in package types of 48-ball FBGA, 48-pin TSOP, and known good dice
(KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed
information (see Appendix at the bottom of this specification for Ordering Information).
The EM39LV800 devices are developed for applications that require memories with
convenient and economical updating of program, data or configuration, e.g., DVD player, DVD
R/W, WLAN, Router, Set-Top Box, etc.
Features
„
Single Power Supply
Full voltage range from 2.7 to 3.6 volts
for both read and write operations
„
Sector-Erase Capability
Uniform 2Kword sectors
„
Block-Erase Capability
Uniform 32Kword blocks
„
Read Access Time
Access time: 55, 70 and 90 ns
„
Power Consumption
Active current: 20 mA (Typical)
Standby current: 2 µA (Typical)
„
Erase/Program Features
Sector-Erase Time: 18 ms (Typical)
Block-Erase Time: 18 ms (Typical)
Chip-Erase Time: 45 ms (Typical)
Word-Program Time: 14µs (Typical)
Chip Rewrite Time: 8 seconds (Typical)
This specification is subject to change without further notice. (04.09.2004 V1.0)
„
Automatic Write Timing
Internal VPP Generation
„
End-of-Program or End-of-Erase
Detection
Data# Polling
Toggle Bit
„
CMOS I/O Compatibility
„
JEDEC Standard
Pin-out and software command sets
compatible with single-power supply Flash
memory
„
High Reliability
Endurance cycles: 100K (Typical)
Data retention: 10 years
„
Package Option
48-pin TSOP
48-pin FBGA
Page 1 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Functional Block Diagram
Flash
Mem ory Array
X-Decoder
Address Buffer &
Latches
Mem ory Address
CE#
OE#
Control Logic
Y-Decoder
I/O Buffers and Data Latches
W E#
DQ15-DQ0
Figure 0a: Functional Block Diagram
Pin Assignments
TSOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Figure 0b: TSOP Pin Assignments
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 2 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
FBGA
FBGA
Top View, Balls Facing Down
A13
A12
A14
A15
A16
NC
DQ15
VSS
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
W E#
NC
NC
NC
DQ5
DQ12
VDD
DQ4
NC
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Figure 0c: FBGA Pin Assignments
Pin Description
Pin Name
Function
A0–A18
19 addresses
DQ15–DQ0
Data inputs/outputs
CE#
Chip enable
OE#
Output enable
WE#
Write enable
VDD
2.7 ~ 3.6 volt single power supply
VSS
Device ground
NC
Pin not connected internally
Table 1: Pin Description
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 3 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Device Operation
The EM39LV800 uses Commands to initiate the memory operation functions. The
Commands are written to the device by asserting WE# Low while keeping CE# Low. The
address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data
bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the EM39LV800 is controlled by CE# and OE#. Both have to be Low
for the system to obtain data from the outputs. CE# is used for device selection. When CE#
is high, the chip is deselected and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for
further details.
Word Program
The EM39LV800 is programmed on a word-by-word basis. Before programming, the sector
where the word is located must be erased completely. The Program operation is
accomplished in three steps:
„ The first step is a three-byte load sequence for Software Data Protection.
„ The second step is to load word address and word data. During the Word Program
operation, the addresses are latched on the falling edge of either CE# or WE#, whichever
occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever
occurs first.
„ The third step is the internal Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated,
will be completed within 20 µs. See Figures 2 and 3 for WE# and CE# controlled
Program operation timing diagrams respectively and Figure 15 for flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform additional tasks. Any command
issued during the internal Program operation is ignored.
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 4 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
EM39LV800 Device Operation
Operation
CE#
OE#
WE#
DQ
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
Erase
VIL
VIH
VIL
X
Standby
VIH
X
X
High Z
X
Write Inhibit
X
VIL
X
High Z/DOUT
X
Write Inhibit
X
X
VIH
High Z/DOUT
X
Software Mode
VIL
VIL
VIH
*
Address
Sector or Block address, XXH for
Chip-Erase
See Table 3
Product
Identification
* X can be VIL or VIH, but no other value.
Table 2: EM39LV800 Device Operation
Write Command/Command Sequence
The EM39LV800 provides two software methods to detect the completion of a Program or
Erase cycle in order to optimize the system write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates the internal Program or Erase
operation. The actual completion of the write operation is asynchronous with the system;
therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid
data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious
rejection, when an erroneous result occurs, the software routine should include an additional
two times loop to read the accessed location. If both reads are valid, then the device has
completed the write cycle, otherwise the rejection is valid.
Chip Erase
The EM39LV800 provides Chip-Erase feature, which allows the entire memory array to be
erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte
command sequence with Chip-Erase command (10H) at address 5555H in the last byte
sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,
whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and
Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and
Figure 17 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 5 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Sector/Block Erase
The EM39LV800 offers both Sector-Erase and Block-Erase modes. The Sector- (or Block-)
Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The sector architecture is based on uniform sector size of 2 KWord.
The Block architecture is based on uniform block size of 32 KWord. The Sector-Erase
operation is initiated by executing a six-byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block address is latched on the falling edge
of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The
End-of-Erase operation can be determined by using either Data# Polling or Toggle Bit
method. See Figures 7 and 8 for timing waveforms. Any commands issued during the
Sector or Block Erase operation are ignored.
Data# Polling (DQ7)
When the EM39LV800 is in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7
will produce the true data. Note that even though DQ7 may have valid data immediately
following the completion of an internal Program operation, the remaining data outputs may still
be invalid (valid data on the entire data bus will appear in subsequent successive Read cycles
after an interval of 1 µs). During internal Erase operation, any attempt to read DQ7 will
produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-Erase, Block-Erase, or Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 14 for
a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will
produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or
Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the
next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-Erase, Block-Erase or Chip-Erase, the Toggle Bit is valid
after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram
and Figure 14 for a flowchart.
Data Protection
The EM39LV800 provides both hardware and software features to protect the data from
inadvertent write.
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 6 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Hardware Data Protection
Noise/Glitch Protection:
VDD Power Up/Down Detection:
Write Inhibit Mode:
A WE# or CE# pulse of less than 5 ns will not initiate a
write cycle.
The Write operation is inhibited when VDD is less than
1.5V.
Forcing OE# Low, CE# High, or WE# High will inhibit the
Write operation. This prevents inadvertent write during
power-up or power-down.
Software Data Protection (SDP)
The EM39LV800 provides the JEDEC approved Software Data Protection (SDP) scheme for
Program and Erase operations. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent Write operations, especially during
the system power-up or power-down transition. Any Erase operation requires the inclusion of
six-byte sequence. See Table 3 for the specific software command codes. During SDP
command sequence, invalid commands will abort the device to Read mode within TRC. The
contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The EM39LV800 contains the CFI information to describe the characteristics of the device.
In order to enter the CFI Query mode, the system must write three-byte sequence, same as
Software ID Entry command, with 98H (CFI Query command) to address 5555H in the last
byte sequence. Once the device enters the CFI Query mode, the system can read CFI data
at the addresses given in Tables 4 through 6. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 7 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Software Command Sequence
1st Bus
Write Cycle
Command
Sequence
1
Addr
2
Data
2nd Bus
Write Cycle
Addr
1
2
Data
3rd Bus
Write Cycle
Addr
1
2
4th Bus
Write Cycle
1
Data
Addr
3
2
Data
Word Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA
Data
Sector Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
5th Bus
Write Cycle
Addr
1
2AAAH
2
6th Bus
Write Cycle
Data
Addr
1
Data
55H
SAX4
30H
4
50H
Block Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BAX
Chip Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
Software ID
5,6
Entry
5555H
AAH
2AAAH
55H
5555H
90H
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0000H 0007F
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0003H 0007F
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0040H 0001F
Device ID
5555H
AAH
2AAAH
55H
5555H
90H
0001H 0020H
5555H
AAH
2AAAH
55H
5555H
98H
Software ID
Exit7/CFI Exit
XXH
F0H
Software ID
Exit7/CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
5
CFI Query Entry
2
10H
Notes:
1. Address format A14-A0 (Hex), Addresses A18-A15 can be VIL or VIH, but no other value, for the Command
sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence.
3. WA = Program word address.
4. SAX for Sector-Erase; uses A18-A11 address lines.
BAX for Block-Erase; uses A18-A15 address lines.
5. The device does not remain in Software Product ID mode if powered down.
6. Both Software ID Exit operations are equivalent.
7. Refer to Figure 9 for more information.
Table 3: Software Command Sequence
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 8 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
CFI Query Identification String*
Address
Data
10H
0051H
11H
0052H
12H
0059H
13H
0001H
14H
0007H
15H
0000H
16H
0000H
17H
0000H
18H
0000H
19H
0000H
1AH
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extend Table
Alternate OEM command set (00H=none exists)
Address for Alternate OEM extended Table (00H=none exists)
* Refer to CFI publication 100 for more details.
Table 4: CFI Query Identification String1
System Interface
Address
Data
Data
1BH
0027H
1CH
0036H
1DH
0000H
VPP min (00H=no VPP pin)
1EH
0000H
VPP max (00H=no VPP pin)
1FH
0004H
Typical time out for Word-Program 2 µs (2 =16µs)
20H
0000H
Typical time out for min size buffer program 2N µs (00H=not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24=16ms)
22H
0006H
Typical time out for Chip-Erase 2 ms (2 =64ms)
23H
0001H
Maximum time out for Word-Program 2 times typical (2 x2 =32µs)
24H
0000H
Maximum time out for buffer Program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2 times typical
(21x24=32ms)
26H
0001H
Maximum time out for Chip-Erase 2 times typical (2 x2 =128ms)
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
N
4
N
6
N
1
4
N
N
1
6
Table 5: System Interface
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 9 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Device Geometry Information
Address
Data
Data
N
20
27H
0014H
Device size=2 Byte (14H=20; 2 =1MByte)
28H
0001H
29H
0000H
Flash Device Interface description; 0001H=x16-only asynchronous
interface
2AH
0000H
2BH
0000H
Maximum number of byte in multi-byte write=2N (00H=not
supported)
2CH
0002H
Number of Erase Sector/Block sizes supported by device
2DH
00FFH
Sector Information (y+1=Number of sectors; z x 256B=sector size)
2EH
0000H
y=255+1=256 sectors (00FFH=255)
2FH
0010H
30H
0000H
z=16 x 256 Bytes=4Kbyte/sector (0010H=16)
31H
000FH
Block Information (y+1=Number of blocks; z x 256B=block size)
32H
0000H
y=15+1=16 blocks (000FH=15)
33H
0000H
34H
0001H
z=256 x 256 Bytes=64 Kbyte/block (0100H=256)
Table 6: Device Geometry Information
Absolute Maximum Ratings
NOTE
Applied conditions greater than those listed under these ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these conditions or conditions greater than those defined in the operational sections of this
specification, are not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.
Temperature Under Bias ............................................................ –55°C to 125°C
Storage Temperature .................................................................. –65°C to 150°C
D.C. Voltage on Any Pin to Ground Potential ............................. –0.5 V to VDD+0.5V
Transient Voltage (<20ns) on Any Pin to Ground Potential .......... –2.0V to VDD +2.0V
Voltage on A9 Pin to Ground Potential ......................................... –0.5 V to 13.2V
Package Power Dissipation Capability (Ta=25°C)........................ 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds)............ 240°C
Output Short Circuit Current * ...................................................... 50mA
* Output shorted for no more than one second.
No more than one output shorted at a time.
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 10 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Operating Range
Model Name
Ambient Temperature
VDD
EM39LV800
0°C to +70°C
2.7~3.6V
Table 7: Operating Range
AC Conditions of Test
Input Rise/Fall Time ..................................................................... 5ns
Output Load ................................................................................. CL=30pF for 55Rns
Output Load ................................................................................. CL=100pF for 70ns/90ns
See Figures 14 and 15
DC CHARACTERISTICS (CMOS Compatible)
Parameter
Description
Test Conditions
Max
Unit
CE#=OE#=VIL, WE#=VIH, all I/Os open
30
mA
CE#=WE#=VIL, OE#=VIH,
30
mA
Standby VDD Current
CE#=VIHC, VDD=VDD Max
20
µA
Power Supply Current
Address Input =VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
Read
Program and Erase
ISB
IDD
Min
ILI
Input Leakage Current
VIN=GND to VDD, VDD=VDD Max
1
µA
ILO
Output Leakage Current
VOUT=GND to VDD, VDD=VDD Max
10
µA
0.8
V
VIL
Input Low Voltage
VDD=VDD Min
VIH
Input High Voltage
VDD=VDD Max
0.7 VDD
V
VIHC
Input High Voltage (CMOS)
VDD=VDD Max
VDD-0.3
V
VOL
Output Low Voltage
IOL=100µA, VDD=VDD Min
VOH
Output High Voltage
IOH=-100µA, VDD=VDD Min
0.2
VDD-0.2
V
V
Table 8: DC Characteristics (Cmos Compatible)
Recommended System Power-up Timing
Parameter
Min
Unit
TPU-READ*
Power-up to Read Operation
Description
100
µs
TPU-WRITE*
Power-up to Program/Erase Operation
100
µs
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 9: Recommended System Power-up Timing
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 11 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Capacitance (Ta=25°C, f=1Mhz, other pins open)
Parameter
Test Conditons
Max
CI/O*
I/O Pin Capacitance
Description
VI/O=0V
12pF
CIN*
Input Capacitance
VIN=0V
6pF
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 10: Capacitance (Ta=25°C, f=1Mhz, Other Pins Open)
Reliability Characteristics
Symbol
Parameter
Min Specification
Unit
Test Method
NEND*
Endurance
10,000
Cycles
JEDEC Standard A117
TDR*
Data Retention
10
Years
JEDEC Standard A103
ILTH*
Latch Up
100+IDD
mA
JEDEC Standard 78
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 11: Reliability Characteristics
AC Characteristics
Read Cycle Timing Parameters
Symbol
Parameter
55REC
Min
Max
55
70REC
Min
Max
70
90REC
Min
Max
90
Unit
TRC
Read Cycle Time
TCE
Chip Enable Access Time
55
70
90
ns
TAA
Address Access Time
55
70
90
ns
TOE
Output Enable Access Time
30
35
45
ns
TCLZ*
CE# Low to Active Output
0
TOLZ*
OE# Low to Active Output
0
TCHZ*
CE# High to High-Z Output
15
20
30
ns
TOHZ*
OE# High to High-Z Output
15
20
30
ns
TOH*
Output Hold from Address
Change
0
0
ns
0
0
ns
0
0
0
ns
ns
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 12a: Read Cycle Timing Parameters
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 12 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Symbol
55EC
Parameter
Min
70EC
Max
Min
55
90EC
Max
Min
70
Max
90
Unit
TRC
Read Cycle Time
TCE
Chip Enable Access Time
55
70
90
ns
TAA
Address Access Time
55
70
90
ns
TOE
Output Enable Access Time
30
35
45
ns
TCLZ*
0
ns
CE# Low to Active Output
0
TOLZ*
0
OE# Low to Active Output
0
TCHZ*
CE# High to High-Z Output
15
20
30
ns
TOHZ*
OE# High to High-Z Output
15
20
30
ns
TOH*
Output Hold from Address
Change
0
0
ns
0
0
ns
0
ns
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 12b: Read Cycle Timing Parameters
Program/Erase Cycle Timing Parameter
Symbol
Parameter
Min
Max
Unit
20
µs
TBP
Word-Program Time
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
45
ns
TWP
WE# Pulse Width
45
ns
TWPH*
WE# Pulse Width High
30
ns
TCPH*
CE# Pulse Width High
30
ns
TDS
Data Setup Time
45
ns
TDH*
Data Hold Time
0
ns
TIDA*
Software ID Access and Exit Time
TSE
Sector Erase
30
ms
TBE
Block Erase
30
ms
TSCE
Chip Erase
60
ms
150
ns
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 13: Program/Erase Cycle Timing Parameter
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 13 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Timing Diagrams
Read Cycle Timing Diagram
T RC
T AA
A18~A0
T CE
CE#
T OE
OE#
T OHZ
T OLZ
V IH
W E#
HIGH-Z
DQ15-0
T CHZ
T OH
T CLZ
Data Valid
Data Valid
HIGH-Z
Figure 1: Read Cycle Timing Diagram
WE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
T BP
5555
A18~A0
2AAA
5555
ADDR
T AH
W E#
T DH
TW P
T W PH
T DS
T AS
OE#
T CH
CE#
T CS
DQ15-0
XXAA
XX55
XXA0
SW 0
SW 1
SW 2
DATA
W ORD
(ADDR/DATA)
X can be V IL or V IH , but no other value.
Figure 2: WE# Controlled Program Cycle Timing Diagram
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 14 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
CE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
TBP
5555
A18~A0
2AAA
5555
ADDR
TAH
CE#
TDH
TCP
TCPH
TDS
TAS
OE#
TCH
WE#
T CS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
X can be VIL or VIH, but no other value.
Figure 3: CE# Controlled Program Cycle Timing Diagram
Data# Polling Timing Diagram
A18~A0
T CE
CE#
T O EH
T O ES
OE#
TOE
W E#
DQ7
DATA
DATA#
DATA#
DATA#
Figure 4: Data# Polling Timing Diagram
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 15 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Toggle Bit Timing Diagram
A18~A0
T CE
CE#
T OEH
T O ES
TOE
OE#
W E#
DQ6
Two Read Cycles
W ith Sam e Outputs
Figure 5: Toggle Bit Timing Diagram
WE# Controlled Chip-Erase Timing Diagram
TSCE
Six-Byte Code For Chip-Erase
A18~A0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
T WP
WE#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See
(SeeTable
Table13).
14)
X can be VIL or VIH, but no other value.
Figure 6: WE# Controlled Chip-Erase Timing Diagram
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 16 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
WE# Controlled Block-Erase Timing Diagram
TBE
Six-Byte Code For Block-Erase
5555
A18~A0
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
XXAA
SW0
DQ15-0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
Note: This device also supports CE# controlled Block-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met.(See
(SeeTable
Table13).
14)
BAX=Block Address
X can be VIL or VIH, but no other value.
Figure 7: WE# Controlled Block-Erase Timing Diagram
WE# Controlled Sector-Erase Timing Diagram
Six-Byte Code For Sector-Erase
A18~A0
5555
2AAA
5555
5555
2AAA
TSE
SA X
CE#
OE#
TWP
WE#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See
(SeeTable
Table13).
14)
SAX=Sector Address
X can be VIL or VIH, but no other value.
Figure 8: WE# Controlled Sector-Erase Timing Diagram
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 17 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Software ID Entry and Read
Three-Byte Sequence For
Software ID Entry
Address A14-0
5555
2AAA
5555
0000H 0003H 0040H 0001H
CE#
OE#
T IDA
TW P
W E#
T AA
T W PH
DQ15-0
XXAA
XX55
XX90
1
2
3
0020H
SW 0
SW 1
SW 2
Device ID=0020H
X can be V IL or V IH , but no other value.
1=007FH, 2=007FH, 3=001FH
Figure 9: Software ID Entry and Read
CFI Query Entry and Read
Three-Byte Sequence For
CFI Query Entry
Address A14-0
5555
2AAA
5555
CE#
OE#
T IDA
TW P
W E#
T AA
T W PH
DQ15-0
XXAA
XX55
XX98
SW 0
SW 1
SW 2
X can be VIL or VIH, but no other value.
Figure 10: CFI Query Entry and Read
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 18 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Software ID Exit/CFI Exit
Three-Byte Sequence For
Software ID Entry
Address A14-0
DQ15-0
5555
2AAA
XXAA
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
SW0 TWPH SW1
SW2
X can be VIL or VIH, but no other value.
Figure 11: Software ID Exit/CFI Exit
AC Input/Output Reference Waveforms
VIHT
Input
VIT
Reference Points
VOT
Output
VILT
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and V ILT(0.1 VDD) for a logic "0".
Measurement reference points for inputs and outpputs are V IT(0.5 VDD) and VOT(0.5 VDD). Input
rise and fall times(10% - 90% ) are <5ns
Note: VIT = Vinput Test
VOT = Voutput Test
VIHT = Vinput HIGH Test
VILT = Vinput LOW Test
Figure 12: AC Input/Output Reference Waveforms
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 19 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
A Test Load Example
TO TESTER
TO DUT
CL
Figure 13: A Test Load Example
Flow Charts
Wait Options
Internal Timer
Toggle Bit
Data# Polling
Progrm/Erase
Initiated
Progrm/Erase
Initiated
Progrm/Erase
Initiated
Wait TBP, TSCE,
TSE or TBE
Read Word
Read DQ7
Progrm/Erase
Completed
Read Same
Word
Is DQ7=true
data?
No
Yes
Does DQ6
match?
No
Progrm/Erase
Completed
Yes
Progrm/Erase
Completed
Figure 14: Wait Options
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 20 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Word-Program Algorithm
Start
Load Data: XXAAH
Address: 5555H
Load Data: XX55H
Address: 2AAAH
Load Data: XXA0H
Address: 5555H
Load Word
Address/Word Data
Wait for end of Program
(TBP, Data# Polling bit, or
Toggle bit operation)
Program Completed
X can be VIL or VIH, but no other value.
Figure 15: Word-Program Algorithm
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 21 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Software ID/CFI Command Flowcharts
CFI Query Entry
Command Sequence
Software ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XXF0H
Address: XXH
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Wait TIDA
Load Data: XX98H
Address: 5555H
Load Data: XX90H
Address: 5555H
Load Data: XXF0H
Address: 5555H
Return to Normal
Operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI Data
Read Software ID
Return to Normal
Operation
X can be VIL or VIH, but no other value.
Figure 16: Software ID/CFI Command Flowcharts
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 22 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Erase Command Sequence
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Load Data: XX80H
Address: 5555H
Load Data: XX80H
Address: 5555H
Load Data: XX80H
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XXAAH
Address: 5555H
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Load Data: XX55H
Address: 2AAAH
Load Data: XX10H
Address: 5555H
Load Data: XX30H
Address: SAX
Load Data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip Erased to
FFFFH
Sector Erased to
FFFFH
Block Erased to
FFFFH
X can be VIL or VIH, but no other value.
Figure 17: Erase Command Sequence
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 23 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Appendix
ORDERING INFORMATION (Standard Products)
The order number is defined by a combination of the following elements.
EM39LV800 -70 M
Description
Package Type (1 digit)
M
Y
H
D
= TSOP (Type 1, die up, 12mm x 20mm)
= FBGA (0.8mm pitch, 6mm x 8mm)
= Chip Form
= Known Good Dice (for wafer dice sell)
Speed Option (2-3 digits)
55R
70
90
**
**R
= 55ns
= 70ns
= 90ns
= VDD = 2.7–3.6V
= VDD=3.0-3.6V
Device Number/Description
EM39LV800
8 Megabit (512K x 16-Bit) Flash Memory
2.7-3.6 Volt only Read, Program, and Erase
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 24 of 25
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
ORDERING INFORMATION (Non-Standard Products)
For Know Good Dice (KGD), please contact ELAN Microelectronics at the following contact
information or its representatives.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Science-based Industrial Park
Hsinchu, Taiwan, R.O.C. 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information Technology
Group
Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
[email protected]
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
USA
Tel: +1 408 366-8223
Fax: +1 408 366-8220
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp.
(Europe)
Elan (Shenzhen)
Microelectronics Corp., Ltd.
Elan Electronics (Shanghai)
Corporation, Ltd.
Dubendorfstrasse 4
8051 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S. Ave.
Shenzhen Hi-Tech Industrial Park
Shenzhen, Guandong, CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
23/Bldg. #115 Lane 572, Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA
Tel: +86 021 5080-3866
Fax: +86 021 5080-4600
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 25 of 25
Similar pages