TI BQ24061DRCR 1a single-chip li-ion/li-pol charge management ic with thermal regulation Datasheet

bq2406x
www.ti.com
SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
1A SINGLE-CHIP Li-Ion/Li-Pol CHARGE MANAGEMENT IC
WITH THERMAL REGULATION
FEATURES
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DESCRIPTION
Ideal for Low-Dropout Designs for Single-Cell
Li-Ion or Li-Pol Packs in Space Limited
Applications
Integrated Power FET and Current Sensor for
up to 1-A Charge Applications
Reverse Leakage Protection Prevents Battery
Drainage
±0.5% Voltage Regulation Accuracy
Thermal Regulation Maximizes Charge Rate
Charge Termination by Minimum Current and
Time
Precharge Conditioning With Safety Timer
Status Outputs for LED or System Interface
Indicate Charge, Fault, and Power Good
Outputs
Short-Circuit and Thermal Protection
Automatic Sleep Mode for Low Power
Consumption
Small 3×3 mm MLP Package
Selectable Battery Insertion and Battery
Absent Detection
Input Overvoltage Protection
– 6.5 V and 10.5 V Options
The bq2406x series are highly integrated Li-Ion and
Li-Pol linear chargers, targeted at space-limited
portable applications. The bq2406x series offers a
variety of safety features and functional options,
while still implementing a complete charging system
in a small package. The battery is charged in three
phases: conditioning, constant or thermally regulated
current, and constant voltage. Charge is terminated
based
on
minimum
current.
An
internal
programmable charge timer provides a backup
safety feature for charge termination and is
dynamically adjusted during the thermal regulation
phase. The bq2406x automatically re-starts the
charge if the battery voltage falls below an internal
threshold; sleep mode is set when the external input
supply is removed. Multiple versions of this device
family enable easy design of the bq2406x in cradle
chargers or in the end equipment, while using low
cost or high-end AC adapters.
Pin Out
(Top View)
bq24061
IN
10
OUT
TMR
2
9
BAT
STAT1
3
8
CE
STAT2
4
7
PG
VSS
5
6
ISET
APPLICATIONS
•
•
1
PDA, MP3 Players, Digital Cameras
Internet Appliances and Handheld Devices
TYPICAL APPLICATION CIRCUIT
Li-lon or Li-Pol
Battery Pack
bq24061
Input Power
1
RTMR
4.7 mF
1.5 kW
1.5 kW
2
IN
OUT
TMR
BAT
49.9 kW
3
4
5
STAT1
CE
STAT2
PG
VSS
ISET
Pack+
10
4.7 mF
9
+
Pack-
8
7
6
RSET
1.13 kW
Typical Application for Charging Between 350 mA and 1 A.
Charge Enable and
Input Power Status
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq2406x
www.ti.com
SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
Charge Input Over
Voltage
Voltage
Termination
Enable
Safety
Timer
Enable
Power
Good
Status
IC
Enable
Pack
Temp
Pack Voltage
Detection
(Absent)
Devices (1) (2) (3)
Marking
4.2 V
6.5 V
TMR pin
TMR pin
PG pin
No
TS pin
With timer
enabled
bq24060
BPG
4.2 V
6.5 V
TMR pin
TMR pin
PG pin
CE pin
No
With timer
enabled
bq24061
BPH
4.2 V
6.5 V
TE pin
TMR pin
No
CE pin
No
With termination
enabled
bq24063
Preview
4.2 V
10.5 V
TMR pin
TMR pin
PG pin
No
TS pin
With timer
enabled
bq24064
BSA
(1)
(2)
(3)
The bq2406x are only available taped and reeled. Add suffix R to the part number for quantities of 3,000 devices per reel (e.g.,
bq24060BPGR). Add suffix T to the part number for quantities of 250 devices per reel (e.g., bq24060DRCT).
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
bq2406x
–0.3 V to 18 V (2)
Supply voltage (IN with respect to Vss)
Input voltage on IN, STATx, PG, TS, CE, TE, TMR (all with respect to Vss)
–0.3 V to V(IN)
Input voltage on OUT, BAT, ISET (all with respect to Vss)
–0.3 V to 7 V
Output sink current (STATx) + PG
15 mA
Output current (OUT pin)
1.5 A
TA
Operating free-air temperature range
–40°C to 155°C
Tstg
Storage temperature range
–65°C to 150°C
TJ
Junction temperature range
–40°C to 150°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability
The bq2406x device can withstand up to 26 V for a maximum of 87 hours.
RECOMMENDED OPERATING CONDITIONS
MIN
V(IN)
Supply voltage range
Battery absent detection not functional
V(IN)
Supply voltage range
Battery absent detection functional
TJ
Junction temperature
RTMR
33K ≤ RTMR≤ 100K
TYP
MAX
UNIT
V
3.5
4.35
4.35
16.5
V
0
125
°C
DISSIPATION RATINGS (1)
(1)
2
PACKAGE
θJC (°C/W)
θJA (°C/W)
10-pin DRC
3.21
46.87
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu
pad on the board. This is connected to the ground plane by a 2×3 via matrix.
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
over recommended operating, TJ = 0 –125°C range, See the Application Circuits section, typical values at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
1.5
3.0
V
130
mV
POWER DOWN THRESHOLD – UNDERVOLTAGE LOCKOUT
V(UVLO)
V(IN) = 0 V, increase V(OUT): 0 → 3 V OR
V(OUT) = 0 V, increase V(IN): 0 → 3 V,
CE = LO (1)
Power down threshold
INPUT POWER DETECTION, CE = HI or LOW, V(IN) > 3.5 V
VIN(DT)
Input power detection threshold
V(IN) detected at [V(IN) – V(OUT)] > VIN(DT)
VHYS(INDT)
Input power detection hysteresis
Input power not detected at
[V(IN)– V(OUT)] < [VIN(DT)– VHYS(INDT)]
30
TDGL(INDT1)
Deglitch time, input power detected
status
PG:HI → LO, Thermal regulation loop not active,
RTMR = 50 KΩ or V(TMR) = OPEN
1.5
TDGL(NOIN)
Delay time, input power not detected
status
PG: LO →HI after TDGL(NOIN)
TDLY(CHGOFF)
Charger off delay
Charger turned off after TDLY(CHGOFF), Measured
from PG: LO → HI; Timer reset after
TDLY(CHGOFF)
mV
28
3.5
ms
10
µs
32
ms
INPUT OVERVOLTAGE PROTECTION
V(OVP)
Input overvoltage detection threshold
V(IN) increasing
VHYS(OVP)
Input overvoltage hysteresis
V(IN) decreasing
TDGL(OVDET)
Input overvoltage detection delay
TDGL(OVNDET)
Input overvoltage not detected delay
bq24060/61/63
bq24064
6.2
6.5
7.0
10.2
10.5
11.7
V
bq24060/61/63
0.1
0.2
bq24064
0.3
0.5
CE = HI or LO, Measured from V(IN) > V(OVP) to
PG: LO → HI; VIN increasing
10
100
µs
CE = HI or LO, Measured from V(IN) < V(OVP)
to PG: HI → LO; V(IN) decreasing
10
100
µs
V
QUIESCENT CURRENT
V(IN) = 6 V
100
V(IN) = 16.5 V
300
200
ICC(CHGOFF)
IN pin quiescent current, charger off
Input power detected, CE =
HI
ICC(CHGON)
IN pin quiescent current, charger on
Input power detected, CE = LO, VBAT = 4.5 V
4
6
mA
IBAT(DONE)
Battery leakage current after termination
into IC
Input power detected, charge terminated,
CE = LO
1
5
µA
IBAT(CHGOFF)
Battery leakage current into IC, charger
off
Input power detected, CE = HI OR
input power not detected, CE = LO
1
5
µA
µA
TS PIN COMPARATOR
V(TS1)
Lower voltage temperature threshold
Hot detected at V(TS) < V(TS1); NTC thermistor
29
30
31 %V(IN)
V(TS2)
Upper voltage temperature threshold
Cold detected at V(TS) > V(TS2); NTC thermistor
60
61
62 %V(IN)
Hysteresis
Temp OK at V(TS) > [ V(TS1) + VHYS(TS) ] OR
V(TS) < [ V(TS2)– VHYS(TS) ]
2
%V(IN)
VIL
Input (low) voltage
V(CE) increasing
VIH
Input (high) voltage
V(CE) decreasing
VHYS(TS)
CE INPUT
0
1
2.0
V
V
STAT1, STAT2 AND PG OUTPUTS , V(IN) ≥ VO(REG) + V(DO-MAX)
VOL
Output (low) saturation voltage
Ioutput = 5 mA (sink)
0.5
V
THERMAL SHUTDOWN
T(SHUT)
Temperature trip
Junction temperature, temp rising
T(SHUTHYS)
Thermal hysteresis
Junction temperature
(1)
155
°C
20
°C
Specified by design, not production tested.
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating, TJ = 0–125°C range, See the Application Circuits section, typical values at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REGULATION, V(IN) ≥ VO(REG) + V(DO-MAX), I(TERM) < I(OUT) < IO(OUT), CHARGER ENABLED, NO FAULT CONDITIONS
DETECTED
VO(REG)
Output voltage
VO(TOL)
Voltage regulation accuracy
V(DO)
Dropout voltage, V(IN) – V(OUT)
bq24060/61/63/64
4.20
TA = 25°C
–0.5%
V
0.5%
–1%
1%
I(OUT) = 1 A
750
mV
1000
mA
V
CURRENT REGULATION , V(IN) > V(OUT) > V(DO-MAX), CHARGER ENABLED, NO FAULT CONDITIONS DETECTED
IO(OUT)
Output current range
V(BAT) > V(LOWV), IO(OUT) = I(OUT) = K(SET)×
V(SET)/RSET
100
V(SET)
Output current set voltage
V(ISET) = V(SET), V(LOWV) < V(BAT) ≤ VO(REG)
2.45
2.50
2.55
K(SET)
Output current set factor
100 mA ≤ IO(OUT)≤ 1000 mA
315
335
355
315
372
430
RISET
External resistor range
10 mA ≤ IO(OUT) < 100 mA
mA kW
Volts
Resistor connected to ISET pin
0.7
10
kΩ
VOLTAGE AND CURRENT REGULATION TIMING, V(IN) > V(OUT) + V(DO-MAX), CHARGER ENABLED, NO FAULT CONDITIONS
DETECTED, RTMR = 50K or V(TMR) = OPEN; Thermal regulation loop not active
TPWRUP(CHG)
Input power detection to full
charge current time delay
Measured from PG:HI → LO to I(OUT) > 100 mA,
CE = LO, IO(OUT) = 1 A, V(BAT) = 3.5 V
25
35
ms
TPWRUP(EN)
Charge enable to full charge
current delay
Measured from CE:HI → LO to I(OUT) >100 mA,
IO(OUT) = 1A, V(BAT)= 3.5 V, V(IN) = 4.5 V, Input
power detected
25
35
ms
TPWRUP(LDO)
Input power detection to voltage
regulation delay, LDO mode set,
no battery or load connected
Measured from PG:HI → LO to V(OUT) > 90% of
charge voltage regulation;
V(TMR) = OPEN, LDO mode set, no battery and no
load at OUT pin, CE = LO
25
35
ms
PRECHARGE AND OUTPUT SHORT-CIRCUIT CURRENT REGULATION, V(IN)–V(OUT) > V(DO-MAX) , V(IN) ≥ 4.5V, CHARGER
ENABLED, NO FAULT CONDITIONS DETECTED, RTMR = 50K or V(TMR)=OPEN; Thermal regulation loop not active
V(LOWV)
Precharge to fast-charge transition
V(BAT) increasing
threshold
2.8
2.95
3.15
V(SC)
Precharge to short-circuit
transition threshold
V(BAT) decreasing
1.2
1.4
1.6
V(SCIND)
Short-circuit indication
V(BAT) decreasing
1.6
1.8
2.0
IO(PRECHG)
Precharge current range
V(SC) < VI(BAT) < V(LOWV), t < T(PRECHG)
IO(PRECHG) = K(SET)× V(PRECHG)/R(ISET)
10
V(PRECHG)
Precharge set voltage
V(ISET) = V(PRECHG), V(SC) < VI(BAT) < V(LOWV),
t < T(PRECHG)
Output shorted regulation current
VSS≤ V(BAT)≤ V(SCI),
IO(SHORT) = I(OUT), V(BAT)=
VSS, Internal pullup resistor
IO(SHORT)
VPOR < VIN < 6.0
V
V
V
100
mA
mV
225
250
280
15
22
30
mA
6.0 V < VIN <
VOVP
25
TEMPERATURE REGULATION (Thermal regulation™), CHARGER ENABLED, NO FAULT CONDITIONS DETECTED
4
TJ(REG)
Temperature regulation limit
V(IN) = 5.5 V, V(BAT) = 3.2 V, Fast charge
current set to 1A
I(MIN_TJ(REG))
Minimum current in thermal
regulation
V(LOWV) < V(BAT) < VO(REG), 0.7kΩ < RISET
< 3.5kΩ
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101
112
125
°C
200
250
mA
bq2406x
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating, TJ = 0–125°C range, See the Application Circuits section, typical values at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE TERMINATION DETECTION, VO(REG) = 4.2 V, CHARGER ENABLED, NO FAULT CONDITIONS DETECTED, Thermal
regulation LOOP NOT ACTIVE, RTMR = 50K or TMR pin OPEN
I(TERM)
Termination detection current
range
V(BAT) > V(RCH), I(TERM) = K(SET)× V(TERM)/RISET
V(TERM)
Charge termination detection
set voltage (1)
V(BAT) > V(RCH)
TDGL(TERM)
Deglitch time, termination
detected
10
100
mA
225
250
275
mV
V(ISET) decreasing
15
25
35
ms
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold detection
[VO(REG)–V(BAT) ] > V(RCH)
75
100
135
mV
TDGL(RCH)
Deglitch time, recharge
detection
V(BAT) decreasing
15
25
35
ms
TIMERS, CE = LO, CHARGER ENABLED, NO FAULT CONDITIONS DETECTED, V(TMR) < 3 V, TIMERS ENABLED
T(CHG)
Charge safety timer range
T(CHG) = K(CHG)× RTMR ; thermal loop not active
K(CHG)
Charge safety timer constant
V(BAT) > V(LOWV)
0.08
T(PCHG)
Pre-charge safety timer range
T(PCHG) = K(PCHG)× T(CHG) ; Thermal regulation
loop not active
1080
K(PCHG)
Pre-charge safety timer
constant
V(BAT) < V(LOWV)
0.08
0.1
0.12
Charge timer and termination
enable threshold
[Charge timer AND
termination disabled] at V(TMR) bq24060/61/64
> VTMR(OFF)
2.5
3.0
3.5
V
Charge timer enable threshold
[Charge timer disabled] at
V(TMR) > VTMR(OFF)
TMR pin source current
V(TMR) = 3.5 V, V(IN) = 4.5 V
1
6
µA
1
3.2
mA
VTMR(OFF)
ITMR
3
0.1
10
hours
0.12
hr/kΩ
3600
sec
bq24063
BATTERY DETECTION THRESHOLDS
IDET(DOWN)
Battery detection current (sink)
2 V < V(BAT) < VO(REG)
IDET(UP)
Battery detection current
(source)
2 V < V(BAT) < VO(REG)
T(DETECT)
Battery detection time
2 V < V(BAT) < VO(REG), Thermal regulation loop not
active; RTMR = 50 kΩ, IDET(down) or IDET (UP)
2
IO(PRECHG)
85
120
150
ms
–12
–10
–8
mA
TIMER FAULT RECOVERY
I(FAULT)
Fault Current (source)
V(OUT) < V(RCH)
CHARGE OVERCURRENT DETECTION, V(IN) ≥ 4.5 V, CHARGER ENABLED
ICH(OI)
Charge overcurrent detection
threshold
V(ISET) = VSS
TDGL(OI)
Overcurrent detection delay
time
Measured from V(ISET) = VSS to IO(OUT) = 0
(1)
2
A
100
µs
The voltage on the ISET pin is compared to the V(TERM) voltage to determine when the termination should occur.
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
DEVICE INFORMATION
PIN ASSIGNMENT
VSS
STAT 2
STAT 1
TMR
IN
VSS
STAT 2
STAT 1
TMR
IN
VSS
STAT 2
STAT 1
TMR
IN
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
bq24060/64 DRC
(TOP VIEW)
bq24063 DRC
(TOP VIEW)
bq24061 DRC
(TOP VIEW)
6
7
8
9
10
6
7
8
9
10
6
7
8
9
10
ISET
PG
TS
BAT
OUT
ISET
PG
CE
BAT
OUT
ISET
CE
TE
BAT
OUT
TERMINAL FUNCTIONS, REQUIRED COMPONENTS
TERMINAL NO.
NAME
DESCRIPTION AND REQUIRED COMPONENTS
bq24061
bq24063
IN
1
1
1
I
Charge Input Voltage and internal supply. Connect a 1- µF (minimum)
capacitor from IN to VSS. CIN≥ COUT
TMR
2
2
2
I
Safety Timer Program Input, timer disabled if floating. Connect a resistor to
VSS pin to program safety timer timeout value
STAT1
3
3
3
O
Charge Status Output 1 (open-collector, seeTable 3)
STAT2
4
4
4
O
Charge Status Output 2 (open-collector, see Table 3)
VSS
5
5
5
I
Ground
ISET
6
6
6
O
Charge current set point, resistor connected from ISET to VSS sets charge
current value. Connect a 0.47-µF capaciator from BAT to ISET.
PG
7
7
—
O
Power Good status output (open-collector), active low
CE
—
8
7
I
Charge enable Input. CE = LO enables charger. CE = HI disables charger.
TE
—
—
8
I
Termination enable Input. TE = LO enables termination detection and battery
absent detection. TE = HI disables termination detection and battery absent
detection.
TS
8
—
—
I
Temperature Sense Input, connect to battery pack thermistor. Connect an
external resistive divider to program temperature thresholds.
BAT
9
9
9
I
Battery Voltage Sense Input. Connect to the battery positive terminal. Connect
a 200-Ω resistor from BAT to OUT.
OUT
10
10
10
O
Charge current output. Connect to the battery positive terminal. Connect a 1µF (minimum) capacitor from OUT to VSS.
Exposed
Thermal
Pad
6
I/O
bq24060/64
Pad
Pad
Pad
There is an internal electrical connection between the exposed thermal pad
and Vss pin of the IC. The exposed thermal pad must be connected to the
same potential as the VSS pin on the printed circuit board. Do not use the
thermal pad as the primary ground input for the IC. VSS pin must be
connected to ground at all times.
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
TYPICAL OPERATING CHARACTERISTICS
Measured using the typical application circuit shown previously.
THERMAL LOOP OPERATION
WITH POWERPAD ATTACHED
THERMAL LOOP AND DTC OPERATION
1.75
1.6
6
1.50
1.4
5
1.25
4
1
12
10
IBAT
0.75
3
VISET
2
Battery Current - A
Safety Timer
Battery Current - A
Voltage - V
VIN
1.2
8
1
0.8
0
1.50
2
t - Time - s
2.50
2
0.2
0
1
4
0.4
0.25
0.50
IBAT
0.6
0.50
1
0
6
0
0
0
3
TCHG - Safety Timer - Hrs
7
0.50
Figure 1.
1
1.50
2
t - Time - s
2.50
3
Figure 2.
PACK REMOVAL TRANSIENT
5
4.75
INPUT OVP RECOVERY TRANSIENTS
1
8
0.8
7
2
1.80
0.2
IBAT
3.75
0
Voltage - V
0.4
4
VIN
6
Battery Current - A
4.25
5
1.40
1.20
1
4
IBAT
3
0.80
0.60
3.50
2
VPG
-0.2
3.25
3
0
0.5
1
1.5
t - Time - mS
2
1
-0.4
2.5
0.40
0.20
0
0
0
5
Figure 3.
10 15
20 25 30 35
t - Time - mS
40 45 50
Figure 4.
PG DEGLITCH TIME
9
8
7
VIN
Voltage - V
Battery Voltage - V
0.6
Charge Current - A
1.60
VBAT
4.50
6
5
4
VPG
3
2
1
0
0
1
2
3
t - Time - mS
4
5
Figure 5.
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SLUS689A – JUNE 2006 – REVISED OCTOBER 2006
TYPICAL OPERATING CHARACTERISTICS (continued)
Measured using the typical application circuit shown previously.
FAST-CHARGE CURRENT
vs
BATTERY VOLTAGE
FAST-CHARGE CURRENT
vs
BATTERY VOLTAGE
52.5
1000
104.5
995
52
104
990
51.5
103.5
103
85°C
102.5
25°C
102
101.5
0°C
985
980
970
85°C
965
101
960
955
2.20
2.40
2.60
Battery Voltage - V
2.80
3.20
3.40
3.60
3.80
Battery Voltage - V
85°C
49
3
4
3.20
3.40
3.60
Battery Voltage - V
3.80
4
Figure 8. LOW CHARGE RATE
KSET LINEARITY
vs
CHARGE CURRENT
BATTERY REGULATION VOLTAGE
vs
INPUT VOLTAGE
4.202
350
400
390
0°C
4.200
345
380
4.198
Battery Voltage - V
85°C
370
85°C
350
0°C
340
KSET - A/A
340
KSET - A/A
50
49.5
Figure 7. HIGH CHARGE RATE
KSET LINEARITY
vs
CHARGE CURRENT
330
50.5
48
47.5
Figure 6. HIGH CHARGE RATE
360
25°C
0°C
51
48.5
950
3
3
25°C
0°C
975
100.5
100
2
Charge Current - mA
105
Charge Current - mA
Charge Current - mA
PRE-CHARGE CURRENT
vs
BATTERY VOLTAGE
25°C
0°C
335
25°C
330
25°C
4.196
4.194
4.192
4.190
320
325
300
25 35 45 55 65 75 85 95 105 115 125
Battery Charge Current -
320
0
100 200 300 400 500 600 700 800 900 1000
Battery Charge Current - mA
Figure 9. 2.0 < V(BAT) < 3.0 V
Figure 10. 3.0 < V(BAT) < 4.0 V
DROPOUT VOLTAGE
vs
TEMPERATURE
0.400
V(DO) - Droput Voltage - V
0.375
0.350
0.325
0.300
0.275
0.250
0.225
0.200
-15
5
25
45
65
85
TA - Temperature - °C
105
Figure 12.
8
85°C
4.188
310
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125
4.186
4.5
6.5
8.5
10.5 12.5
Input Voltage - V
Figure 11.
14.5
16.5
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FUNCTIONAL DESCRIPTION
The charge current is programmable using external components (RISET resistor). The charge process starts
when an external input power is connected to the system, the charger is enabled by CE = LO and the battery
voltage is below the recharge threshold, V(BAT) < V(RCH). When the charge cycle starts a safety timer is
activated, if the safety timer function is enabled. The safety timer timeout value is set by an external resistor
connected to TMR pin.
When the charger is enabled two control loops modulate the battery switch drain to source impedance to limit
the BAT pin current to the programmed charge current value (charge current loop) or to regulate the BAT pin
voltage to the programmed charge voltage value (charge voltage loop). If V(BAT) < V(LOWV) (3 V typical) the
BAT pin current is internally set to 10% of the programmed charge current value.
A typical charge profile is shown below, for an operation condition that does not cause the IC junction
temperature to exceed TJ(REG), (112°C typical).
VO(REG)
PreConditioning
Phase
Voltage Regulation and
Charge Termination
Phase
Current
Regulation
Phase
DONE
IO(OUT)
FAST-CHARGE
CURRENT
Battery Current,
I(BAT)
Battery Voltage,
V(BAT)
v(LOWV)
Charge
Complete
Status,
Charger
Off
IO(PRECHG), I(TERM)
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
T(PRECHG)
T(CHG)
DONE
Figure 13. Charging Profile With TJ(REG)
If the operating conditions cause the IC junction temperature to exceed TJ(REG), the charge cycle is modified,
with the activation of the integrated thermal control loop. The thermal control loop is activated when an internal
voltage reference, which is inversely proportional to the IC junction temperature, is lower than a fixed,
temperature stable internal voltage. The thermal loop overrides the other charger control loops and reduces the
charge current until the IC junction temperature returns to TJ(REG), effectively regulating the IC junction
temperature.
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IN
VREF
VTJ
Thermal
Loop
BATTERY
SWITCH
I(BAT)
OUT
I(BAT) / K(SET)
ISET
V(BAT)
VO(REG)
System Voltage
Regulation Loop
BAT
Figure 14. Thermal Regulation Circuit
A modified charge cycle, with the thermal loop active, is shown in Figure 15.
VO(REG)
PreConditioning
Phase
Thermal
Regulation
Phase
Current
Regulation
Phase
Voltage Regulation and
Charge Termination
Phase
DONE
IO(OUT)
Battery Current,
I(BAT)
FAST-CHARGE
CURRENT
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
Battery
Voltage,
V(BAT)
Charge
Complete
Status,
Charger
Off
VO(LOWV)
IO(PRECHG),I(TERM)
T(THREG)
temperature , Tj
T(PRECHG)
T(CHG)
Figure 15. Charge Profile, Thermal Loop Active
10
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FUNCTIONAL BLOCK DIAGRAM
BACKGATE BIAS
V(IN)
I(OUT)
OUT
IN
V(OUT)
PRE_CHARGE
IOUT) / K(SET)
ISET
VO(REG)
V(ISET)
I(DETECT)
V(IN)
V(SET)
V(PRECHG)
I(FAULT )
TJ
BATTERY ABSENT DETECTION
AND SHORT RECOVERY
T J(REG)
CHG ENABLE
V(IN)
Dynamically
Controlled
Oscillator
V(SET) , V(PRECHG)
+
- V
OC
TDGL(CHOVC)
Deglitch
TMR
+
V(IN)
VTMR(OFF)
TDGL(INDT)
Deglitch
Over_current
+
+
V(IN)
-
V(OUT)+VIN(DT )
Input Power
Detected
TS
Timer
Fault
+
V(IN)
Timer
V(IN)
Disable
+
V(OVP)
BAT
+
V (RCH)
-
TDGL(OVP)
Deglitch
Input Over-Voltage
TDGL(RCH)
Deglitch
Recharge
Precharge
+
V(LOW)
V (TERM )
V(ISET)
POR
Suspend
Thermal
Shutdown
Internal
Voltage
References
CE
CHARGE
CONTROL,
TIMER and
DISPLAY LOGIC
+
-
REFERENCE
AND
BIAS
PG
STAT1
TDGL(TERM)
Deglitch
Terminate
STAT2
VSS
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APPLICATION CIRCUITS
The typical application diagrams shown here are configured for 750 mA fast charge current, 75 mA pre-charge
current, 5 hour safety timer and 30 min pre-charge timer.
Li-Ion or Li-Pol
Battery Pack
bq24060/64
Input Power
1
RTMR
C3
4.7 mF
R1
R2
1.5 kW 1.5 kW
2
OUT 10
IN
TMR
BAT 9
STAT 1
TS 8
STAT 2
PG
49.9 kW
RED
3
Pack+
R8
+
C2
200 W
2.2 mF
C1
4
GREEN
5
0.47 mF
7
ISET 6
Vss
Pack-
RT1
10 kW
RT2
33.2 kW
R ISET
1.13 kW
Power
Good
Li-Ion or Li-Pol
Battery Pack
bq24061
Input Power
1
RTMR
C3
4.7 mF
R1
1.5 kW
R2
1.5 kW
2
IN
3
RED
GREEN
4
5
10
OUT
TMR
49.9 kW
CE
STAT 2
PG
Pack+
R8
9
BAT
STAT 1
Vss
TEMP
+
C2
200 W
1 mF
Pack-
8
C1
7
0.47 mF
6
ISET
RSET
1.13 kW
Charge Enable
and Power Good
Li-Ion or Li-Pol
Battery Pack
bq24063
Input Power
1
RTMR
C3
4.7 mF
R1
1.5 kW
R2
1.5 kW
2
IN
TMR
49.9 kW
RED
GREEN
3
4
5
OUT
BAT
Pack+
R8
9
C2
1 mF
200 W
TE
STAT 2
CE
ISET
+
Pack-
8
STAT 1
Vss
10
C1
7
0.47 mF
6
RSET
1.13 kW
Charge and
Termination Enable
NOTE: Temp window set between 0°C and 45°C for application w/TS pin.
Figure 16. Application Circuits
OPERATING MODES
Power Down
The bq2406x family is in a power-down mode when the input power voltage (IN) is below the power-down
threshold V(PDWN). During the power down mode all IC functions are off, and the host commands at the control
pins are not interpreted. The integrated power mosfet connected between IN and OUT pins is off, the status
output pins STAT1 and STAT2 are set to high impedance mode and PG output is set to the high impedance
state.
12
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Sleep Mode
The bq2406x enters the sleep mode when the input power voltage (IN) is above the power down threshold
V(PDWN) but still lower than the input power detection threshold, V(IN) < V(OUT) + VIN(DT).
During the sleep mode the charger is off, and the host commands at the control pins are not interpreted. The
integrated power mosfet connected between IN and OUT pins is off, the status output pins STAT1 and STAT2
are set to the high impedance state and the PG output indicates input power not detected.
The sleep mode is entered from any other state, if the input power (IN) is not detected.
Overvoltage Lockout
The input power is detected when the input voltage V(IN) > V(OUT) + VIN(DT). When the input power is detected
the bq2460x transitions from the sleep mode to the power-on-reset mode. In this mode of operation an internal
timer T(POR) is started and internal blocks are reset (power-on-reset). Until the timer expires the STAT1 and
STAT2 outputs indicate charger OFF, and the PG output indicates the input power status as not detected.
At the end of the power-on-reset delay the internal comparators are enabled, and the STAT1, STAT2 and PG
pins are active.
Stand-By Mode
In the bq24061/63 the stand-by mode is started at the end of the power-on-reset phase, if the input power is
detected and CE = HI. In the stand-by mode selected blocks in the IC are operational, and the control logic
monitors system status and control pins to define if the charger will set to on or off mode. The quiescent current
required in stand-by mode is 100 µA typical.
If the CE pin is not available the bq2406x enters the begin charge mode at the end of the power-on-reset phase.
Begin Charge Mode
All blocks in the IC are powered up, and the bq2406x is ready to start charging the battery pack. A new charge
cycle is started when the control logic decides that all conditions required to enable a new charge cycle are met.
During the begin charge phase all timers are reset, after that the IC enters the charging mode.
Charging Mode
When the charging mode is active the bq2406x executes the charging algorithm, as described in the operational
flow chart, Figure 17.
Suspend Mode
The suspend mode is entered when the pack temperature is not within the valid temperature range. During the
suspend mode the charger is set to off, but the timers are not reset.
The normal charging mode resumes when the pack temperature is within range.
LDO Mode Operation
The LDO Mode (TMR pin open circuit) disables the charging termination circuit, disables the battery detect
routine and holds the safety timer clock in reset. This is often used for operation without a battery or in
production testing. This mode is different than a typical LDO since it has different modes of operation, and
delivers less current at lower output voltages. See Figure 24 for the output current versus the output voltage.
Note that a load on the output prior to powering the device may keep the part in short-circuit mode. Also, during
normal operation, exceeding the programmed fast charge level causes the output to drop, further restricting the
output power, and soon ends up in short-circuit mode. Operation with a battery or keeping the average load
current below the programmed current level prevents this type of latch up. The out pin current can be monitored
via the ISET pin. If in LDO mode without a battery present, It is recommended that a 200-Ω feedback resistor,
R8, be used, see Figure 16.
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STATE MACHINE DIAGRAM
CHARGING
RECHARGE
DETECTION
No
V(TS) >V(TS2) OR
V(TS) < V( TS1)
VI(BAT ) < V(RCH )
Yes
Suspend
Set Charge Off,
Stop timers,
Keep timer count,
STATn=Hi-Z
V(TS) < V(TS2) AND
V(TS) > V( TS1)
V(OUT) <V(SC)
Enable IO(SHORT)
current
T (PRCH) OFF
ANY
STATE
No
VDETECT
ENABLED
ANY
STATE
Yes
V(OUT)
<V(LOWV)
Reset T(CHG)
Regulate
IO(PRECHG)
T(PRCH) ON
Indicate ChargeIn-Progress
Yes
No
Enable I(DETECT) for
t(DETECT)
No
Yes
Reset T(PRCH)
T (CHG) ON
Battery Present
VI(BAT) <V(LOWV)
No
GO TO
Begin Charge
Indicate ChargeIn-Progress
Yes
BATTERY
DETECTION
No OR
Timers disabled
Regulate Current
or Voltage
Apply IO(PRECHG) for
t(DETECT)
No
Yes
Yes
No
T(CHG) Expired?
T (PRCH)
Expired?
VI(BAT ) > V(RCH )
No OR
timers disabled
Yes
ANY
STATE
V(OUT)
<V( LOWV)
Yes AND
timers enabled
Yes AND
Timers enabled
Battery Absent
Charge Off
T(DETECT) Fault
Yes
V(OUT)
<V(LOWV)
Fault Condition
V(TS) >V (TS2) OR
V(TS) < V (TS1)
Suspend
Set Charge Off,
Stop timers,
Keep timer count,
STATn=Hi-Z
V(TS) >V(TS2) OR
V(TS) < V(TS1)
No
OR
termination
disabled
ANY
STATE
V(TS) < V(TS2) AND
V(TS) > V(TS1)
Indicate Fault
No
ITERM
detection?
V(OUT)
> V(RCH)?
Stand-by
/CE=HI OR
V(IN)>V( OVP)
STATn set to HI-Z,
update /PG status,
enable control logic
Yes AND
termination
enabled
Yes
/CE=LO AND
[V(BAT)+V(INDT) ]
< V(IN) <
V( OVP)
No
Enable IFAULT
current
Termination
No
Indicate
Termination
Yes
T (POR)
Expired?
Yes
No
Power-on-reset
Turn off charger ,
STATn and PG
set to HI-Z,
reset timers
Begin Charge
Disable IFAULT
current
Reset ALL TImers
V(IN) > V(POR) AND
V(IN) > V(OUT)+VIN(DT)
FAULT
RECOVERY
Sleep
[V(IN) -V(OUT)] <
[VIN(DT) - VHYS(INDT) ]
Turn off charger ,
STATn , /PG set to
HI-Z , monitor
input power
Done
Turn off charger ,
Indicate
Charge done
Reset timers
V(IN) > V(POR)
V(IN) < V (POR)
Power down
All IC functions off
STATn and PG
set to HI-Z
START -UP
ANY
STATE
Figure 17. Operational Flow Chart
14
V(OUT)
> V(RCH )?
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CONTROL LOGIC OVERVIEW
An external host can enable or disable the charging process using a dedicated control pin, CE. A low-level
signal on this pin enables the charge, and a high-level signal disables the charge. The bq2460x is in stand-by
mode with CE = HI. When the charger function is enabled (CE = LO) a new charge is initiated.
Table 1 describes the charger control logic operation, in bq2460x versions without the TS pin the pack temp
status is internally set to OK.
Table 1. Control Logic Functionality
bq2460X
OPERATION
MODE
CE
INPUT
POWER
TIMER
FAULT
(latched)
OUTPUT
SHORT
CIRCUIT
TERMINATION
(latched)
PACK
TEMP
THERMAL
SHUTDOWN
POWER
DOWN
CHARGER
POWER
STAGE
POWER
DOWN
LO
Low
X
X
X
X
X
Yes
OFF
SLEEP
X
Not
Detected
X
X
X
X
X
No
OFF
STANDBY
HI
Detected
X
X
X
X
X
No
OFF
SEE STATE
DIAGRAM
LO
Detected
X
Yes
X
X
X
No
LO
Detected
No
No
Yes
X
X
No
LO
Detected
Yes
No
No
X
X
No
IFAULT
LO
Detected
No
No
Yes
Absent
TJ < TSHUT
No
IDETECT
LO
Detected
No
No
No
Hot or
Cold
TJ < TSHUT
No
OFF
LO
Detected
No
No
No
Ok
TJ < TSHUT
No
OFF
LO
Over
Voltage
No
No
No
Ok
TJ < TSHUT
No
OFF
LO
Detected
No
No
No
Ok
TJ < TSHUT
No
ON
CHARGING
OFF
In both STANDBY and SUSPEND modes the charge process is disabled. In the STANDBY mode all timers are
reset; in SUSPEND mode the timers are held at the count stored when the suspend mode was set.
The timer fault, termination and output short circuit variables shown in the control logic table are latched in the
detection circuits, outside the control logic. Refer to the timers, termination and short circuit protection sections
for additional details on how those latched variables are reset.
TEMPERATURE QUALIFICATION (Applies only to versions with TS pin option)
The bq2406x devices continuously monitor the battery temperature by measuring the voltage between the TS
and VSS pins. The IC compares the voltage on the TS pin against the internal V(TS1) and V(TS2) thresholds to
determine if charging is allowed. Once a temperature outside the V(TS1) and V(TS2) thresholds is detected the IC
immediately suspends the charge. The IC suspends charge by turning off the power FET and holding the timer
value (i.e., timers are NOT reset). Charge is resumed when the temperature returns to the normal range.
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VIN
Charge Suspend
VC(TS2)
0.6* VIN
Normal Temperature
Charge Range
VC(TS1)
0.3* VIN
Charge Suspend
Figure 18. Battery Temperature Qualification With NTC Thermistor
The external resistors RT1 and RT2 (see application diagram) enable selecting a temperature window. If RTC and
RTH are the thermistor impedances for the Cold and Hot thresholds the values for RT1 and RT2 can be calculated
as follows, for a NTC (negative temperature coefficient) thermistor. Solve for RT2 first and substitute into RT1
equation.
2.5 R TCRTH
R T2 +
RTC * 3.5 RTH
(1)
R T1 +
7 R THRT2
3 ƪRTH ) RT2ƫ
(2)
Applying a fixed voltage, 1/2 Vin (50% resistor divider from Vin to ground), to the TS pin to disable the
temperature sensing feature.
INPUT OVERVOLTAGE DETECTION, POWER GOOD STATUS OUTPUT
The input power detection status for pin IN is shown at the open collector output pin PG.
Table 2. Input Power Detection Status
INPUT POWER DETECTION (IN)
PG STATE
NOT DETECTED
High impedance
DETECTED, NO OVERVOLTAGE
LO
DETECTED, OVERVOLTAGE
High impedance
The bq2406x detects an input overvoltage when V(IN) > V(OVP). When an overvoltage protection is detected the
charger function is turned off and the bq2460x is set to standby mode of operation. The OVP detection is not
latched, and the IC returns to normal operation when the fault condition is removed.
CHARGE STATUS OUTPUTS
The open-collector STAT1 and STAT2 outputs indicate various charger operations as shown in Table 3. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-collector transistor is turned off. When termination is disabled (TMR pin floating or TE = Hi, bq24063) the
Done state is not available; the status LEDs indicate fast charge if VBAT > VLOWV and precharge if VBAT < VLOWV.
The available output current is a function of the OUT pin voltage, See Figure 24.
16
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Table 3. Charge Status
Charge State
(1)
STAT1
STAT2
Precharge in progress
ON
ON
Fast charge in progress
ON
OFF
Done (termination enabled only)
OFF
ON
OFF
OFF
Charge Suspend (temperature)
Timer Fault
Charger off
Selected Input power overvoltage detected
Battery absent
Batteryshort
(1)
Pulse loading on the OUT pin may cause the IC to cycle between Done and charging states (LEDs
Flashing)
BATTERY CHARGING: CONSTANT CURRENT PHASE
The bq2406x family offers on-chip current regulation. The current regulation is defined by the value of the
resistor connected to ISET pin.
During a charge cycle the fast charge current IO(OUT) is applied to the battery if the battery voltage is above the
V(LOWV) threshold (2.95 V typical):
V(SET) KSET)
I(OUT) + I O(OUT) +
RISET
(3)
Where K(SET) is the output current set factor and V(SET) is the output current set voltage.
During a charge cycle if the battery voltage is below the V(LOWV) threshold a pre-charge current I(PRECHG) is
applied to the battery. This feature revives deeply discharged cells.
V(PRECHG) KSET)
I O(OUT)
I(OUT) + I (PRECHG) +
X
10
RISET
(4)
Where K(SET) is the output current set factor and V(PRECHG) is the precharge set voltage.
At low constant current charge currents, less than 350 mA, it is recommended that a 0.47-µF capacitor be
placed between the ISET and BAT pins to insure stability, see Figure 16.
CHARGE CURRENT TRANSLATOR
When the charge function is enabled internal circuits generate a current proportional to the charge current at the
ISET pin. This current, when applied to the external charge current programming resistor RISET generates an
analog voltage that can be monitored by an external host to calculate the current sourced from the OUT pin.
R ISET
V(ISET) + I(OUT)
K(SET)
(5)
BATTERY VOLTAGE REGULATION
The battery pack voltage is sensed through the BAT pin, which is tied directly to the positive side of the battery
pack. The bq2406x monitors the battery pack voltage between the BAT and VSS pins. When the battery voltage
rises to VO(REG) threshold the voltage regulation phase begins and the charging current begins to taper down.
The voltage regulation threshold VO(REG) is fixed by an internal IC voltage reference.
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PRE-CHARGE TIMER
The bq2406x family activates an internal safety timer during the battery pre-conditioning phase. The charge
safety timer time-out value is set by the external resistor connected to TMR pin, RTMR and the timeout constants
K(PCHG) and T(CHG) :
T(PCHG) = K(PCHG)× T(CHG)
The pre-charge timer operation is detailed in Table 4.
Table 4. Pre-Charge Timer Operational Modes
bq2460X MODE
V(OUT) > V(LOWV)
PRE-CHARGE TIMER MODE
STANDBY (CE = Hi)
X
RESET
CHARGING
Yes
RESET
SUSPEND (TS out of range)
Yes
RESET
SUSPEND (TS out of range)
No
Hold
CHARGING, TMR PIN NOT OPEN
No
COUNTING, EXTERNAL PROGRAMMED RATE
X
RESET
CHARGING, TMR PIN OPEN
In SUSPEND mode the pre-charge timer is put on hold (i.e., pre-charge timer is not reset), normal operation
resumes when the timer returns to the normal operating mode (COUNTING). If V(BAT) does not reach the
internal voltage threshold V(LOWV) within the pre-charge timer period a fault condition is detected, the charger is
turned off and the pre-charge safety timer fault condition is latched.
When the pre-charge timer fault latch is set the charger is turned off. Under those conditions a small current
IFAULT is applied to the OUT pin, as long as input power (IN) is detected AND V(OUT) < V(LOWV), as part of a
timer fault recovery protocol. This current allows the output voltage to rise above the pre-charge threshold
V(LOWV), resetting the pre-charge timer fault latch when the pack is removed. Table 5 further details the
pre-charge timer fault latch operation.
Table 5. Pre-Charge Timer Latch Functionality
PRE-CHARGE TIMER FAULT ENTERED WHEN
PRE-CHARGE TIMER FAULT LATCH RESET AT
CE rising edge or OVP detected
Pre-charge timer timeout AND V(OUT) > V(LOW
V)
Input power removed (not detected)
Timer function disabled
THERMAL PROTECTION LOOP
An internal control loop monitors the bq2406x junction termperature (TJ) to ensure safe operation during high
power dissipations and or increased ambient temperatures. This loop monitors the bq2406x junction
temperature and reduces the charge current as necessary to keep the junction temperature from exceeding,
TJ(REG), (112°C, typical).
The bq2406x's thermal loop control can reduce the charging current down to ~200mA if needed. If the junction
temperature continues to rise, the IC will enter thermal shutdown.
THERMAL SHUTDOWN AND PROTECTION
Internal circuits monitor the junction temperature, TJ, of the die and suspends charging if TJ exceeds an internal
threshold T(SHUT) (155°C typical). Charging resumes when TJ falls below the internal threshold T(SHUT) by
approximately 20°C.
18
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Thermal Regulation
Normal Operation
Thermal Shutdown
800
175
IBAT
700
Battery Current - mA
600
125
500
TJ Junction Temperature
400
100
300
75
200
TJ - Junction Temperature - °C
150
50
100
0
4
6
8
10
12
14
16
25
18
VI - Input Voltage - V
Figure 19. Thermal Regulation Loop Performance and Thermal Shutdown
DYNAMIC TIMER FUNCTION
The charge and pre-charge safety timers are programmed by the user to detect a fault condition if the charge
cycle duration exceeds the total time expected under normal conditions. The expected charge time is usually
calculated based on the fast charge current rate.
When the thermal loop is activated the charge current is reduced, and bq2406x activates the dynamic timer
control, an internal circuit that slows down the safety timer's clock frequnency. The dynamic timer control circuit
effectively extends the safety time duration for either the precharge or fast charge timer modes. This minimizes
the chance of a safety timer fault due to thermal regulation.
The bq2406x dynamic timer control (DTC) monitors the voltage at pin ISET during pre-charge and fast charge,
and if in thermal regulation slows the clock frequency proportionately to the change in charge current. The time
duration is based on a 224 ripple counter, so slowing the clock frequency is a real time correction. The DTC
circuit changes the safety timers clock period based on the V(SET)/V(ISET) ratio (fast charge) or V(PRECHG)/V(SET)
ratio (pre-charge). Typical safety timer multiplier values relative to the V(SET)/V(ISET) ratio is shown in Figure 20
and Figure 21.
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CHARGE TIMER INTERNAL CLOCK
PERIOD MULTIPLICATION FACTOR
5
4
3
2
1
0
0
1
5
4
3
2
V(SET)/V(ISET) - V
Figure 20. Safety Timer Linearity
Internal Clock Period Multiplication Factor
45
RTMR = 70 kW
T(CHG) - Safety Timer - Hours
40
35
30
RTMR = 50 kW
25
20
RTMR = 30 kW
15
10
5
0
0
1
2
3
VSET/VISET - V
4
5
Figure 21. bq2406x Safety Timer Linearity for RTMR Values
20
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160
Core Oscillator Frequency - kHz
140
120
100
80
60
40
20
0
20
30
40
60
50
ITMR Current - mA
70
80
90
Figure 22. bq2406x Oscillator Linearity vs ITMR
RTMR 30 KΩ – 100 KΩ
CHARGE TERMINATION DETECTION AND RECHARGE
The charging current is monitored the during the voltage regulation phase. Charge termination is indicated at the
STATx pins (STAT1 = Hi-Z; STAT2 = Low ) once the charge current falls below the termination current threshold
I(TERM). A deglitch period TDGL(TERM) is added to avoid false termination indication during transient events.
Charge termination is not detected if the charge current falls below the termination threshold as a result of the
thermal loop activation. Termination is also not detected when charger enters the suspend mode, due to
detection of invalid pack temperature or internal thermal shutdown.
Table 6 describes the termination latch functionality.
Table 6. Termination Latch Functionality
TERMINATION DETECTED LATCHED WHEN
TERMINATION LATCH RESET AT
CE rising edge or OVP detected
I(OUT) < I(TERM) AND t > TDGL(TERM) AND V(OUT) > V(RCH)
New charging cycle started; see state diagram
Termination disabled
The termination function is DISABLED:
1. In bq24060/61/64 the termination is disabled when the TMR pin is left open (floating).
2. In bq24063 leaving TMR pin open (floating) does NOT disable the termination. The only way to disable
termination in the bq24063 is to set TE = HIGH.
BATTERY ABSENT DETECTION – VOLTAGE MODE ALGORITHM
The bq2406x provides a battery absent detection scheme to reliably detect insertion and/or removal of battery
packs. The detection circuit applies an internal current to the battery terminal, and detects battery presence
based on the terminal voltage behavior. Figure 23 has a typical waveform of the output voltage when the battery
absent detection is enabled and no battery is connected:
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5
VO - Output Voltage - V
4.50
4
3.50
3
2.50
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
t - Time - s
Figure 23. Battery-Absent Detection Waveforms
The battery absent detection function is disabled if the voltage at the BAT pin is held above the battery recharge
threshold, V(RCH), after termination detection. When the voltage at the BAT pin falls to the recharge threshold,
either by connection of a load to the battery or due to battery removal, the bq2406x begins a battery absent
detection test. This test involves enabling a detection current, IDET(DOWN), for a period of T(DETECT) and checking
to see if the battery voltage is below the pre-charge threshold, V(LOWV). Following this, the precharge current,
IDET(UP) is applied for a period of T(DETECT) and the battery voltage checked again to be above the recharge
threshold.
Passing both of the discharge and charging tests (battery terminal voltage being below the pre-charge and
above the recharge thresholds on the battery detection test) indicates a battery absent fault at the STAT1 and
STAT2 pins. Failure of either test starts a new charge cycle. For the absent battery condition the voltage on the
BAT pin rises and falls between the V(LOWV) and VO(REG) thresholds indefinitely. See the operation flowchart for
more details on this algorithm. If it is desired to power a system load without a battery, it is recommended to
float the TMR pin which puts the charger in LDD mode (disables termination).
The battery absent detection function is disabled when the termination is disabled.
The bq2406x provides a small battery leakage current, IBAT(DONE) (1 µA typical), after termination to pull down
the BAT pin voltage in the event of battery removal. If the leakage on the OUT pin is higher than this pulldown
current, then the voltage at the pin remains above termination and a battery-absent state will not be detected.
This problem is fixed with the addition of a pulldown resistor of 2 MΩ to 4 MΩ from the OUT pin to VSS. A
resistor too large (< 2 MΩ) can cause the OUT pin voltage to drop below the V(LOWV) threshold before the
recharge deglitch (typical 25 ms) expires, causing a fault condition. In this case the bq2406x provides a fault
current (typical 750 µA) to pull the pin above the termination threshold.
CHARGE SAFETY TIMER
As a safety mechanism the bq2406x has a user-programmable timer that monitors the total fast charge time.
This timer (charge safety timer) is started at the beginning of the fast charge period. The safety charge timeout
value is set by the value of an external resistor connected to the TMR pin (RTMR); if pin TMR is left open
(floating) the charge safety timer is disabled.
The charge safety timer time-out value is calculated as follows:
T(CHG) = [K(CHG)× R(TMR)]
The safety timer operation modes are shown in Table 7
22
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Table 7. Charge Safety Timer Operational Modes
bq2460X
V(OUT) > V(LOWV)
CHARGE SAFETY TIMER MODE
STANDBY
X
RESET
CHARGING
No
RESET
SUSPEND
No
RESET
SUSPEND
Yes
SUSPEND
CHARGING, TMR PIN NOT OPEN
Yes
COUNTING
X
RESET
CHARGING, TMR PIN OPEN
In SUSPEND mode the charge safety timer is put on hold (i.e., charge safety timer is not reset), normal
operation resumes when the TS fault is removed and the timer returns to the normal operating mode
(COUNTING). If charge termination is not reached within the timer period a fault condition is detected. Under
those circumstances the LED status is updated to indicate a fault condition and the charger is turned off.
When the charge safety timer fault latch is set and the charger is turned off a small current IFAULT is applied to
the OUT pin, as long as input power (IN) is detected AND V(OUT) < V(RCHG), as part of a timer fault recovery
protocol. This current allows the output voltage to rise above the recharge threshold V(RCHG) if the pack is
removed, and assures that the charge safety timer fault latch is reset if the pack is removed and re-inserted.
Table 8 further details the charge safety timer fault latch operation.
Table 8. Charge Safety Timer Latch Functionality
CHARGE SAFETY TIMER FAULT ENTERED
CHARGE SAFETY TIMER FAULT LATCH RESET AT
CE rising edge, or OVP detected
V(OUT) > V(LOW V)
Input power removed (not detected)
New charging cycle started; see state diagram
SHORT CIRCUIT PROTECTION
The internal comparators monitor the battery voltage and detect when a short circuit is applied to the battery
terminal. If the voltage at the BAT pin is less than the internal threshold V(scind) (1.8 V typical), the STAT pins
indicate a fault condition (STAT1 = STAT2 = Hi-Z). When the voltage at the BAT pin falls below a second
internal threshold V(sc) (1.4 V typical), the charger power stage is turned off. A recovery current, I(short) (22 mA
typical), is applied to the BAT pin, enabling detection of the short circuit removal. The battery output current
versus battery voltage is shown in the graph, Figure 24
1200
RISET at 840 W
Battery Current - mA
1000
800
600
400
200
0
4
3.5
3
2.5
2
1.5
1
0.5
0
Battery Voltage - V
Figure 24. bq2406x Short Circuit Behavior
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See the application section for additional details on start-up operation with V(BAT) < V(SC).
STARTUP WITH DEEPLY DEPLETED BATTERY CONNECTED
The bq2406x charger furnishes the programmed charge current if a battery is detected. If no battery is
connected the bq2406x operates as follows:
• The output current is limited to 22 mA (typical), if the voltage at BAT pin is below the short circuit detection
threshold V(SC), 1.8 V typical.
• The output current is regulated to the programmed pre-charge current if V(SC) < V(BAT) < V(LOWV).
• The output current is regulated to the programmed fast charge current If V(BAT) > V(LOWV) AND voltage
regulation is not reached.
The output voltage collapses if no battery is present and the end equipment requires a bias current larger that
the available charge current.
24
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APPLICATION INFORMATION
SELECTING INPUT AND OUTPUT CAPACITOR
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 1-µF
ceramic capacitor, placed in close proximity to the IN pin and GND pad, works fine. In some applications,
depending on the power supply characteristics and cable length, it may be necessary to increase the input filter
capacitor to avoid exceeding the IN pin maximum voltage rating during adapter hot plug events.
The bq2406x only requires a small output capacitor for loop stability. A 0.47 µF ceramic capacitor placed
between the BAT and ISET pad is typically sufficient.
bq2406x CHARGER DESIGN EXAMPLE
Requirements
• Supply voltage = 5 V
• Safety timer duration of 5 hours for fast charge
• Fast charge current of approximately 750 mA
• Battery temp sense is not used
Calculations
Program the charge current for 750 mA:
RISET = [V(SET)× K(SET) / I(OUT)]
from electrical characteristics table. . . V(SET) = 2.5 V
from electrical characteristics table. . . K(SET) = 335
RISET = [2.5 V × 335 / 0.75 A] = 1.12 kΩ
Selecting the closest standard value, use a 1.13 kΩ resistor connected between ISET (pin 6) and ground.
Program 5-hour safety timer timeout:
R(TMR) = [T(CHG) / K(CHG)]
from the electrical characteristics table. . . K(CHG) = 0.1 hr / kΩ
K(TMR) = [5 hrs / (0.1 hr / kΩ)] = 50 kΩ
Selecting the closest standard value, use a 49.9 kΩ resistor connected between TMR (pin 2) and ground.
Disable the temp sense function:
A constant voltage between VTS1 and VTS2 on the TS input disables the temp sense function.
from electrical characteristics table. . . V(TS1) = 30% × VIN
from electrical characteristics table. . . V(TS2) = 61% × VIN
A constant voltage of 50% × Vin disables the temp sense function, so a divide-by-2 resistor divider
connected between Vin and ground can be used. Two 1-mΩ resistors keeps the power dissipated in this
divider to a minimum.
For a 0–45°C range with a Semitee 103AT thermistor, the thermistor values are 4912 at 450°C and 2728k at
0°C. RT1 (top resisotr) and RT2 (bottom resistor) are calculated as follows:
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APPLICATION INFORMATION (continued)
R T2 +
R T1 +
2.5 R TCRTH
RTC * 3.5 RTH
7 R THRT2
3 ƪRTH ) RT2ƫ
+
+
2.5 (27.28k) (4.912k)
+ 33.2k;
27.28k * 3.5(4.912k)
7 (4.921k) (33.2k)
+ 10k
3 [4.921k ) 33.2k]
(6)
PIN
COMPONENTS
IN
In most applications, the minimum input capacitance needed is a 0.1 µF ceramic decoupling
capacitor near the input pin connected to ground (preferably to a grond plane through vias).
The recommended amount of input capacitance is 1 µF or at least as much as on the
output pin. This added capacitance helps with hot plug transients, input inductance and
initial charge transients.
OUT
There is no minimum value for capacitance for this output, but it is recommended to connect
a 1 µF ceramic capacitor between OUT and ground. This capacitance helps with
termination, and cycling frequency between charge done and refresh charge when no
battery is present. It also helps cancel out any battery lead inductance for long leaded
battery packs. It is recommended to put as much ceramic capacitance on the input as the
output so as not to cause a drop out of the input when charging is initiated.
ISET/BAT
For stability reasons, it may be necessary to put a 0.47-µF capacitor between the ISET and
BAT pin..
STAT1/2 and PG Optional (LED STATUS – See below, Processor Monitored; or no status)
STAT1
Connect the cathode of a red LED to the open-collector STAT1 output, and connect the
anode of the red LED to the input supply through a 1.5 kΩ resistor that limits the current.
STAT2
Connect the cathode of a green LED to the open-collector STAT2 output, and connect the
anode of the green LED to the input supply through a 1.5 kΩ resistor that limits the current.
PG
Connect the cathode of an LED to the open-collector PG output, and connect the anode of
the LED to the input supply through a 1.5 kΩ resistor to limit the current.
THERMAL CONSIDERATIONS
The bq2406x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application
Note (SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA ) measured (or
modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical
expression for θJA is:
T * TA
q(JA) + J
P
(7)
Where:
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
26
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APPLICATION INFORMATION (continued)
•
Whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT)
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See the charging profile, Figure 13 .
If the board thermal design is not adequate the programmed fast charge rate current may not be achieved under
maximum input voltage and minimum battery voltage, as the thermal loop can be active effectively reducing the
charge current to avoid excessive IC junction temperature.
USING ADAPTERS WITH LARGE OUTPUT VOLTAGE RIPPLE
Some low cost adapters implement a half rectifier topology, which causes the adapter output voltage to fall
below the battery voltage during part of the cycle. To enable operation with low cost adapters under those
conditions the bq2406x family keeps the charger on for at least 30 msec (typical) after the input power puts the
part in sleep mode. This feature enables use of external low cost adapters using 50 Hz networks.
The backgate control circuit prevents any reverse current flowing from the battery to the adapter terminal during
the charger off delay time.
Note that the PG pin is not deglitched, and it indicates input power loss immediately after the input voltage falls
below the output voltage. If the input source frequently drops below the output voltage and recovers, a small
capacitor can be used from PG to VSS to prevent /PG flashing events.
PCB LAYOUT CONSIDERATIONS
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2406x, with short
trace runs to both IN, OUT and GND (thermal pad).
• All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and
the power ground path.
• The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces.
• The bq2406x family are packaged in a thermally enhanced MLP package. The package includes a thermal
pad to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal
pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground
connection. Full PCB design guidelines for this package are provided in the application note entitled:
QFN/SON PCB Attachment Application Note (SLUA271).
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24060DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24060DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24060DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24060DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24061DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24061DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24061DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24061DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24064DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24064DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24064DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24064DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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