LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 LM10504 Triple Buck + LDO Power Management Unit Check for Samples: LM10504 FEATURES DESCRIPTION • The LM10504 is an advanced PMU containing three configurable, high-efficiency buck regulators for supplying variable voltages. The device is ideal for supporting ASIC and SOC designs for Solid-State and Flash drives. 1 2 • • • • • • • Three Highly Efficient Programmable Buck Regulators – Integrated FETs with Low RDSON – Bucks Operate with Their Phases Shifted to Reduce the Input Current Ripple and Capacitor Size – Programmable Output Voltage via the SPI Interface – Overvoltage and Undervoltage Lockout – Automatic Internal Soft Start with Power-On Reset – Current Overload and Thermal Shutdown Protection – PFM Mode for Low-Load, High-Efficiency Operation Power-Down Data Protection Enhances Data Integrity – Bypass Mode Available on Bucks 1 and 2 Deep Sleep Mode to Save Power During Idle Times – DEVSLP Function Programmable Low-Dropout LDO 1.2V to 3.1V, up to 250 mA SPI-Programmable Interrupt Comparator (2.0V to 4.0V) Alternate Buck VOUTS Selectable via VSELECT Logic Pins Customizable Startup Sequencing for Varied Controllers RESET Pin The LM10504 operates cooperatively with ASIC to optimize the supply voltage for low-power conditions and Power Saving modes via the SPI interface. It also supports a 250 mA LDO and a programmable Interrupt Comparator. KEY SPECIFICATIONS • • • • • Programmable Buck Regulators: – Buck 1: 1.1V to 3.6V; 1.6A – Buck 2: 1.1V to 3.6V; 1A – Buck 3: 0.7V to 1.335V; 1A ±3% feedback voltage accuracy Up to 95% efficient buck regulators 2MHz switching frequency for smaller inductor size 2.8 x 2.8 mm, 0.4 mm pitch 34-bump DSBGA package APPLICATIONS • Solid-State Drives 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Typical Application Diagram Reset DevSLP LM10504 CS IO input supply SPI VIN_IO DI System DO Control CLK VIN C8 2.2 F Power Supply 3.3/5.0V CONTROL LOGIC and REGISTERS C9 2.2 F VIN_B1 C5 4.7 F VIN_B2 C6 4.7 F Vcomp COMP Interrupt LDO LDO C4 4.7 F L1 2.2 H C1 10 F FB_B1 L2 SW_B2 BUCK2 Host 1 Flash Vcc 3.0V/1.6A 3V SW_B1 BUCK1 Host Controller Vhost 3.0V/250 mA 3V 3V 2.2 H FB_B2 L3 1.2V SW_B3 VIN_B3 Vselect3 Vselect2 GND GND BUCK3 GND C7 4.7 F Host 2 Domain Vccq 3.0V/1A C2 Low = 1.8V 10 F 2.2 H Host 3 Domain Vcore 1.2V/1A C3 Low = 1.0V 10 F FB_B3 Voltage Monitored @ Startup Overview The LM10504 contains three buck converters and one LDO. Table 1 below lists the output characteristics of the power regulators. SUPPLY SPECIFICATION Table 1. Output Voltage Configurations for LM10504 (1) 2 Regulator VOUT if Vselect=Hi gh (B2, B3) VOUT if Vselect=L ow (B2, B3) VOUT if DEVSLP=High (DevSLP Mode) VOUT Maximum Output Current Typical Application Comments Buck 1 (1) 3.0V 3.0V off 1.1V to 3.6V; 50 mV steps 1.6A VCC Flash Buck 2 (1) 3.0V 1.8V off 1.1V to 3.6V; 50 mV steps 1A VCCQ Interface Buck 3 (1) 1.2V 1.0V Vnomimal −7% 0.7V to 1.335V; 5mV steps 1A VCORE Core LDO 3.0V 3.0V 3.0V 3.0V 250 mA VHOST controller Reference for Host Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Connection Diagram and Package Marking TOP VIEW (looking through part) 7 GND_B1 GND_B1 6 SW_B1 5 VCOMP GND RESET GND_B3 SW_B1 SW_B3 SW_B3 VIN_B1 VIN_B1 FB_B3 VIN_B3 4 FB_B1 FB_B1 Vselect3 Vselect2 3 VIN GND FB_B2 VIN_B2 2 LDO GND SW_B2 SW_B2 1 Interrupt VIN_IO SPI_ CLK SPI_DI SPI_DO SPI_CS GND_B2 A B C D E DEVSLP F G Table 2. PIN DESCRIPTIONS Pin # (1) (2) Pin Name I/O (1) Type (2) Functional Description A/B5 VIN_B1 I P Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if Buck 1 is not used, tie to ground to reduce leakage. A/B6 SW_B1 I/O P Buck Switcher Regulator 1 - Power Switching node, connect to inductor. A/B4 FB_B1 I/O A Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power. A/B7 GND_B1 G P Buck Switcher Regulator 1 - Power ground for Buck Regulator. G3 VIN_B2 I P Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET, if Buck 2 is not used, tie to ground to reduce leakage. F/G2 SW_B2 I/O P Buck Switcher Regulator 2 - Power Switching node, connect to inductor. F3 FB_B2 I A Buck Switcher Regulator 2 - Voltage output feedback. G1 GND_B2 G P Buck Switcher Regulator 2 - Power ground for Buck Regulator. G5 VIN_B3 I P Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET. F/G6 SW_B3 I/O P Buck Switcher Regulator 3 - Power Switching node, connect to inductor. F5 FB_B3 I A Buck Switcher Regulator 3 - Voltage output feedback. G7 GND_B3 G P Buck Switcher Regulator 3 - Power ground for Buck Regulator A3 VIN I P Power supply Input Voltage — must be present for device to work; decouple closely to D7. A2 LDO O P LDO regulator output voltage G4 Vselect_B2 I D Digital Input Startup Control Signal to change predefined output Voltage of Buck 2, internally pulled down as a default. I: Input Pin, O: Output Pin A: Analog Pin, I: Input Pin, D: Digital Pin, G: Ground, P: Power Connection Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 3 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Table 2. PIN DESCRIPTIONS (continued) Pin # Pin Name I/O (1) Type (2) Functional Description F4 Vselect_B3 I D Digital Input Startup Control Signal to change predefined output Voltage of Buck 3, internally pulled up as a default. E7 DevSLP I D Digital Input Control Signal for entering Device Sleep Mode. This is an active High pin with an internal pulldown resistor. Lowers core ASIC voltage and turns off the FLASH and I/O bucks. F7 RESET I D Digital Input Control Signal to abort SPI transactions; resets the PMIC to default voltages. This is an active Low pin with an internal pullup. C7 VCOMP I A Analog Input for Comparator A1 Interrupt O D Digital Output of Comparator to signal interrupt condition F1 SPI_CS I D SPI Interface - chip select D1 SPI_DI I D SPI Interface - serial data input E1 SPI_DO O D SPI Interface - serial data output C1 SPI_CLK I D SPI Interface - serial clock input B1 VIN_IO I A Supply Voltage for Digital Interface B2 GND G G Ground. Connect to system Ground. B3 GND G G Ground. Connect to system Ground. D7 GND G G Connect to system Ground; decouple closely to A3. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN, VCOMP −0.3V to +6.0V VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, Vselect_B2,Vselect_B3, RESET, SW_1, SW_2, SW_3, FB_1, FB_2, FB_3, LDO, Interrupt, DevSLP −0.3V to +6.0V Junction Temperature (TJ-MAX) 150°C −65°C to 150°C Storage Temperature ESD Rating (1) (2) Human Body Model (HBM) 2.0kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Operating Ratings (1) (2) (3) VIN_B1, VIN_B2_VIN_B3, VIN 3.0V to 5.5V VIN_IO 1.72V to 3.63V but < VIN All pins other than VIN_IO 0V to VIN Junction Temperature (TJ) −30°C to 125°C Ambient Temperature (TA) −30°C to 85°C Junction-to-Ambient Thermal Resistance (θJA) 44.5°C/W Maximum Continuous Power Dissipation (PD-MAX) (1) (2) (3) 4 0.9W Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = +140°C and disengages at TJ = +120°C (typ.). Thermal shutdown is ensured by design. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 General Electrical Characteristics (1) (2) Unless otherwise noted, VIN = 5.0V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol IQ(DEVSLP) Parameter Conditions Quiescent supply current Min DevSLP = HIGH, no load Typ Max Units 100 200 µA UNDER/OVERVOLTAGE LOCK OUT VUVLO_RISING 2.75 2.9 3.05 VUVLO_FALLING 2.45 2.6 2.75 VOVLO_RISING 5.64 VOVLO_FALLING 5.54 V DIGITAL INTERFACE VIL Logic input low VIH Logic input high VIL Logic input low VIH Logic input high VOL Logic output low VOH Logic output high IIL Input current, pin driven low IIH tRESET tDEVSLP (2) (3) Vselect_B2, Vselect_B3 SPI_DO Input current, pin driven high fSPI_MAX (1) SPI_CS, SPI_DI, SPI_CLK, RESET, DevSLP 0.3*VIN_IO 0.7*VIN_IO 0.3*VIN 0.2*VIN_IO 0.8*VIN_IO SPI_CS, SPI_DI, SPI_CLK, Vselect_B2, DevSLP −2 Vselect_B3, RESET −5 µA SPI_CS, SPI_DI, SPI_CLK, Vselect_B3, RESET 2 Vselect_B2, DevSLP 5 SPI max frequency Minimum pulse width V 0.7*VIN µA 10 MHz 2 (3) µsec 2 All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. Specification ensured by design. Not tested during production. Buck 1 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VIN = 5.0V where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol Parameter Conditions IQ VIN DC bias current No Load, PFM Mode IOUT_MAX IPEAK η (1) (2) (3) (4) (5) (6) Continuous maximum load current Min (4) (5) (6) Buck 1 enabled, switching in PWM 1.6 Peak switching current limit Buck 1 enabled, switching in PWM 1.9 Peak efficiency (4) IOUT = 0.3A Typ Max Units 15 50 µA A 2.1 2.6 90 A % All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 5 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Buck 1 Electrical Characteristics(1)(2)(3) (continued) Unless otherwise noted, VIN = 5.0V where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol Parameter FSW Switching frequency CIN Conditions Input capacitor COUT L Max Units 2 2.3 MHz 4.7 Output filter capacitor (4) Output capacitor ESR (4) DC line regulation 10 0mA ≤ IOUT ≤ IOUT-MAX (4) IFB Feedback pin input bias current RDS-ON-HS High side switch on resistance RDS-ON-LS Low side switch on resistance 10 100 20 (4) (4) DC load regulation RDS-ON-BYPASS Typ (4) Output filter inductance ΔVOUT Min 1.75 µF mΩ 2.2 µH 3.3V ≤ VIN ≤ 5.0V, IOUT = IOUT-MAX 0.5 %/V 100 mA ≤ IOUT ≤ IOUT-MAX 0.3 VFB = 3.0V 2.1 %/A 5 135 VIN = 2.6V mΩ 215 85 µA 190 mΩ Used in parallel with the high side FET while in Bypass mode. Resistance (DCR) of inductor = 100 mΩ Bypass FET on resistance VIN = 3.3V 85 VIN = 2.6V 120 Startup from shutdown, VOUT = 0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.1 mΩ STARTUP TSTART Internal soft-start (turn on time) (4) ms Buck 2 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VIN = 5.0V where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol IQ Parameter Conditions VIN DC bias current IOUT_MAX No Load, PFM Mode Continuous maximum load current (4) (5) (6) IPEAK Peak switching current limit η Peak efficiency FSW Switching frequency CIN Input capacitor COUT L (1) (2) (3) (4) (5) (6) 6 (4) Buck 2 enabled, switching in PWM 1.0 Buck 2 enabled, switching in PWM 1.35 IOUT = 0.3A 1.75 (4) Output capacitor ESR (4) DC load regulation Max Units 15 50 µA A 1.56 1.8 2 0mA ≤ IOUT ≤ IOUT-MAX (4) (4) (4) 10 10 A % 2.3 4.7 Output filter capacitor DC line regulation Typ 90 (4) Output filter inductance ΔVOUT Min 100 20 MHz µF mΩ 2.2 µH 3.3V ≤ VIN ≤ 5.0V, IOUT = IOUT-MAX 0.5 %/V 100 mA ≤ IOUT ≤ IOUT-MAX 0.3 %/A All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Buck 2 Electrical Characteristics(1)(2)(3) (continued) Unless otherwise noted, VIN = 5.0V where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol Parameter Conditions IFB Feedback pin input bias current RDS-ON-HS High side switch on resistance RDS-ON-LS Low side switch on resistance Min VFB = 1.8V Typ Max Units 1.8 5 µA 135 VIN = 2.6V 260 85 mΩ 190 STARTUP TSTART Internal soft-start (turn on time) Startup from shutdown, VOUT = 0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value (4) Buck 3 Electrical Characteristics 0.1 ms (1) (2) (3) Unless otherwise noted, VIN = 5.0V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol IQ Parameter Conditions VIN DC bias current IOUT_MAX Continuous maximum load current (4) (5) (6) IPEAK Peak switching current limit η Peak efficiency FSW Switching frequency CIN Input capacitor COUT L (4) IFB Buck 3 enabled, switching in PWM 1.0 Buck 3 enabled, switching in PWM 1.35 IOUT = 0.3A 1.75 (4) Output capacitor ESR (4) DC load regulation Max Units 15 50 µA A 1.56 1.8 2 0mA ≤ IOUT ≤ IOUT-MAX (4) (4) (4) Feedback pin input bias current RDS-ON-HS High side switch on resistance RDS-ON-LS Low side switch on resistance 10 10 A % 2.3 4.7 Output filter capacitor DC line regulation Typ 90 (4) Output filter inductance ΔVOUT Min No Load, PFM Mode 100 20 MHz µF mΩ 2.2 µH 3.3V ≤ VIN ≤ 5V, IOUT = IOUT-MAX 0.5 %/V 100 mA ≤ IOUT ≤ IOUT-MAX 0.3 %/A VFB = 1.2V 0.9 5 µA 135 VIN = 2.6V 260 85 mΩ 190 STARTUP TSTART (1) (2) (3) (4) (5) (6) Internal soft-start (turn on time) (4) Startup from shutdown, VOUT = 0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.1 ms All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 7 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 LDO Electrical Characteristics www.ti.com (1) (2) Unless otherwise noted, VIN = 5.0V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol Parameter Conditions Min Typ −3 VOUT Output Voltage Accuracy IOUT Maximum Output Current ISC Short-Circuit Current Limit VOUT = 0V 0.5 VDO Dropout Voltage IOUT = 250 mA 160 Line Regulation 3.3V ≤ VIN ≤ 5.0V, IOUT = 1mA Load Regulation 1mA ≤ IOUT ≤ 250 mA, VIN = 3.3V, 5.0V ΔVOUT IOUT = 1mA (3) PSRR Power Supply Rejection Ratio TSTART Startup Time from Shutdown (3) TTRANSI Startup Transient Overshoot (3) (3) ENT 8 % mA VIN = 3.3V 35 F = 10 kHz, COUT = 4.7 µF, IOUT VIN = 5.0V = 20 mA VIN = 3.3V 65 VIN = 5.0V 45 VIN = 3.3V 60 COUT = 4.7 µF, IOUT = 250 mA mV 5 10 COUT = 4.7 µF, IOUT = 250 mA A 220 5 VIN = 5.0V 10 Hz ≤ f ≤ 100 kHz Output Noise Voltage (2) (3) Units +3 250 eN (1) Max µVRMS dB 40 µs 30 mV All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. Specification ensured by design. Not tested during production. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Comparators Electrical Characteristics (1) (2) Unless otherwise noted, VIN = 5.0V. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire operating junction temperature range of −30°C ≤ TA = TJ ≤ +85°C. Symbol Parameter Typ Max VCOMP = 0.0V Conditions Min 0.1 2 VCOMP = 5.0V 0.1 2 IVCOMP VCOMP pin bias current VCOMP_RIS Comparator rising edge trigger level 2.79 Comparator falling edge trigger level 2.74 E VCOMP_FAL Units µA V L Hysteresis InterruptVO 30 60 Output voltage high H InterruptVO 0.2*VI N_IO Output voltage low L tCOMP (1) (2) 80 0.8*VI N_IO Transition time of Interrupt output 6 15 mV V µs All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 9 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics unless otherwise noted, TA = 25°C Efficiency of Buck 2: VIN=5.0V 100 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) Efficiency of Buck 1: VIN=5.0V, VOUT=3.0V 100 70 60 50 70 60 50 40 40 30 30 20 VOUT = 3.0V VOUT = 1.8V 20 1 10 100 IOUT(mA) 1k 10k 1 10 Figure 1. 100 IOUT(mA) 1k 10k Figure 2. Efficiency of Buck 3: VIN=5.0V, VOUT=1.0V 100 Startup of Buck 1: VOUT=3.0V 200 µs/ 1 1.00V/ 90 VIN = 3.3V 1A load EFFICIENCY (%) 80 70 60 50 40 1 BUCK1 30 20 1 10 100 IOUT(mA) Figure 3. 1k 10k Figure 4. Startup of Buck 1: VOUT=3.0V 1 1.00V/ 200 µs/ LDO VOUT vs. IOUT 3.008 VIN = 5.0V VIN = 3.3V 3.006 VIN = 5V 1A load VOUT(V) 3.004 1 3.002 3.000 2.998 2.996 BUCK1 2.994 2.992 0 Figure 5. 10 Submit Documentation Feedback 40 80 120 160 200 240 280 IOUT(mA) Figure 6. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) LDO VIN vs. VOUT 3.003 Buck 1 VOUT vs. IOUT VIN=5.0V, VOUT=3.0V 3.20 IOUT = 1mA IOUT= 250mA 3.002 3.16 3.12 3.000 3.08 VOUT(V) 3.001 VOUT(V) 2.999 2.998 2.997 3.04 3.00 2.96 2.996 2.92 2.995 2.88 2.994 2.84 2.993 3.5 4.0 4.5 5.0 VIN(V) 5.5 2.80 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 IOUT(A) 6.0 Figure 7. Figure 8. Buck 2 VOUT vs. IOUT VIN=5.0V, VOUT=1.8V Buck 2 VOUT vs. IOUT VIN=5.0V, VOUT=3.0V 1.85 3.10 1.84 3.08 1.83 3.06 1.82 3.04 VOUT(V) VOUT(V) 3.0 1.81 1.80 1.79 3.02 3.00 2.98 1.78 2.96 1.77 2.94 1.76 2.92 1.75 2.90 0 200 400 600 IOUT(mA) 800 1000 0 200 400 600 800 1000 1200 IOUT(mA) Figure 9. Figure 10. Buck 3 VOUT vs. IOUT VIN=5.0V, VOUT=1.0V Buck 3 VOUT vs. IOUT VIN=5.0V, VOUT=1.2V 1.02 1.210 1.208 1.01 1.206 1.204 VOUT(V) VOUT(V) 1.00 1.202 0.99 1.200 1.198 0.98 1.196 1.194 0.97 1.192 0.96 1.190 0 200 400 600 800 1000 1200 IOUT(mA) Figure 11. 0 200 400 600 800 1000 1200 IOUT(mA) Figure 12. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 11 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Buck 2 VOUT vs. VIN VOUT=1.8V, IOUT=1A Buck 2 VOUT vs. VIN VOUT=3.0V, IOUT=1A 3.000 1.800 2.995 1.795 2.990 VOUT(V) VOUT(V) 1.805 1.790 2.985 1.785 2.980 1.780 2.975 1.775 2.970 3.0 3.5 4.0 VIN(V) 4.5 5.0 3.5 4.0 5.0 Figure 13. Figure 14. Buck 3 VOUT vs VIN VOUT=1.0V, IOUT=1A Buck 3 VOUT vs VIN VOUT=1.2V, IOUT=1A 1.215 1.010 1.210 1.005 1.205 VOUT(V) VOUT(V) 1.015 1.000 1.200 0.995 1.195 0.990 1.190 0.985 1.185 3.0 3.5 4.0 VIN(V) 4.5 5.0 3.0 3.5 Figure 15. 1 VIN 2 LDO 4.0 VIN(V) 4.5 5.0 Figure 16. LDO Startup Time from VIN Rise 1 1.00V/ 2 1.00V/ From LDO Startup to Buck 1 Startup 1 1.00V/ 2 1.00V/ 5.00 ms/ 1 LDO 2 BUCK1 Figure 17. 12 4.5 VIN(V) 1.00 ms/ Figure 18. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) From Buck 1 Startup to Buck 2 Startup 1 1.00V/ 2 1.00V/ From Buck 2 Startup to Buck 3 Startup 1.00 ms/ 1 1.00V/ 2 1.00V/ 1 BUCK1 1 BUCK2 2 BUCK2 2 BUCK3 Figure 19. 1.00 ms/ Figure 20. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 13 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com GENERAL DESCRIPTION LM10504 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and processors. It operates cooperatively and communicates with processors over an SPI interface with output Voltage programmability. SPI RESET GND GND GND LDO VIN LDO CONTROL LOGIC REGISTERS VIN_B2 EN DEVSLP SPI_CLK SPI_DO SPI_DI VIN_IO SPI_CS The device incorporates three high-efficiency synchronous buck regulators and one LDO that deliver four output voltages from a single power source. The device also includes a SPI-programmable Comparator Block that provides an interrupt output signal. SW_B2 BUCK2 GND_B2 FB_B2 EN VSELECT_B2 LM10504 VIN_B1 SEQUENCER TSD EN SW_B1 BUCK1 GND_B1 OVLO UVLO FB_B1 EN VIN_B3 VCOMP SW_B3 BUCK3 COMPARATOR GND_B3 FB_B3 INTERRUPT VSELECT_B3 Figure 21. Internal Block Diagram of the LM10504 PMIC SPI DATA INTERFACE The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the individual Bucks and of course read the status of Flag registers. By accessing the registers in the device through this interface, the user can get access and control the operation of the buck controllers and program the reference voltage of the comparator in the device. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 CS CLK DI 1 1 2 0 3 A4 Write Command DO 7 A3 A2 A1 A0 9 0 D7 16 D6 D5 D4 D3 D2 D1 D0 Write Data Register Address 0 Figure 22. SPI Interface Write • • Data In (DI) – 1 to 0 Write Command – A4to A0 Register address to be written – D7 to D0 Data to be written Data Out (DO) – All Os CS CLK DI 1 1 2 1 Read Command 3 A4 7 A3 A2 A1 A0 9 16 0 Register Address DO D7 D6 D5 D4 D3 D2 D1 D0 Read Data Figure 23. SPI Interface Read • • • Data In (DI) – 1 to 1 Read Command – A4to A0 Register address to be read Data Out (DO) – D7 to D0 Data Read Data In (DI) – Don't Care after A0 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 15 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Registers Configurable Via The SPI Interface Addr 0x00 0x07 0x08 Reg Name Buck 3 Voltage Buck 1 Voltage Buck 2 Voltage Bit R/W Default Description 7 — 6 R/W Buck 3 Voltage Code[6] Reset default: Vselect_B3=1 → 0x64 (1.2V) 5 R/W Buck 3 Voltage Code[5] Vselect_B3=0 → 0x3C (1.0V) 4 R/W 3 R/W 2 R/W Buck 3 Voltage Code[2] 1 R/W Buck 3 Voltage Code[1] 0 R/W Buck 3 Voltage Code[0] 7 — Reset default: 6 — 0x26 (3.0V) 5 R/W 4 R/W 3 R/W 2 R/W Buck 1 Voltage Code[2] 1 R/W Buck 1 Voltage Code[1] 0 R/W Buck 1 Voltage Code[0] 7 — 6 — 5 R/W Buck 2 Voltage Code[5] 4 R/W Buck 2 Voltage Code[4] 3 R/W 2 R/W Buck 2 Voltage Code[2] 1 R/W Buck 2 Voltage Code[1] 0 R/W Buck 2 Voltage Code[0] See Notes Buck 3 Voltage Code[4] Buck 3 Voltage Code[3] 0x09 See Notes Buck 1 Voltage Code[4] 16 Buck Control Range: 1.1V to 3.6V Buck 1 Voltage Code[3] Reset default: Vselect_B2=1 → 0x26 (3.0V) See Notes Buck 2 Voltage Code[3] Vselect_B2=0 → 0x0E (1.8V) Range: 1.1V to 3.6V Reset default: 6 Buck 3 Voltage Code[6] Vselect_B3=1 → 0x53 (1.115V) 5 Buck 3 Voltage Code[5] Vselect_B3=0 → 0x0E (0.93V) 4 Buck 3 Voltage Code[4] 3 R/W See Notes Buck 3 Voltage Code[3] 2 Buck 3 Voltage Code[2] 1 Buck 3 Voltage Code[1] 0 0x0A Range: 0.7V to 1.335V Buck 1 Voltage Code[5] 7 DevSLP Mode for Buck3 Notes Buck 3 Voltage Code[0] 7 R 6 — 1 BK3EN Reads Buck 3 enable status 5 — 4 R/W 0 BK1FPWM Buck 1 forced PWM mode when high 3 R/W 0 BK2FPWM Buck 2 forced PWM mode when high 2 R/W 0 BK3FPWM Buck 3 forced PWM mode when high 1 R/W 1 BK1EN Enables Buck 1 0-disabled, 1-enabled 0 R/W 1 BK2EN Enables Buck 2 0-disabled, 1-enabled Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com Addr 0x0B 0x0C 0x0D 0x0E SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Reg Name Comparator Control Interrupt Enable Interrupt Status MISC Control Bit R/W Default 7 R/W 0 Comp_hyst[0] Description Doubles Comparator hysteresis Notes 6 R/W 0 Comp_thres[5] Programmable range of 2.0V to 4.0V, step size = 31.75 mV 5 R/W 1 Comp_thres[4] 4 R/W 1 Comp_thres[3] 3 R/W 0 Comp_thres[2] Comp_hyst=1 → min 80 mV hysteresis 2 R/W 0 Comp_thres[1] Comp_hyst=0 → min 40 mV hysteresis 1 R/W 1 Comp_thres[0] 0 R/W 1 COMPEN 7 — 6 — 5 — 4 R/W 0 LDO OK 3 R/W 0 Buck 3 OK 2 R/W 0 Buck 2 OK 1 R/W 0 Buck 1 OK 0 R/W 1 Comparator Interrupt comp event 7 — 6 — 5 — 4 R LDO OK LDO is greater than 90% of target 3 R Buck 3 OK Buck 3 is greater than 90% of target 2 R Buck 2 OK Buck 2 is greater than 90% of target 1 R Buck 1 OK Buck 1 is greater than 90% of target 0 R Comparator Comparator output is high 7 — 6 — 5 — 4 — 3 — Comparator Threshold reset default: 0x19 Comparator enable 2 — 1 R/W 0 LDO Sleep Mode LDO goes into extra power save mode 0 R/W 0 Interrupt Polarity Interrupt_polarity=0→Active low Interrupt Interrupt_polarity=1→Active high Interrupt ADDR 0x07& 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping Voltage code Voltage Voltage code Voltage 0x00 1.10 0x20 2.70 0x01 1.15 0x21 2.75 0x02 1.20 0x22 2.80 0x03 1.25 0x23 2.85 0x04 1.30 0x24 2.90 0x05 1.35 0x25 2.95 0x06 1.40 0x26 3.00 0x07 1.45 0x27 3.05 0x08 1.50 0x28 3.10 0x09 1.55 0x29 3.15 0x0A 1.60 0x2A 3.20 0x0B 1.65 0x2B 3.25 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 17 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Voltage code Voltage Voltage code Voltage 0x0C 1.70 0x2C 3.30 0x0D 1.75 0x2D 3.35 0x0E 1.80 0x2E 3.40 0x0F 1.85 0x2F 3.45 0x10 1.90 0x30 3.50 0x11 1.95 0x31 3.55 0x12 2.00 0x32 3.60 0x13 2.05 0x33 3.60 0x14 2.10 0x34 3.60 0x15 2.15 0x35 3.60 0x16 2.20 0x36 3.60 0x17 2.25 0x37 3.60 0x18 2.30 0x38 3.60 0x19 2.35 0x39 3.60 0x1A 2.40 0x3A 3.60 0x1B 2.45 0x3B 3.60 0x1C 2.50 0x3C 3.60 0x1D 2.55 0x3D 3.60 0x1E 2.60 0x3E 3.60 0x1F 2.65 0x3F 3.60 ADDR 0x00 & 0x09: Buck 3 Voltage Code and VOUT Level Mapping 18 Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage 0x00 0.700 0x20 0.860 0x40 1.020 0x60 1.180 0x01 0.705 0x21 0.865 0x41 1.025 0x61 1.185 0x02 0.710 0x22 0.870 0x42 1.030 0x62 1.190 0x03 0.715 0x23 0.875 0x43 1.035 0x63 1.195 0x04 0.720 0x24 0.880 0x44 1.040 0x64 1.200 0x05 0.725 0x25 0.885 0x45 1.045 0x65 1.205 0x06 0.730 0x26 0.890 0x46 1.050 0x66 1.210 0x07 0.735 0x27 0.895 0x47 1.055 0x67 1.215 0x08 0.740 0x28 0.900 0x48 1.060 0x68 1.220 0x09 0.745 0x29 0.905 0x49 1.065 0x69 1.225 0x0A 0.750 0x2A 0.910 0x4A 1.070 0x6A 1.230 0x0B 0.755 0x2B 0.915 0x4B 1.075 0x6B 1.235 0x0C 0.760 0x2C 0.920 0x4C 1.080 0x6C 1.240 0x0D 0.765 0x2D 0.925 0x4D 1.085 0x6D 1.245 0x0E 0.770 0x2E 0.930 0x4E 1.090 0x6E 1.250 0x0F 0.775 0x2F 0.935 0x4F 1.095 0x6F 1.255 0x10 0.780 0x30 0.940 0x50 1.100 0x70 1.260 0x11 0.785 0x31 0.945 0x51 1.105 0x71 1.265 0x12 0.790 0x32 0.950 0x52 1.110 0x72 1.270 0x13 0.795 0x33 0.955 0x53 1.115 0x73 1.275 0x14 0.800 0x34 0.960 0x54 1.120 0x74 1.280 0x15 0.805 0x35 0.965 0x55 1.125 0x75 1.285 0x16 0.810 0x36 0.970 0x56 1.130 0x76 1.290 0x17 0.815 0x37 0.975 0x57 1.135 0x77 1.295 0x18 0.820 0x38 0.980 0x58 1.140 0x78 1.300 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage 0x19 0.825 0x39 0.985 0x59 1.145 0x79 1.305 0x1A 0.830 0x3A 0.990 0x5A 1.150 0x7A 1.310 0x1B 0.835 0x3B 0.995 0x5B 1.155 0x7B 1.315 0x1C 0.840 0x3C 1.000 0x5C 1.160 0x7C 1.320 0x1D 0.845 0x3D 1.005 0x5D 1.165 0x7D 1.325 0x1E 0.850 0x3E 1.010 0x5E 1.170 0x7E 1.330 0x1F 0.855 0x3F 1.015 0x5F 1.175 0x7F 1.335 ADDR 0x0B: Comparator Threshold Mapping Voltage code Voltage Voltage code Voltage 0x00 2.000 0x20 3.016 0x01 2.032 0x21 3.048 0x02 2.064 0x22 3.080 0x03 2.095 0x23 3.111 0x04 2.127 0x24 3.143 0x05 2.159 0x25 3.175 0x06 2.191 0x26 3.207 0x07 2.222 0x27 3.238 0x08 2.254 0x28 3.270 0x09 2.286 0x29 3.302 0x0A 2.318 0x2A 3.334 0x0B 2.349 0x2B 3.365 0x0C 2.381 0x2C 3.397 0x0D 2.413 0x2D 3.429 0x0E 2.445 0x2E 3.461 0x0F 2.476 0x2F 3.492 0x10 2.508 0x30 3.524 0x11 2.540 0x31 3.556 0x12 2.572 0x32 3.588 0x13 2.603 0x33 3.619 0x14 2.635 0x34 3.651 0x15 2.667 0x35 3.683 0x16 2.699 0x36 3.715 0x17 2.730 0x37 3.746 0x18 2.762 0x38 3.778 0x19 2.794 0x39 3.810 0x1A 2.826 0x3A 3.842 0x1B 2.857 0x3B 3.873 0x1C 2.889 0x3C 3.905 0x1D 2.921 0x3D 3.937 0x1E 2.953 0x3E 3.969 0x1F 2.984 0x3F 4.000 BUCK REGULATORS OPERATION A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground and a feedback path. The following figure shows the block diagram of each of the three buck regulators integrated in the device. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 19 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com CONTROL G CIN P D D SW N S L VOUT G FB S VIN PVIN U1 LM10504 COUT PGND GND Figure 24. Buck Functional Diagram During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN – VOUT)/L by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (–VOUT)/L. The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. Buck Regulators Description The LM10504 incorporates three high-efficiency synchronous switching buck regulators that deliver various voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage regulation, high efficiency and fast transient response time. The bucks feature voltage mode architecture with synchronous rectification. Each of the switching regulators is specially designed for high-efficiency operation throughout the load range. With a 2MHz typical switching frequency, the external L- C filter can be small and still provide very low output voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage and high output currents. All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch on. Additional features include soft-start, undervoltage lockout, bypass, and current and thermal overload protection. To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase. These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced PWM) or automatic mode (PWM/PFM). PWM Operation During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, a feed forward voltage inversely proportional to the input voltage is introduced. In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current. In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM (Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 100 mA (typ.) they operate in PWM mode. This increases the efficiency at lower output currents. The 30 mA (typ.) hysteresis is designed in for stable Mode transition. 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. In this case the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. PWM Mode at Moderate to Heavy Loads VOUT PFM Mode at Light Load Load current increases, draws Vout towards Low 2 PFM Threshold High PFM Threshold ~1.016*VOUT Low1 PFM Threshold ~1.008*VOUT PFET on until LPFM limit reached NFET on drains inductor current until I inductor=0 High PFM Voltage Threshold reached, go into idle mode Low PFM Threshold, turn on PFET Load current increases Low 2 PFM Threshold, switch back to PWM mode Low2 PFM Threshold VOUT Time Figure 25. PFM vs PWM Operation PFM Operation At very light loads, Buck 1, 2 and Buck 3 enter PFM mode and operate with reduced switching frequency and supply current to maintain high efficiency. Buck 1, 2 and 3 will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: 1. The inductor current becomes discontinuous, or 2. The peak PMOS switch current drops below the IMODE level. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 25), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘idle’ mode is less than 100 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 21 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Soft Start Each of the buck converters has an internal soft-start circuit that limits the in-rush current during startup. This allows the converters to gradually reach the steady-state operating point, thus reducing startup stresses and surges. During startup, the switch current limit is increased in steps. For Buck 1, 2 and 3 the soft start is implemented by increasing the switch current limit in steps that are gradually set higher. The startup time depends on the output capacitor size, load current and output voltage. Typical startup time with the recommended output capacitor of 10 µF is 0.2 to 1ms. It is expected that in the final application the load current condition will be more likely in the lower load current range during the start up. Current Limiting A current limit feature protects the device and any external components during overload conditions. In PWM mode the current limiting is implemented by using an internal comparator that trips at current levels according to the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. Internal Synchronous Rectification While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. Bypass-FET Operation on Buck 1 and Buck 2 There is an additional bypass FET used on Buck 1. The FET is connected in parallel to High Side FET and inductor. Buck 2 has no extra bypass FET – it uses High Side FET (PFET) for bypass operation. If Buck 1 input voltage is greater than 3.5V (2.6V for Buck 2), the bypass function is disabled. The determination of whether or not the Buck regulators are in bypass mode or standard switching regulation is constantly monitored while the regulators are enabled. If at any time the input voltage goes above 3.5V (2.6V for Buck 2) while in bypass mode, the regulators will transition to normal operation. When the bypass mode is enabled, the output voltage of the buck that is in bypass mode is not regulated, but instead, the output voltage follows the input voltage minus the voltage drop seen across the FET and DCR of the inductor. The voltage drop is a direct result of the current flowing across those resistive elements. When Buck 1 transitions into bypass mode, there is an extra FET used in parallel along with the high side FET for transmission of the current to the load. This added FET will help reduce the resistance seen by the load and decrease the voltage drop. For Buck 2, the bypass function uses the same high side FET. 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Equivalent Circuit of Bypass Operation of Buck 1 High Side FET VIN_B1 DCR 100m Max. Ideal Inductor, no resistance VOUT Buck1 SW_B1 Model of Inductor Load Resistance FB_B1 Load Capacitance Bypass FET Equivalent Circuit of Bypass Operation of Buck 2 High Side FET VIN_B2 DCR 100m Max. Ideal Inductor, no resistance VOUT Buck2 SW_B2 Model of Inductor Load Resistance Load Capacitance Low Dropout Operation The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage: VIN_MIN=VOUT+ILOAD*(RDSON_PFET+RIND) Where • • • ILOAD = Load Current RDSON_PFET = Drain to source resistance of PFET (high side) RIND = Inductor resistance (1) Out of Regulation When any of the Buck outputs are taken out of regulation (below 85% of the output level) the device will start a shutdown sequence and all other outputs will switch off normally. The device will restart when the forced out-ofregulation condition is removed. Device Operating Modes STARTUP SEQUENCE The startup mode of the LM10504 will depend on the input voltage. Once VIN reaches the UVLO threshold, there is a 15 msec delay before the LM10504 determines how to set up the buck regulators. If VIN is below 3.6V, then Buck 1 and Buck 2 will be in bypass mode, see Bypass-FET Operation on Buck 1 and Buck 2 for functionality description. If the VIN voltage is greater than 3.6V the bucks will start up as the standard regulators. The 3 buck regulators are staggered during startup to avoid large inrush currents. There is a fixed delay of 2 msec between the startup of each regulator. The Startup Sequence will be: 1. 15 msec (±30%) delay after VIN above UVLO 2. LDO → 3.2V 3. 2 msec delay Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 23 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 4. 5. 6. 7. 8. www.ti.com Buck 1 → 3.0V 2 msec delay Buck 2 → 3.0V or if Vselect_B2 = Low → 1.8V 2 msec delay Buck 3 → 1.2V or if Vselect_B3 = Low → 1.0V 5.64V 5.54V 3.5V 3.5V 2.9V 2.6V ~2.25V VIN BG / BIAS 15 ms 15 ms UVLO 3.2V LDO 3.5V 3.5V 2ms 2ms 2ms Buck1 1.1V 2.6V 2ms 2ms Buck2 2ms 2ms 2ms 2ms 1.1V PSML Buck3 Comparator OVLO B1 en Bypass B2 en Bypass DevSLP UVLO STARTUP BYPASS OPERATION OVLO STARTUP DEVSLP UVLO BYPASS OPERATION Figure 26. Operating Modes POWER-ON DEFAULT AND DEVICE ENABLE The device is always enabled and the LDO is always on, unless outside of operating voltage range. There is no LM10504 Enable Pin. Once VIN reaches a minimum required input Voltage the power-up sequence will be started automatically and the startup sequence will be initiated. Once the device is started, the output voltage of the Bucks 1 and 2 can be individually disabled by accessing their corresponding BKEN register bits (BUCK CONTROL). RESET: PIN FUNCTION The RESET pin is internally pulled high. If the reset pin is pulled low, the device will perform a complete reset of all the registers to their default states. This means that all of the voltage settings on the regulators will go back to their default states. DevSLP FUNCTION The Device can be placed into Sleep (DevSLP) mode. There are two ways for doing that: 1. DevSLP pin 2. Programming via SPI 24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 Bucks 1 and 2 will be ramped down when the disable signal is given. Buck 1 starts ramping 2ms after Buck 2 has started ramping. Entering DevSLP Sequence will be: 1. Buck 3 → PSML (Programmable DevSLP Mode Level) 2. 2 msec delay 3. Buck 2 → Disabled 4. 2 msec delay 5. Buck 1 → Disabled DevSLP Pin When the DevSLP pin is asserted high, the LM10504 will enter Sleep Mode. While in Sleep Mode, Buck 1 and Buck 2 are disabled. Buck 3’s output voltage is transitioned to the PSML (Programmable Sleep Mode Level) as set by LM10504 register 0x09. The DevSLP pin is internally pulled down, and there is a 1 second delay during powerup before the state of the DevSLP pin is checked. NOTE If Buck 1 and Buck 2 are already disabled, and the DevSLP pin is asserted high, then Buck 3 will not go to PSML – for further instructions, see DevSLP Programming via SPI. Bucks 1 and 2 will be ramped down when the disable signal is given. Buck 1 starts ramping 2ms after Buck 2 has started ramping. Entering Sleep Sequence will be: 1. Buck 3 → PSML (Programmable Sleep Mode Level) 2. 2 msec delay 3. Buck 2 → Disabled 4. 2 msec delay 5. Buck 1 → Disabled An internal 22 kΩ pull down resistor (±30%) is attached to the FB pin of Buck 1 and Buck 2. Buck 1 and 2 outputs are pulled to ground level when they are disabled to discharge any residual charge present in the output circuitry. When Sleep transitions to a low, Buck 1 is again enabled followed by Buck 2. Buck 3 will go back to its previous state. When waking up from Sleep, the sequence will be: 1. Buck 1 → Previous state 2. 2 msec delay 3. Buck 2 and Buck 3 transition together → Previous state DevSLP Programming via SPI There is no bit which has the same function as DevSLP PIN. There is only one requirement programming LM10504 into DevSLP Mode via SPI. Setting LDO Sleep Mode bit high must be the last move when entering DevSLP Mode and programming the bit low when waking from DevSLP Mode must be the first move. Disabling or programming the Bucks to new level is the user’s decision based on power consumption and other requirements. The following section describes how to program the chip into Sleep Mode corresponding to DevSLP PIN function. To program the LM10504 to Sleep Mode via SPI, Buck 1 and Buck 2 must be disabled by host device (Register 0x0A bit 1 and 0). Buck 3 must be programmed to desired level using Register 0x00. After Buck 3 has finished ramping, LDO Sleep Mode bit must be set high (Register 0x0E bit 1). To wake LM10504 from Sleep Mode, LDO Sleep Mode bit must be set low (Register 0x0E bit 1). Buck 1 and 2 must be enabled. Buck 3 voltage must be programmed to previous output level. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 25 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com DevSLP Operational Constraints In Sleep mode the device is in a low power mode. All internal clocks are turned off to conserve power and BUCK 3 will only operate in PFM mode. While limited to PFM mode the loading on BUCK 3 should be kept below 80mA typ. to remain below the PFM/PWM threshold and avoid device shutdown. It is recommended that the device loading should be lowered accordingly prior to entering SLEEP mode via DEVSLP. Vselect_B2, Vselect_B3 FUNCTION The Vselect_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3, respectively. Vselect_B2 has an internal pulldown which defaults to a 1.8V output voltage selection for Buck 2. Alternatively, if Vselect_B2 is driven high, an output voltage of 3.0V is selected. Vselect_B3 has an internal pullup which defaults to a 1.2V output voltage selection for Buck 3. Alternatively, if Vselect_B3 is driven low, an output voltage of 1.0V is selected. The pullup resistor is connected to the main input voltage. Transitions of the pins will not affect the output voltage, the state is only checked during startup. UNDERVOLTAGE LOCKOUT (UVLO) The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device can not be ensured. The part will automatically disable Buck 3. To prevent unstable operation, the undervoltage lockout (UVLO) has a hysteresis window of about 300 mV. An UVLO will force the device into the reset state, all internal registers are reset. Once the supply voltage is above the UVLO hysteresis, the device will initiate a power-up sequence and then enter the active state. Buck 1 and Buck 2 will remain in bypass mode after VIN passes the UVLO until VIN reaches approximately 1.9V. When Buck 2 is set to 1.8V, the voltage will jump from 1.8V to VUVLO_FALLING, and then follow VIN. The LDO and the Comparator will remain functional past the UVLO threshold until VIN reaches approximately 2.25V. OVERVOLTAGE LOCKOUT (OVLO) The VIN voltage is monitored for a supply over voltage condition, for which the operation of the device cannot be ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to the PMU outputs from any damage and malfunction. Once VIN rises over 5.64V all the Bucks, and LDO will be disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An OVLO will force the device into the reset state; all internal registers are reset. Once the supply voltage is below the OVLO hysteresis, the device will initiate a power-up sequence, and then enter the active state. Operating maximum input voltage at which parameters are ensured is 5.5V. Absolute maximum of the device is 6.0V. DEVICE STATUS, INTERRUPT ENABLE The LM10504 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can be read via the serial interface. The interrupts are not latched to the register and will always represent the current state and will not be cleared on a read. If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1', and Interrupt output is asserted. There are 5 interrupt generating conditions: • Buck 3 output is over flag level (90% when rising, 85% when falling) • Buck 2 output is over flag level (90% when rising, 85% when falling) • Buck 1 output is over flag level (90% when rising, 85% when falling) • LDO is over flag level (90% when rising, 85% when falling • Comparator input voltage crosses over selected threshold Reading the interrupt register will not release Interrupt output. Interrupt generation conditions can be individually enabled or disabled by writing respective bits in INTERRUPT ENABLE register (0x0C) to '1' or '0'. 26 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 THERMAL SHUTDOWN (TSD) The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the device can not be ensured. The part will automatically be disabled if the temperature is too high (>140°C). The thermal shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below the TSD hysteresis, the device will initiate a powerup sequence and then enter the active state. In the active state, the part will start up as if for the first time, all registers will be in their default state. COMPARATOR The comparator on the LM10504 takes its inputs from the VCOMP pin and an internal threshold level which is programmed by the user. The threshold level is programmable between 2.0 and 4.0V with a step of 31 mV and a default comp code of 0x19. The output of the comparator is the Interrupt pin. Its polarity can be changed using Register 0x0E bit 0. If Interrupt_polarity = 0 → Active low (default) is selected, then the output is low if VCOMP value is greater than the threshold level. The output is high if the VCOMP value is less than the threshold level. If Interrupt_polarity = 1 → Active high is selected then the output is high if VCOMP value is greater than the threshold level. The output is low if the VCOMP value is less than the threshold level. There is some hysteresis when VCOMP transitions from high to low, typically 60 mV. There is a control bit in register 0x0B, comparator control, that can double the hysteresis value. VTHRES VCOMP Interrupt + Interrupt - VCOMP Delay due to hysteresis VTHRES External Components Selection All three switchers require an input capacitor and an output inductor-capacitor filter. These components are critical to the performance of the device. All three switchers are internally compensated and do not require external components to achieve stable operation. The output voltages of the bucks can be programmed through the SPI pins. OUTPUT INDUCTORS & CAPACITORS SELECTION There are several design considerations related to the selection of output inductors and capacitors: • Load transient response • Stability • Efficiency • Output ripple voltage • Over current ruggedness The device has been optimized for use with nominal LC values as shown in the Typical Application Circuit. INDUCTOR SELECTION The recommended inductor values are shown in Typical Application Diagram. It is important to ensure the inductor core does not saturate during any foreseeable operational situation. The inductor should be rated to handle the peak load current plus the ripple current: Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 27 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com IL(MAX) = ILOAD(MAX) + 'IRIPPLE = ILOAD(MAX) + D x (VIN - VOUT) 2 x L x FS D x (VIN - VOUT) ~ ILOAD(MAX) + (A typ.), ~ 2 x 2.2 x 2.0 D = VOUT , FS = 2 MHz, L = 2.2 PH VIN (2) There are two methods to choose the inductor saturation current rating: Recommended Method for Inductor Selection: The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating greater than the maximum device current limit, as specified in the Electrical Characteristics tables. In this case the device will prevent inductor saturation by going into current limit before the saturation level is reached. Alternate Method for Inductor Selection: If the recommended approach cannot be used care must be taken to ensure that the saturation current is greater than the peak inductor current: ISAT > ILPEAK IRIPPLE 2 D x (VIN ± VOUT) IRIPPLE = L x FS VOUT D= VIN x EFF ILPEAK = IOUTMAX + • • • • • • • • • • ISAT:Inductor saturation current at operating temperature ILPEAK: Peak inductor current during worst case conditions IOUTMAX: Maximum average inductor current IRIPPLE: Peak-to-Peak inductor current VOUT: Output voltage VIN: Input voltage L: Inductor value in Henries at IOUTMAX F: Switching frequency, Hertz D: Estimated duty factor EFF: Estimated power supply efficiency (3) ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst-case conditions, etc. Suggested Inductors and Their Suppliers The designer should choose the inductors that best match the system requirements. A very wide range of inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance loss limited), series resistance, maximum operating frequency, losses, etc. In general, smaller physical size inductors will have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very lowprofile inductors may have even higher series resistance. The designer should try to find the best compromise between system performance and cost. Table 3. Recommended Inductors Value Manufacturer Part Number DCR Current Package 2.2 µH Murata LQH55PN2R2NR0L 31 mΩ 2.5A 2220 2.2 µH TDK NLC565050T-2R2K-PF 60 mΩ 1.3A 2220 2.2 µH Murata LQM2MPN2R2NG0 110 mΩ 1.2A 806 28 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 OUTPUT AND INPUT CAPACITORS CHARACTERISTICS CAP VALUE (% of NOMINAL 1 PF) Special attention should be paid when selecting these components. As shown in the following figure, the DC bias of these capacitors can result in a capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g., 0402) may not be suitable in the actual application. 0603, 10V, X5R 100 80 60 0402, 6.3V, X5R 40 20 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 27. Typical Variation in Capacitance vs. DC Bias The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 44 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −30°C, so some guard band must be allowed. Output Capacitor Selection L ESR SW1/2/3 COUT The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their inductive component can usually be neglected at the frequency ranges at which the switcher operates. VOUT1/2/3 OUTPUT CAPACITOR The output-filter capacitor smooths out the current flow from the inductor to the load and helps maintain a steady output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and low enough ESR to perform these functions. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 29 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 www.ti.com Note that the output voltage ripple increases with the inductor current ripple and the Equivalent Series Resistance of the output capacitor (ESRCOUT). Also note that the actual value of the capacitor’s ESRCOUT is frequency and temperature dependent, as specified by its manufacturer. The ESR should be calculated at the applicable switching frequency and ambient temperature. D x (VIN - VOUT) V üIRIPPLE and D = OUT where üIRIPPLE = VOUT-RIPPLE-PP = 2 x L x FS 8 x FS x COUT VIN (4) Output ripple can be estimated from the vector sum of the reactive (capacitance) voltage component and the real (ESR) voltage component of the output capacitor where: VOUT-RIPPLE-PP = 2 V 2 ROUT +V COUT (5) where: VROUT = IRIPPLE x ESRCOUT and VCOUT = • • • IRIPPLE 8 x FS x COUT VOUT-RIPPLE-PP: estimated output ripple, VROUT: estimated real output ripple, VCOUT: estimated reactive output ripple. (6) The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The recommended value for the output capacitors is 22 μF, 6.3V with an ESR of 2mΩ or less. The output capacitors need to be mounted as close as possible to the output/ground pins of the device. Table 4. Recommended Output Capacitors Model Type Vendor Vendor Voltage Rating Case Size 08056D226MAT2A Ceramic, X5R AVX Corporation 6.3V 0805, (2012) C0805L226M9PACTU Ceramic, X5R Kemet 6.3V 0805, (2012) ECJ-2FB0J226M Ceramic, X5R Panasonic - ECG 6.3V 0805, (2012) JMK212BJ226MG-T Ceramic, X5R Taiyo Yuden 6.3V 0603, (1608) C2012X5R0J226M Ceramic, X5R TDK Corporation 6.3V 0603, (1608) Input Capacitor Selection There are 3 buck regulators in the LM10504 device. Each of these buck regulators has its own input capacitor which should be located as close as possible to their corresponding SWx_VIN and SWx_GND pins, where x designates Buck 1, 2 or 3. The 3 buck regulators operate at 120° out of phase, which means that they switch on at equally spaced intervals, in order to reduce the input power rail ripple. It is recommended to connect all the supply/ground pins of the buck regulators, SWx_VIN to two solid internal planes located under the device. In this way, the 3 input capacitors work together and further reduce the input current ripple. A larger tantalum capacitor can also be located in the proximity of the device. The input capacitor supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle both the RMS current and the dissipated power. The input capacitor must be rated to handle this current: IRMS_CIN = IOUT VOUT (VIN - VOUT) VIN (7) The power dissipated in the input capacitor is given by: PD_CIN = I2RMS_CIN x RESR_CIN 30 (8) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 The device is designed to be used with ceramic capacitors on the inputs of the buck regulators. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The minimum recommended value for the input capacitor is 10 µF with an ESR of 10 mΩ or less. The input capacitors need to be mounted as close as possible to the power/ground input pins of the device. The input power source supplies the average current continuously. During the PFET switch on-time, however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the input capacitor. A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is estimated as follows: VPPIN = IOUT x D + IOUT x ESRCIN CIN x FS where: • • • • VPPIN: estimated peak-to-peak input ripple voltage, IOUT: Output Current CIN: Input capacitor value ESRCIN: input capacitor ESR. (9) This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: © • I2RIPPLE 12 § © IRMSCIN = D x §I2OUT + IRMSCIN: estimated input capacitor RMS current. (10) PCB Layout Considerations PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. S CIN L D N COUT PGND LOOP2 G VIN CONTROL LOOP1 VOUT P D SW VIN G S U1 LM10504 Figure 28. Schematic of LM10504 Highlighting Layout Sensitive Nodes 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched rapidly. The first loop starts from the CIN input capacitor, to the regulator SWx_VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor COUT and load. The second loop starts from the output capacitor ground, to the regulator SWx_GND pins, to the inductor and then out to COUT and the load (see figure above). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitors should consist of a small localized top side plane that connects to PGND. The inductor should be placed as close as possible to the SW pin and output Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 31 LM10504 SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 2. 3. 4. 5. www.ti.com capacitor. Minimize the copper area of the switch node. The SW pins should be directly connected with a trace that runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause too much capacitive loading on the SW pin. The inductors should be placed as close as possible to the SW pins to further minimize the copper area of the switch node. Have a single point ground for all device analog grounds. The ground connections for the feedback components should be connected together then routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior. Minimize trace length to the FB pin. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. Figure 29. Possible PCB Layout Configuration to Use 6X Through Hole Vias in the Middle Outside 7x7 array 0.4 mm DSBGA 34-bump, with 24 peripheral and 6 inner vias = 30 individual signals PCB LAYOUT THERMAL DISSIPATION FOR DSBGA PACKAGE 1. Position ground layer as close as possible to DSBGA package. Second PCB layer is usually good option. LM10504 evaluation board is a good example. 2. Draw power traces as wide as possible. Bumps which carry high currents should be connected to wide traces. This helps the silicon to cool down. 32 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 LM10504 www.ti.com SNVS739E – DECEMBER 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 32 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM10504 33 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM10504TME/NOPB ACTIVE DSBGA YFR 34 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 V039 LM10504TMX/NOPB ACTIVE DSBGA YFR 34 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 V039 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM10504TME/NOPB DSBGA YFR 34 250 178.0 8.4 LM10504TMX/NOPB DSBGA YFR 34 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.02 3.02 0.76 4.0 8.0 Q1 3.02 3.02 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10504TME/NOPB DSBGA YFR LM10504TMX/NOPB DSBGA YFR 34 250 210.0 185.0 35.0 34 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFR0034xxx D 0.600±0.075 E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE TME34XXX (Rev B) D: Max = 2.84 mm, Min = 2.78 mm E: Max = 2.84 mm, Min = 2.78 mm 4215092/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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