CY2907 Single-PLL General Purpose EPROM Programmable Clock Generator Single-PLL General Purpose EPROM Programmable Clock Generator Features Benefits ■ Single phase locked loop (PLL) architecture ■ Generates a custom frequency from an external source ■ EPROM programmability ■ Easy customization and fast turnaround ■ Factory programmable (CY2907) or field programmable (CY2907F) device options ■ Programming support available for all opportunities Up to two configurable outputs ■ Provides clocking requirements from a single device ■ Low skew, low jitter, high accuracy outputs ■ Meets critical industry standard timing requirements ■ Power management (power-down, OE) ■ Supports low power applications ■ Frequency select option ■ Up to 16 user selectable frequencies ■ Configurable 5 V or 3.3 V Operation ■ Supports industry standard design platforms ■ 8-pin or 14-pin SOIC packages ■ Industry standard packaging saves on board space ■ Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-07137 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 2, 2013 CY2907 Contents Pin Configurations ........................................................... 3 Pin Description ................................................................. 3 Functional Description ..................................................... 4 Device Programming ........................................................ 4 CyberClocks™ Software .................................................. 4 Cypress CY3670 Programming Kit ................................. 4 Maximum Ratings ............................................................. 4 Operating Conditions ....................................................... 4 Electrical Characteristics at 5.0 V Commercial ............. 5 Electrical Characteristics at 3.3 V Commercial ............. 5 Switching Characteristics at 5.0 V Commercial ............ 6 Switching Characteristics at 3.3 V Commercial ............. 6 Switching Waveforms ...................................................... 7 Document Number: 38-07137 Rev. *G Test Circuit ........................................................................ 7 Ordering Information ........................................................ 8 Ordering Code Definitions ........................................... 8 Package Characteristics .................................................. 8 Package Diagrams ............................................................ 9 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 2 of 13 CY2907 Pin Configurations Figure 1. 14-pin SOIC and 8-pin SOIC (Top View) S1 S2 1 2 14 13 S0 R EFC LK S3 V SS 3 4 12 11 V DD C LKA V SS PD X T A L IN 5 6 7 10 9 8 OEA OER XTALO U T S0 V SS 1 2 8 7 R EFC LK V DD X T A L IN XTALO U T 3 4 6 5 C LKA S1 Pin Description Name Pin Number Description 14-pin SOIC 8-pin SOIC S1 1 5 Frequency select (CLKA) (internal pull-up resistor to VDD) S2 2 NA Frequency select (CLKA) (internal pull-up resistor to VDD) S3 3 NA Frequency select (CLKA) (internal pull-up resistor to VDD) VSS 4 2 Ground VSS 5 NA Ground PD 6 NA Power-down (active LOW) (internal pull-up resistor to VDD) XTALIN[1] 7 3 Reference crystal input XTALOUT[1, 2] 8 4 Reference crystal feedback OER 9 NA REFCLK output enable (active HIGH) (internal pull-up resistor to VDD) OEA 10 NA CLKA output enable (active HIGH) (internal pull-up resistor to VDD) CLKA 11 6 Clock output VDD 12 7 Voltage supply REFCLK 13 8 Reference clock output (default, can be driven by PLL if desired) S0 14 1 Frequency select (CLKA) (internal pull-up resistor to VDD) Notes 1. For best accuracy, use a parallel resonant crystal, CLOAD 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). Document Number: 38-07137 Rev. *G Page 3 of 13 CY2907 Functional Description The CY2907 is a general purpose clock generator designed for use in a wide variety of applications—from graphics to PC peripherals to disk drives. It generates selectable system clock frequencies from a single reference input (crystal or reference clock). The CY2907 is configured with an EPROM array, similar to the other devices in the Cypress EPROM Programmable Clock family, making it easy to customize for any application. Furthermore, the CY2907 is compatible with all industry standard 9107 and 9108 clock synthesizers. Device Programming Two versions of the CY2907 are available - Field Programmable and Factory Programmable. Field programmable devices must be programmed before being installed in an application. They are one-time-programmable (OTP). Customers can program small quantities in-house using the Cypress CY3670 programmer. Production quantities are available through Cypress’s value-added distribution partners, or by using third party programmers from BP Microsystems, Hi-Lo Systems, and others. Note the output frequency ranges in this data sheet when specifying them in CyberClocks to make sure that you stay within the limits. After a configuration is established, you can print the configuration and save programming files in ENT and JED formats. CyberClocks runs on PCs running the Windows™ operating system, and is available for free download on the Cypress Semiconductor website at www.cypress.com. Within the CyberClocks application, the CY2907 is found in the CyClocks™ section. Note that the standalone CyberClocks software should not be confused with the CyberClocks Online software, which is a web-based application that is used to configure other programmable clock devices. Cypress CY3670 Programming Kit Cypress’s CY3670 is a portable programmer that connects to a PC serial port and enables users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. An adapter is also required and is ordered separately. The CY3097 is the adapter for the CY2907F8. For the CY2907F14, order adapter CY3098. For high volume orders, devices can be factory programmed by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, you receive a new part number, samples, and a data sheet with the programmed values. This part number is used for additional sample requests and production orders. Maximum Ratings CyberClocks™ Software Storage temperature (non-condensing).... –65 °C to +150 °C CyberClocks is an easy-to-use software application that enables the user to configure any one of the EPROM Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Junction temperature............................................... +150 °C Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage ................................................. –0.5 to +7.0 V Input voltage ........................................ –0.5 V to VDD + 0.5 V Max soldering temperature (10 sec)........................ +260 °C Static discharge voltage........................................... > 2000 V (per MIL-STD-883, method 3015) Operating Conditions[3] Parameter VDD Description Min Max Unit Supply voltage, 5 V operation 4.5 5.5 V Supply voltage, 3.3 V operation 3.0 3.6 V TA Commercial operating temperature, Ambient 0 70 °C CL Maximum capacitive load – 15 pF fREF External reference crystal 10.0 25.0 MHz 1.0 30.0 MHz External reference clock [4, 5] Notes 3. Electrical parameters are guaranteed with these operating conditions. 4. Guaranteed by design, not 100% tested in production. 5. Load = max typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD (mA) = VDD × (6.25 + (0.055 × FREF) + (0.0017 × CLOAD × (FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz. Document Number: 38-07137 Rev. *G Page 4 of 13 CY2907 Electrical Characteristics at 5.0 V Commercial VDD = 4.5 V to 5.5 V, TA = 0 °C to +70 °C Parameter Description Test Conditions Min Max Unit VIH High-level input voltage Except crystal inputs 2.0 – V VIL Low-level input voltage Except crystal inputs – 0.8 V VOH[6] VOL[6] IOH[6] IOL[6] High-level output voltage VDD = VDD Min. IOH = –30 mA CLKA 2.4 – V Low-level output voltage CLKA – 0.4 V Output high current VDD = VDD Min. IOL = 10 mA VOH = 2.0 V – –35 mA Output low current VOL = 0.8 V 22 – mA IIH Input high current VIH = VDD –2 2 µA IIL Input low current VIL = 0V – 20 µA IDD[7] Power supply current PD HIGH, CLKA = 50 MHz – 42 mA IDD Power supply current PD LOW, Logic inputs LOW – 100 µA IDD Power supply current PD LOW, Logic inputs HIGH – 40 µA RPU[6] Pull-up resistor VIN = VDD – 1.0 V – 700 k Min Max Unit 0.7 × VDD – V Electrical Characteristics at 3.3 V Commercial VDD = 3.0 V to 3.6 V, TA = 0 °C to +70 °C Parameter Description Test Conditions VIH High-level input voltage Except crystal inputs VIL Low-level input voltage Except crystal inputs – 0.2 × VDD V VOH[8] High-level output voltage CLKA, IOH = –5 mA 0.85 × VDD – V VOL[8] IOH[8] IOL[8] Low-level output voltage CLKA, IOL = 6 mA – 0.1 × VDD V Output high current VOH = 0.7 × VDD – –10 mA Output low current VOL = 0.2 × VDD 15 – mA IIH Input high current VIH = VDD –2 2 µA IIL Input low current VIL = 0 V – 10 µA IDD[9] Power supply current PD HIGH, CLKA = 50 MHz – 40 mA IDD Power supply current PD LOW, Logic inputs LOW – 40 µA IDD Power supply current PD LOW, Logic inputs HIGH – 12 µA RPU[8] Pull-up resistor VIN = VDD – 0.5 V – 900 k Notes 6. Guaranteed by design, not 100% tested in production. 7. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD (mA) = VDD × (6.25 + (0.055 × FREF) + (0.0017 × CLOAD × (FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz. 8. Guaranteed by design, not 100% tested in production. 9. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD (mA) = VDD × (6.25 + (0.055 × FREF) + (0.0017 × CLOAD × (FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz. : Document Number: 38-07137 Rev. *G Page 5 of 13 CY2907 Switching Characteristics at 5.0 V Commercial[10] Parameter Output[11] Description Test Conditions Min Max Unit tR CLKA Output rise time 0.8 V to 2.0 V 15 pF load – 1.40 ns tF CLKA Output fall time 2.0 V to 0.8 V 15 pF load – 1.00 ns tR CLKA Output rise time 20% to 80% 15 pF load – 3.5 ns tF CLKA Output fall time 80% to 20% 15 pF load – 2.5 ns tD CLKA Duty cycle 15 pF load at 1.4 V 45.0 55.0 % FI XTALIN Input frequency Crystal oscillator 10 25 MHz FI XTALIN Input frequency External input clock[12] 1 30 MHz FO CLKA Output frequency CY2907, 15 pF load 0.5 130.0 MHz CY2907F, 15 pF load 0.5 100.0 MHz tJIS CLKA Jitter (one sigma) 20 MHz to 130 MHz – 150 ps tJIS CLKA Jitter (one sigma) 14 MHz to 20 MHz – 200 ps tJIS CLKA Jitter (one sigma) Less than 14 MHz – 1 % tJAB CLKA Jitter (absolute) 20 MHz to 130 MHz –250 + 250 ps tJAB CLKA Jitter (absolute) 14 MHz to 20 MHz –500 + 500 ps tJAB CLKA Jitter (absolute) Less than 14 MHz – 3 % – 18 ms – 13 ms Min Max Unit tPU tFT Power-up time CLKA Transition time 8 MHz to 66.6 MHz Switching Characteristics at 3.3 V Commercial[10] Parameter Output[11] Description Test Conditions tR CLKA Output rise time 20% to 80% 15 pF Load – 3.5 ns tF CLKA Output fall time 80% to 20% 15 pF Load – 2.5 ns tD CLKA Duty cycle 15 pF Load at 1.4 V 40.0 53.0 % FI XTALIN Input frequency Crystal Oscillator 10 25 MHz FI XTALIN Input frequency External Input Clock[12] 1 30 MHz FO CLKA Output frequency CY2907, 15 pF Load 0.5 100.0 MHz CY2907F, 15 pF Load 0.5 80.0 MHz tJIS CLKA Jitter (one sigma) 25 MHz to 100 MHz – 150 ps tJIS CLKA Jitter (one sigma) 14 MHz to 25 MHz – 200 ps tJIS CLKA Jitter (one sigma) Less than 14 MHz – 1 % tJAB CLKA Jitter (absolute) 25 MHz to 120 MHz –250 +250 ps tJAB CLKA Jitter (absolute) 14 MHz to 25 MHz –500 +500 ps tJAB CLKA Jitter (absolute) Less than 14 MHz – 3 % – 18 ms – 13 ms Power-up time tPU tFT CLKA Transition time 8 MHz to 66.6 MHz Notes 10. Guaranteed by design, not 100% tested in production. 11. REFCLK output can also be configured to be driven by the PLL. In that case these characteristics are also valid. 12. Refer to the application note Crystal Oscillator Topics when using an external reference clock as an input frequency source. Document Number: 38-07137 Rev. *G Page 6 of 13 CY2907 Switching Waveforms Figure 2. Frequency Select Change (Transition Time) OLD SELECT SELECT NEW SELECT STABLE Fnew tFT Fold CLKA Figure 3. Duty Cycle Timing tD = t2 t1 t1 t2 CLKA 1.4 V Figure 4. All Outputs Rise/Fall Time CLKA 80% 20% tR tF Test Circuit Figure 5. Test Circuit VDD VDD CLKA CLOAD 0.1 F OUTPUTS REFCLK CLOAD Note: All capacitors should be placed as close to each pin as possible. Document Number: 38-07137 Rev. *G Page 7 of 13 CY2907 Ordering Information Ordering Code Package Type Operating Range Pb-free CY2907FX8[13] 8-pin SOIC 5.0 V/3.3 V, Commercial, Field programmable CY2907FX8T[13] 8-pin SOIC - Tape and Reel 5.0 V/3.3 V, Commercial, Field programmable CY2907FX14 14-pin SOIC 5.0 V/3.3 V, Commercial, Field programmable CY2907FX14T[13] 14-pin SOIC - Tape and Reel 5.0 V/3.3 V, Commercial, Field programmable [13] Programmer CY3670 Cypress FTG programmer CY3097 Socket Adapter for CY3670 for programming CY2907FX8 CY3098 Socket Adapter for CY3670 for programming CY2907FX14 Ordering Code Definitions CY 2907 XX XXX T T = Tape and Reel, Blank = Tube Dash or Variant Code XX = SL or FX SL = SOIC package FX = Pb-free SOIC package Base part number Company ID: CY = Cypress Package Characteristics JA (C/W) JC (C/W) Transistor Count 8-pin SOIC 170 35 5436 14-pin SOIC 140 31 5436 Package Note 13. Not for new designs. New designs should use a device other than the CY2907. Document Number: 38-07137 Rev. *G Page 8 of 13 CY2907 Package Diagrams Figure 6. 8-pin (150-Mil) SOIC 51-85066 *F Document Number: 38-07137 Rev. *G Page 9 of 13 CY2907 Figure 7. 14-pin (150-Mil) SOIC 51-85067 *D Document Number: 38-07137 Rev. *G Page 10 of 13 CY2907 Acronyms Acronym Description EPROM erasable programmable read only memory OE output enable PLL phase-locked loop SOIC small-outline integrated circuit TSSOP thin-shrink small outline package Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius k kilo ohm MHz megahertz µA microampere mA milliampere ms millisecond mW milliwatt ns nanosecond % percent pF picofarad ppm parts per million ps picosecond V volt Document Number: 38-07137 Rev. *G Page 11 of 13 CY2907 Document History Page Document Title: CY2907 Single-PLL General Purpose EPROM Programmable Clock Generator Document Number: 38-07137 Revision ECN Orig. of Change Submission Date Description of Change ** 110246 SZV 12/18/01 Change from Spec number: 38-00505 to 38-07137 *A 1088524 KVM/ KKVTMP See ECN Added Pb-free for CY2907F8 and CY2907F14 field programmable devices Updated and added to text on page 2 Applied new template *B 2715646 KVM/AESA 06/10/09 Removed obsolete part numbers from the ordering information table: CY2907SC-xxx, CY2907SC-xxxT, CY2907SI-xxx, CY2907SI-xxxT, CY2907F8T, CY2907F8I, CY2907F8IT, CY2907F14T, CY2907F14I and CY2907F14IT Added note: “Not for new designs” Removed industrial temperature references: page 1 features list, TA spec, DC and AC electrical tables Removed Selector Guide table from page 1 *C 2948496 KVM 06/09/10 Updated package diagrams and ordering information table. *D 3051170 BASH 10/07/2010 Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. *E 3155189 BASH 01/27/2011 No technical updates. *F 3402027 BASH 10/11/2011 Removed the following pruned parts: CY2907SL-262 and CY2907SL-262T from the Ordering Information table. Updated package diagrams. *G 4047640 CINM 07/02/2013 Updated Package Diagrams: spec 51-85066 – Changed revision from *E to *F. Completing Sunset Review. Document Number: 38-07137 Rev. *G Page 12 of 13 CY2907 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07137 Rev. *G Revised July 2, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 13 of 13