TI1 MSP430G2333IPW8RQ1 Automotive mixed-signal microcontroller Datasheet

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MSP430G2333-Q1
SLAS802A – OCTOBER 2013 – REVISED MARCH 2014
MSP430G2333-Q1 Automotive Mixed-Signal Microcontroller
1 Features
2 Applications
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Qualified for Automotive Applications
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultra-Low-Power Consumption
– Active Mode: 230 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wakeup From Standby Mode in Less
Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With Four
Calibrated Frequency
– Internal Very-Low-Power Low-Frequency (LF)
Oscillator
– 32-kHz Crystal
– External Digital Clock Source
Two 16-Bit Timer_A With Three Capture/Compare
Registers
Up to 24 Capacitive-Touch Enabled I/O Pins
Universal Serial Communication Interface (USCI)
– Enhanced UART Supports Auto Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
10-Bit 200-ksps Analog-to-Digital Converter (ADC)
With Internal Reference, Sample-and-Hold, and
Autoscan
Brownout Detector
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Table 1 Summarizes Available Family Members
Package Options
– TSSOP: 20 Pin, 28 Pin
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
Power Management
Sensor Interface
Capacitive Touch
3 Description
The Texas Instruments MSP430™ family of ultra-lowpower microcontrollers consists of several devices
that feature different sets of peripherals targeted for
various applications. The architecture, combined with
five low-power modes, is optimized to achieve
extended battery life in portable measurement
applications. The device features a powerful 16-bit
RISC CPU, 16-bit registers, and constant generators
that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the device
to wake up from low-power modes to active mode in
less than 1 µs.
The MSP430G2333 devices are ultra-low-power
mixed signal microcontrollers with built-in 16-bit
timers, up to 24 I/O capacitive-touch enabled pins, a
10-bit A/D converter, and built-in communication
capability using the universal serial communication
interface. For configuration details, see Table 1.
Typical applications include low-cost sensor systems
that capture analog signals, convert them to digital
values, and then process the data for display or for
transmission to a host system.
Device Information (1)
PACKAGE
(PIN)
BODY SIZE
MSP430G2333IPW8RQ1
PW (28)
9.7 mm x 4.4 mm
MSP430G2333IPW0RQ1
PW (20)
6.5 mm x 4.4 mm
ORDER NUMBER
(1)
For the most current part, package, and ordering information,
see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430G2333-Q1
SLAS802A – OCTOBER 2013 – REVISED MARCH 2014
www.ti.com
4 Functional Block Diagram
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
8
P3.x
8
Port P1
8 I/O
Interrupt
capability
pullup or
pulldown
resistors
Port P2
8 I/O
Interrupt
capability,
pullup or
pulldown
resistors
Port P3
8 I/O
Pullup or
pulldown
resistors
ACLK
Clock
System
SMCLK
Flash
RAM
ADC
4KB
256B
10-Bit
8 Ch.
Autoscan
1 ch DMA
MCLK
16-MHz
CPU
incl. 16
Registers
MAB
MDB
Emulation
2BP
JTAG
Interface
Brownout
Protection
Watchdog
WDT+
15-Bit
Timer0_A3
Timer1_A3
3 CC
Registers
3 CC
Registers
Spy-BiWire
USCI A0
UART,
LIN, IrDA,
SPI
USCI B0
SPI, I2C
RST/NMI
NOTE: Port P3 is available on 28-pin devices only.
Figure 1. Functional Block Diagram
2
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Functional Block Diagram ....................................
Revision History.....................................................
Device Characteristics ..........................................
Terminal Configuration and Functions................
1
1
1
2
4
4
5
7.1 20-Pin PW Package (Top View) ............................... 5
7.2 28-Pin PW Package (Top View) ............................... 5
7.3 Terminal Functions.................................................... 6
8
Detailed Description .............................................. 8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
CPU........................................................................... 8
Instruction Set ........................................................... 8
Operating Modes....................................................... 9
Interrupt Vector Addresses ..................................... 10
Special Function Registers (SFRs)......................... 11
Memory Organization.............................................. 12
Bootstrap Loader (BSL) .......................................... 12
Flash Memory ......................................................... 12
Peripherals .............................................................. 13
Specifications....................................................... 18
9.1 Absolute Maximum Ratings ................................... 18
9.2 Recommended Operating Conditions..................... 18
9.3 Active Mode Supply Current Into VCC Excluding
External Current....................................................... 19
9.4 Typical Characteristics, Active Mode Supply Current
(Into VCC) ................................................................. 19
9.5 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current ...................................... 20
9.6 Typical Characteristics, Low-Power Mode Supply
Currents ................................................................... 20
9.7 Schmitt-Trigger Inputs, Ports Px ............................. 21
9.8 Leakage Current, Ports Px...................................... 21
9.9 Outputs, Ports Px .................................................... 21
9.10 Output Frequency, Ports Px.................................. 21
9.11 Typical Characteristics, Outputs ........................... 22
9.12 Pin-Oscillator Frequency – Ports Px ..................... 23
9.13 Typical Characteristics, Pin-Oscillator Frequency 23
9.14 POR, BOR............................................................. 24
9.15 Main DCO Characteristics .................................... 26
9.16 DCO Frequency .................................................... 26
9.17 Calibrated DCO Frequencies, Tolerance.............. 27
9.18 Wakeup From Lower-Power Modes (LPM3, LPM4)
................................................................................. 28
9.19 Typical Characteristics, DCO Clock Wakeup Time
From LPM3 or LPM4................................................ 28
9.20 Crystal Oscillator, XT1, Low-Frequency Mode .... 29
9.21 Internal Very-Low-Power Low-Frequency Oscillator
(VLO)........................................................................ 29
9.22 Timer_A................................................................. 29
9.23 USCI (UART Mode) .............................................. 30
9.24 USCI (SPI Master Mode) ...................................... 30
9.25 USCI (SPI Slave Mode) ........................................ 31
9.26 USCI (I2C Mode) ................................................... 32
9.27 10-Bit ADC, Power Supply and Input Range
Conditions ................................................................ 33
9.28 10-Bit ADC, Built-In Voltage Reference ................ 34
9.29 10-Bit ADC, External Reference ........................... 35
9.30 10-Bit ADC, Timing Parameters............................ 35
9.31 10-Bit ADC, Linearity Parameters......................... 35
9.32 10-Bit ADC, Temperature Sensor and Built-In
VMID .......................................................................... 36
9.33 Flash Memory ....................................................... 36
9.34 RAM ...................................................................... 37
9.35 JTAG and Spy-Bi-Wire Interface........................... 37
9.36 JTAG Fuse ............................................................ 37
10 I/O Port Schematics ............................................ 38
10.1 Port P1 Pin Schematic: P1.0 to P1.2, Input/Output
With Schmitt Trigger ................................................ 38
10.2 Port P1 Pin Schematic: P1.3, Input/Output With
Schmitt Trigger......................................................... 40
10.3 Port P1 Pin Schematic: P1.4, Input/Output With
Schmitt Trigger......................................................... 42
10.4 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output
With Schmitt Trigger ................................................ 44
10.5 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output
With Schmitt Trigger ................................................ 46
10.6 Port P2 Pin Schematic: P2.6, Input/Output With
Schmitt Trigger......................................................... 48
10.7 Port P2 Pin Schematic: P2.7, Input/Output With
Schmitt Trigger......................................................... 50
11 Device and Documentation Support ................. 52
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
52
54
54
55
55
55
12 Mechanical, Packaging, and Orderable
Information ........................................................... 55
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5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
REVISION
SLAS802
DESCRIPTION
Production Data release
Formatting and document organization changes throughout.
SLAS802A
Removed all device variants except for MSP430G2333.
Added Device and Documentation Support and Mechanical, Packaging, and Orderable Information.
6 Device Characteristics
Table 1. Family Members (1) (2)
Device
MSP430G2333
(1)
(2)
4
BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
ADC10
Channel
USCI
A0/B0
Clock
I/O
Package
Type
20-TSSOP
1
4
256
2x TA3
8
1
LF,
DCO,
VLO
16
1
24
28-TSSOP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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7 Terminal Configuration and Functions
7.1 20-Pin PW Package (Top View)
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
1
20
2
19
3
18
4
5
6
17
PW20
(TOP VIEW)
16
15
7
14
8
13
9
12
10
11
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
7.2 28-Pin PW Package (Top View)
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS
P3.1/TA1.0
P3.0/TA0.2
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P3.2/TA1.1
P3.3/TA1.2
1
28
2
27
3
26
4
25
5
24
6
7
8
23
PW28
(TOP VIEW)
22
21
9
20
10
19
11
18
12
17
13
16
14
15
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK
P3.7/TA1CLK
P3.6/TA0.2
P3.5/TA0.1
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
P3.4/TA0.0
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7.3 Terminal Functions
Table 2. Terminal Functions
TERMINAL
NAME
NO.
PW28
I/O
DESCRIPTION
PW20
P1.0/
General-purpose digital I/O pin
TA0CLK/
ACLK/
2
2
I/O
Timer0_A, clock signal TACLK input
ACLK signal output
A0
ADC10 analog input A0
P1.1/
General-purpose digital I/O pin
TA0.0/
Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit
UCA0RXD/
3
3
I/O
USCI_A0 receive data input in UART mode
UCA0SOMI/
USCI_A0 slave data out/master in SPI mode
A1
ADC10 analog input A1
P1.2/
General-purpose digital I/O pin
TA0.1/
Timer0_A, capture: CCI1A input, compare: Out1 output
UCA0TXD/
4
4
I/O
USCI_A0 transmit data output in UART mode
UCA0SIMO/
USCI_A0 slave data in/master out in SPI mode
A2
ADC10 analog input A2
P1.3/
General-purpose digital I/O pin
ADC10CLK/
A3/
5
5
I/O
ADC10, conversion clock output
ADC10 analog input A3
VREF-/VEREF-
ADC10 negative reference voltage
P1.4/
General-purpose digital I/O pin
SMCLK/
SMCLK signal output
UCB0STE/
UCA0CLK/
USCI_B0 slave transmit enable
6
6
I/O
USCI_A0 clock input/output
A4/
ADC10 analog input A4
VREF+/VEREF+
ADC10 positive reference voltage
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General-purpose digital I/O pin
TA0.0/
Timer0_A, compare: Out0 output / BSL receive
UCB0CLK/
UCA0STE/
7
7
I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
A5/
ADC10 analog input A5
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General-purpose digital I/O pin
TA0.1/
Timer0_A, compare: Out1 output
A6/
UCB0SOMI/
22
14
I/O
ADC10 analog input A6
USCI_B0 slave out/master in SPI mode,
UCB0SCL/
USCI_B0 SCL I2C clock in I2C mode
TDI/TCLK
JTAG test data input or test clock input during programming and test
P1.7/
General-purpose digital I/O pin
A7/
ADC10 analog input A7
UCB0SIMO/
23
15
I/O
USCI_B0 slave in/master out in SPI mode
UCB0SDA/
USCI_B0 SDA I2C data in I2C mode
TDO/TDI
JTAG test data output terminal or test data input during programming and test
P2.0/
TA1.0
6
10
8
I/O
General-purpose digital I/O pin
Timer1_A, capture: CCI0A input, compare: Out0 output
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Terminal Functions (continued)
Table 2. Terminal Functions (continued)
TERMINAL
NAME
P2.1/
TA1.1
P2.2/
TA1.1
P2.3/
TA1.0
P2.4/
TA1.2
P2.5/
TA1.2
NO.
I/O
PW28
PW20
11
9
I/O
12
10
I/O
16
11
I/O
17
12
I/O
18
13
I/O
27
19
I/O
XIN/
P2.6/
P2.7
P3.0/
TA0.2
P3.1/
TA1.0
P3.2/
TA1.1
P3.3/
TA1.2
P3.4/
TA0.0
P3.5/
TA0.1
P3.6/
TA0.2
P3.7/
TA1CLK
Timer1_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin
Timer1_A, capture: CCI1B input, compare: Out1 output
General-purpose digital I/O pin
Timer1_A, capture: CCI0B input, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2B input, compare: Out2 output
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
26
18
I/O
9
-
I/O
8
-
I/O
13
-
I/O
14
-
I/O
15
-
I/O
19
-
I/O
20
-
I/O
21
-
I/O
24
16
I
RST/
NMI/
General-purpose digital I/O pin
Input terminal of crystal oscillator
TA0.1
XOUT/
DESCRIPTION
Output terminal of crystal oscillator
General-purpose digital I/O pin
General-purpose digital I/O pin
Timer0_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
Timer1_A, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, compare: Out1 output
General-purpose digital I/O
Timer1_A, compare: Out2 output
General-purpose digital I/O
Timer0_A, compare: Out0 output
General-purpose digital I/O
Timer0_A, compare: Out1 output
General-purpose digital I/O
Timer0_A, compare: Out2 output
General-purpose digital I/O
Timer1_A, clock signal TACLK input
Reset
Nonmaskable interrupt input
SBWTDIO
Spy-Bi-Wire test data input/output during programming and test
TEST/
25
17
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to
TEST.
I
SBWTCK
Spy-Bi-Wire test clock input during programming and test
DVCC
1
1
NA
Digital supply voltage
DVSS
28
20
NA
Ground reference
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8 Detailed Description
8.1 CPU
Instruction Set (continued)
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
8.2 Instruction Set
General-Purpose Register
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R14
General-Purpose Register
R15
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 4. Address Mode Descriptions (1)
(1)
8
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
OPERATION
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 -- --> R11
MOV 2(R5),6(R6)
M(2+R5) -- --> M(6+R6)
Indexed
✓
✓
MOV X(Rn),Y(Rm)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV &MEM,&TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) -- --> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) -- --> R11
R10 + 2-- --> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 -- --> M(TONI)
M(EDE) -- --> M(TONI)
M(MEM) -- --> M(TCDAT)
S = source, D = destination
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8.3 Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
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8.4 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
Timer1_A3
TACCR0 CCIFG (4)
Timer1_A3
(2)
(3)
(4)
(5)
(6)
(7)
(8)
10
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
maskable
0FFFAh
29
maskable
0FFF8h
28
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer0_A3
TACCR0 CCIFG (4)
maskable
0FFF2h
25
Timer0_A3
TACCR2 TACCR1 CCIFG, TAIFG
maskable
0FFF0h
24
maskable
0FFEEh
23
maskable
0FFECh
22
0FFEAh
21
USCI_A0, USCI_B0 receive
USCI_B0 I2C status
(1)
TACCR2 TACCR1 CCIFG, TAIFG
(2) (4)
SYSTEM
INTERRUPT
(5) (4)
UCA0RXIFG, UCB0RXIFG
(2) (5)
USCI_A0, USCI_B0 transmit
USCI_B0 I2C receive or transmit
UCA0TXIFG, UCB0TXIFG (2) (6)
ADC10
ADC10IFG (4)
maskable
0FFE8h
20
I/O Port P2 (up to eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
I/O Port P1 (up to eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
See
(7)
0FFDEh
15
See
(8)
0FFDEh to
0FFC0h
14 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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8.5 Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
2
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
3
2
1
0
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
5
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
4
NMIIFG
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
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8.6 Memory Organization
Table 8. Memory Organization
MSP430G2333
Memory
Size
4kB
Main: interrupt vector
Flash
0xFFFF to 0xFFC0
Main: code memory
Flash
0xFFFF to 0xF000
Information memory
RAM
Size
256 Byte
Flash
010FFh to 01000h
Size
256 Byte
0x02FF to 0x0200
Peripherals
16-bit
01FFh to 0100h
8-bit
0FFh to 010h
8-bit SFR
0Fh to 00h
8.7 Bootstrap Loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to
the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's
Guide (SLAU319).
Table 9. BSL Function Pins
BSL FUNCTION
20-PIN PW PACKAGE
28-PIN PW PACKAGE
Data transmit
3 - P1.1
3 - P1.1
Data receive
7 - P1.5
7 - P1.5
8.8 Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
12
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8.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
8.9.1 Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
8.9.2 Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
Table 10. Tags Used by the ADC Calibration Tags
NAME
ADDRESS
VALUE
DESCRIPTION
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C at
calibration
0x10DA
0x10
ADC10_1 calibration tag
-
0xFE
Identifier for empty memory areas
TAG_DCO_30
0x10F6
TAG_ADC10_1
TAG_EMPTY
Table 11. Labels Used by the ADC Calibration Tags
ADDRESS
OFFSET
SIZE
CAL_ADC_25T85
0x0010
word
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
CAL_ADC_25T30
0x000E
word
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR
0x000C
word
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
CAL_ADC_15T85
0x000A
word
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
0x0008
word
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
0x0006
word
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
CAL_ADC_OFFSET
0x0004
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_ADC_GAIN_FACTOR
0x0002
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
LABEL
CONDITION AT CALIBRATION / DESCRIPTION
CAL_BC1_1MHZ
0x0009
byte
-
CAL_DCO_1MHZ
0x0008
byte
-
CAL_BC1_8MHZ
0x0007
byte
-
CAL_DCO_8MHZ
0x0006
byte
-
CAL_BC1_12MHZ
0x0005
byte
-
CAL_DCO_12MHZ
0x0004
byte
-
CAL_BC1_16MHZ
0x0003
byte
-
CAL_DCO_16MHZ
0x0002
byte
-
8.9.3 Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
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8.9.4 Digital I/O
Up to three 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
• Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
• Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch
detection.
8.9.5 WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
8.9.6 Timer_A3 (TA0, TA1)
Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
PW20
PW28
DEVICE INPUT
SIGNAL
P1.0-2
P1.0-2
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW20
PW28
PinOsc
PinOsc
TACLK
INCLK
P1.1-3
P1.1-3
TA0.0
CCI0A
P1.1-3
P1.1-3
ACLK
CCI0B
P1.5-7
P1.5-7
-
P3.4-15
P1.2-4
P1.2-4
P1.6-14
P1.6-22
P2.6-19
P2.6-27
P1.2-4
14
MODULE
INPUT NAME
P1.2-4
CCR0
TA0
VSS
GND
VCC
VCC
TA0.1
CCI1A
CAOUT
CCI1B
VSS
GND
VCC
VCC
-
P3.5-19
-
P3.0-9
-
P3.6-20
-
P3.0-9
TA0.2
CCI2A
PinOsc
PinOsc
TA0.2
CCI2B
VSS
GND
VCC
VCC
CCR1
CCR2
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Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
PW20
PW28
DEVICE INPUT
SIGNAL
-
P3.7-21
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW20
PW28
-
P3.7-21
TACLK
INCLK
P2.0-8
P2.0-10
TA1.0
CCI0A
P2.0-8
P2.0-10
P2.3-11
P2.3-16
TA1.0
CCI0B
P2.3-11
P2.3-16
VSS
GND
VCC
VCC
CCR0
TA0
P3.1-8
P2.1-9
P2.1-11
TA1.1
CCI1A
P2.1-9
P2.1-11
P2.2-10
P2.2-12
TA1.1
CCI1B
P2.2-10
P2.2-12
VSS
GND
VCC
VCC
P2.4-12
P2.4-17
TA1.2
CCI2A
P2.5-13
P2.5-18
TA1.2
CCI2B
VSS
GND
VCC
VCC
CCR1
CCR2
TA1
P3.2-13
TA2
P2.4-12
P2.4-17
P2.5-13
P2.5-18
P3.3-14
8.9.7 Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI
functionality.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
8.9.8 ADC10
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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8.9.9 Peripheral File Map
Table 14. Peripherals With Word Access
MODULE
ADC10
REGISTER DESCRIPTION
ADC data transfer start address
Timer1_A3
ADC10SA
1BCh
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
Capture/compare register
TA1CCR2
0196h
Capture/compare register
TA1CCR1
0194h
Capture/compare register
TA1CCR0
0192h
TA1R
0190h
Capture/compare control
TA1CCTL2
0186h
Capture/compare control
TA1CCTL1
0184h
Capture/compare control
TA1CCTL0
0182h
TA1CTL
0180h
Timer_A interrupt vector
TA1IV
011Eh
Capture/compare register
TA0CCR2
0176h
Capture/compare register
TA0CCR1
0174h
Capture/compare register
TA0CCR0
0172h
Timer_A control
Timer_A register
TA0R
0170h
Capture/compare control
TA0CCTL2
0166h
Capture/compare control
TA0CCTL1
0164h
Capture/compare control
TA0CCTL0
0162h
Timer_A control
Flash Memory
Watchdog Timer+
OFFSET
ADC memory
Timer_A register
Timer0_A3
REGISTER
NAME
TA0CTL
0160h
Timer_A interrupt vector
TA0IV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
WDTCTL
0120h
REGISTER
NAME
OFFSET
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
USCI B0 I2C Interrupt enable
UCB0CIE
06Ch
USCI_B0 bit rate control 1
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
USCI_B0 I C slave address
UCB0SA
011Ah
USCI_B0 I2C own address
UCB0OA
0118h
Watchdog/timer control
Table 15. Peripherals With Byte Access
MODULE
USCI_B0
REGISTER DESCRIPTION
USCI_B0 status
2
16
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Table 15. Peripherals With Byte Access (continued)
REGISTER
NAME
OFFSET
USCI_A0 transmit buffer
UCA0TXBUF
067h
USCI_A0 receive buffer
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
UCA0CTL0
060h
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
MODULE
USCI_A0
ADC10
Basic Clock System+
Port P3
(28-pin PW only)
REGISTER DESCRIPTION
UCA0ABCTL
05Dh
ADC analog enable 0
ADC10AE0
04Ah
ADC analog enable 1
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P3 selection 2. pin
P3SEL2
043h
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P2 selection 2
P2SEL2
042h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
Port P3 input
Port P2
Port P2 interrupt enable
P2IE
02Dh
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 interrupt edge select
Port P2 input
Port P1
P2IN
028h
Port P1 selection 2
P1SEL2
041h
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Port P1 interrupt enable
Special Function
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9 Specifications
9.1 Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
(1)
±2 mA
(3)
Unprogrammed device
–55°C to 150°C
Programmed device
–55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
9.2 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
(1)
(2)
MAX
1.8
3.6
During flash programming
and erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency using the
USART module) (1) (2)
fSYSTEM
NOM
During program execution
UNIT
V
V
-40
85
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC = 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 2. Safe Operating Area
18
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9.3 Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
TA
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current at 1 MHz
IAM,1MHz
(1)
(2)
TEST CONDITIONS
VCC
MIN
TYP
2.2 V
230
3V
330
MAX
UNIT
µA
420
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
9.4 Typical Characteristics, Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC = 2.2 V
4.0
0.0
0.0
VCC − Supply Voltage − V
Figure 3. Active Mode Current vs VCC, TA = 25°C
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 4. Active Mode Current vs DCO Frequency
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9.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
56
µA
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.7
1.5
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
0.5
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.1
Low-power mode 4
(LPM4) current (5)
0.8
1.7
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
(2)
TYP
25°C
2.2 V
85°C
MAX
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
9.6 Typical Characteristics, Low-Power Mode Supply Currents
3.00
2.50
2.75
2.25
ILPM4 – Low-Power Mode Current – µA
ILPM3 – Low-Power Mode Current – µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
Vcc = 3.6 V
1.25
Vcc = 3 V
1.00
Vcc = 2.2 V
0.75
0.50
Vcc = 1.8 V
0.25
0.00
-40
-20
0
20
40
60
80
2.00
1.75
1.50
1.25
Vcc = 3.6 V
1.00
Vcc = 3 V
0.75
Vcc = 2.2 V
0.50
0.25
Vcc = 1.8 V
0.00
-40
-20
20
20
40
60
80
TA – Temperature – °C
TA – Temperature – °C
Figure 5. LPM3 Current vs Temperature
0
Figure 6. LPM4 Current vs Temperature
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9.7 Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
VCC
MIN
RPull
Pullup/pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
V
5
pF
9.8 Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
9.9 Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
I(OHmax) = –6 mA (1)
3V
VCC – 0.3
V
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
3V
VSS + 0.3
V
(1)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
9.10 Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
Clock output frequency
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ (1)
Px.y, CL = 20 pF
(2)
(2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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9.11 Typical Characteristics, Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
0
0.5
1
1.5
2
40
TA = 85°C
30
20
10
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
Figure 7. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 8. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
TA = 25°C
0
0
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
22
VCC = 3 V
P1.7
0.5
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
Figure 9. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 10. Typical High-Level Output Current vs High-Level
Output Voltage
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9.12 Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foP1.x
Port output oscillation frequency
foP2.x
Port output oscillation frequency
foP2.6/7
Port output oscillation frequency
foP3.x
(1)
(2)
Port output oscillation frequency
TEST CONDITIONS
P1.y, CL = 10 pF, RL = 100 kΩ
VCC
MIN
(1) (2)
3V
P1.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.6 and P2.7, CL = 20 pF, RL = 100
kΩ (1) (2)
P3.y, CL = 10 pF, RL = 100 kΩ
(1) (2)
P3.y, CL = 20 pF, RL = 100 kΩ
(1) (2)
3V
3V
3V
TYP
MAX
UNIT
1400
kHz
900
1800
kHz
1000
kHz
700
kHz
1800
kHz
1000
A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
9.13 Typical Characteristics, Pin-Oscillator Frequency
1.50
VCC = 3.0 V
1.35
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
fosc − Typical Oscillation Frequency − MHz
fosc − Typical Oscillation Frequency − MHz
1.50
VCC = 2.2 V
1.35
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
10
50
100
10
CLOAD − External Capacitance − pF
One output active at a time.
Figure 11. Typical Oscillating Frequency vs Load
Capacitance
50
100
CLOAD − External Capacitance − pF
One output active at a time.
Figure 12. Typical Oscillating Frequency vs Load
Capacitance
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9.14 POR, BOR (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 13
dVCC/dt ≤ 3 V/s
0.7 ×
V(B_IT--)
V(B_IT–)
See Figure 13 through Figure 15
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT–)
See Figure 13
dVCC/dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 13
2000
µs
t(reset)
Pulse duration needed at RST/NMI pin to
accepted reset internally
(1)
(2)
2.2 V
2
V
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–)is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 13. POR and BOR vs Supply Voltage
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
t pw − Pulse Width − µs
1 ns
1 ns
t pw − Pulse Width − µs
Figure 14. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal
24
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VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
1000
t pw − Pulse Width − µs
tf
tr
t pw − Pulse Width − µs
Figure 15. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
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9.15 Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency
fDCO(RSEL,DCO)
is
used
for
the
remaining
cycles.
The
frequency
is
an
average
equal
to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
faverage =
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
9.16 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3
3.6
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.054
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.067
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.49
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.70
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
3.78
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
5.24
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
7.73
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
10.65
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
14.65
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Measured at SMCLK output
3V
50
Duty cycle
26
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9.17 Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
1-MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
+3
%
1-MHz tolerance overall
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
+6
%
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
-3
±2
+3
%
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.2 V to 3.6 V
-6
±3
+6
%
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
-3
±2
+3
%
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.7 V to 3.6 V
-6
±3
+6
%
16-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
16-MHz tolerance over VCC
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
-3
±2
+3
%
16-MHz tolerance overall
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
3.3 V to 3.6 V
-6
±3
+6
%
(1)
This is the frequency change from the measured frequency at 30°C over temperature.
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9.18 Wakeup From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from LPM3
or LPM4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3 or
LPM4 (2)
(1)
(2)
VCC
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
MIN
TYP
3V
MAX
UNIT
1.5
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
9.19 Typical Characteristics, DCO Clock Wakeup Time From LPM3 or LPM4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 16. DCO Wakeup Time From LPM3 vs DCO Frequency
28
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9.20 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
10000
32768
200
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
Oscillator fault frequency,
LF mode (3)
(4)
1.8 V to 3.6 V
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
fFault,LF
MAX
32768
500
LF mode
(3)
TYP
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Duty cycle
(2)
MIN
1.8 V to 3.6 V
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
(1)
VCC
2.2 V
30
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
9.21 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
-40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
-40°C to 85°C
3V
25°C
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
UNIT
kHz
0.5
%/°C
4
%/V
9.22 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
SMCLK, duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
VCC
MIN
TYP
MAX
fSYSTEM
3V
20
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MHz
ns
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9.23 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (1)
3V
2
tτ
UART receive deglitch time (2)
3V
50
(1)
(2)
SMCLK, duty cycle = 50% ± 10%
TYP
MAX
fSYSTEM
UNIT
MHz
MHz
100
600
ns
The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
9.24 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17 and
Figure 18)
PARAMETER
TEST CONDITIONS
VCC
MIN
SMCLK, duty cycle = 50% ± 10%
TYP
MAX
UNIT
fSYSTEM
MHz
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
3V
75
ns
tHD,MI
SOMI input data hold time
3V
0
ns
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, CL = 20 pF
3V
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 17. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 18. SPI Master Mode, CKPH = 1
30
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9.25 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19 and
Figure 20)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
3V
tSTE,LAG
STE lag time, Last clock to STE high
3V
tSTE,ACC
STE access time, STE low to SOMI data out
3V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
3V
50
ns
tSU,SI
SIMO input data setup time
3V
15
ns
tHD,SI
SIMO input data hold time
3V
10
ns
tVALID,SO
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data valid time
3V
tSTE,LEAD
50
UNIT
tSTE,LEAD
ns
10
ns
50
75
ns
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 19. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 20. SPI Slave Mode, CKPH = 1
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9.26 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 21)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
3V
0
TYP
SMCLK, duty cycle = 50% ± 10%
fSCL ≤ 100 kHz
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
3V
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3V
0
tSU,DAT
Data setup time
3V
250
ns
tSU,STO
Setup time for STOP
3V
4.0
µs
tSP
Pulse duration of spikes suppressed
by input filter
3V
50
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STA
tHD,STA
4.7
3V
fSCL > 100 kHz
µs
0.6
µs
0.6
tHD,STA
ns
100
600
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 21. I2C Mode Timing
32
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9.27 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
(2)
ADC10 supply current
TA
(3)
Reference supply current,
reference buffer disabled (4)
All Ax terminals, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 0 (4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 1 (4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax can be selected
at one time
25°C
3V
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
(1)
(2)
(3)
(4)
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied through terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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9.28 10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,REF+
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in reference
analog supply voltage range IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in reference
voltage
ILD,VREF+
Maximum VREF+ load
current
VREF+ load regulation
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 1
VCC
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
TYP
MAX
2.2
3V
UNIT
V
2.9
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
MIN
1.41
1.5
1.59
2.35
2.5
2.65
±1
V
mA
±2
3V
LSB
±2
VREF+ load regulation
response time
IVREF+ = 100 µA → 900 µA,
VAx ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at
pin VREF+
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference
buffer to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
34
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9.29 10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VEREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference
input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF–
(1)
(2)
(3)
(4)
(5)
UNIT
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
ΔVEREF
Static input current into VEREF–
MAX
VCC
VEREF+ > VEREF–
IVEREF–
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VEREF+
MIN
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
VEREF–
IVEREF+
VCC
V
(5)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
9.30 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn-on settling time of
the ADC
(1)
ADC10SR = 1
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
3V
2.6
6.8
3V
1.91
5.00
3V
UNIT
MHz
MHz
µs
13 ×
ADC10DIV ×
1/fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10SSELx ≠ 0
(1)
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
9.31 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
TEST CONDITIONS
3V
±1.1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
3V
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5.1
LSB
Source impedance RS < 100 Ω
VCC
MIN
TYP
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9.32 10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
TEST CONDITIONS
Temperature sensor supply
current (1)
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
TCSENSOR
ADC10ON = 1, INCHx = 0Ah
(2)
60
3V
3.55
tSensor(sample)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≉ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel
11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(2)
(3)
(4)
(5)
TYP
3V
Sample time required if channel
10 is selected (3)
(1)
MIN
MAX
UNIT
µA
mV/°C
30
µs
(4)
1.5
µA
V
1220
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
9.33 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
fFTG
Flash timing generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
257
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
104
Program and erase endurance
tRetention
tWord
tBlock,
0
tBlock, 1-63
tBlock,
End
tMass Erase
tSeg
(1)
(2)
36
Erase
20
MAX
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
ms
105
15
cycles
Data retention duration
TJ = 25°C
Word or byte program time
(2)
years
30
tFTG
Block program time for first byte or word
(2)
25
tFTG
Block program time for each additional byte or
word
(2)
18
tFTG
Block program end-sequence wait time
(2)
6
tFTG
Mass erase time
(2)
10593
tFTG
Segment erase time
(2)
4819
tFTG
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
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9.34 RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
9.35 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
(1)
(2)
TEST CONDITIONS
VCC
MIN
TYP
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
9.36 JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
TA = 25°C
MIN
MAX
UNIT
2.5
6
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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10 I/O Port Schematics
10.1 Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Timer
1
1
2
Direction
0: Input
1: Output
3
From USCI
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Timer
1
0
3
0
1
2
Bus
Keeper
EN
TAx.y
TAxCLK
1
P1.0/TA0CLK/ ACLK/A0
P1.1/TA0.0/
UCA0RXD/UCA0SOMI/A1
P1.2/TA0.1/
UCA0TXD/UCA0SIMO/A2
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
38
Interrupt
Edge
Select
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Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger (continued)
Table 16. Port P1 (P1.0 to P1.2) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.y = 1)
I: 0; O: 1
0
0
0
TA0.TACLK
0
1
0
0
ACLK
1
1
0
0
A0/
A0
X
X
X
1 (y = 0)
Pin Osc
Capacitive sensing
P1.1/
P1.x (I/O)
TA0.0/
TA0.0
P1.0/
P1.x (I/O)
TA0CLK/
ACLK/
0
X
0
1
0
I: 0; O: 1
0
0
0
1
1
0
0
TA0.CCI0A
0
1
0
0
UCA0RXD
from USCI
1
1
0
UCA0SOMI/
UCA0SOMI
from USCI
1
1
0
A1/
A1
X
X
X
1 (y = 1)
Pin Osc
Capacitive sensing
P1.2/
P1.x (I/O)
TA0.1/
TA0.1
UCA0RXD/
1
X
0
1
0
I: 0; O: 1
0
0
0
1
1
0
0
TA0.CCI1A
0
1
0
0
UCA0TXD
from USCI
1
1
0
UCA0SIMO/
UCA0SIMO
from USCI
1
1
0
A2/
A2
X
X
X
1 (y = 2)
Pin Osc
Capacitive sensing
X
0
1
0
UCA0TXD/
(1)
2
X = don't care
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10.2 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2
To ADC10 VREF-
VSS
0
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
PxOUT.y
From ADC10
DVSS
DVCC
0
1
1
0
1
2
Bus
Keeper
EN
3
P1.3/ADC10CLK/
A3/VREF-/VEREF-
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
40
EN
Set
Interrupt
Edge
Select
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Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger (continued)
Table 17. Port P1 (P1.3) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.x = 1)
I: 0; O: 1
0
0
0
P1.3/
P1.x (I/O)
ADC10CLK/
ADC10CLK
1
1
0
0
A3/
A3
X
X
X
1 (y = 3)
VREF-
X
X
X
1
VEREF-/
VEREF-
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
VREF-/
(1)
3
X = don't care
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10.3 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
From/To ADC10 Ref+
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
SMCLK
0
1
from Module
2
3
0
1
Bus
Keeper
EN
1
P1.4/SMCLK/UCB0STE/UCA0CLK/
VREF+/VEREF+/A4/TCK
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
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Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger (continued)
Table 18. Port P1 (P1.4) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.x = 1)
JTAG Mode
I: 0; O: 1
0
0
0
0
P1.4/
P1.x (I/O)
SMCLK/
SMCLK
1
1
0
0
0
UCB0STE/
UCB0STE
from USCI
1
1
0
0
UCA0CLK/
UCA0CLK
from USCI
1
1
0
0
VREF+/
VREF+
X
X
X
1
0
VEREF+/
VEREF+
X
X
X
1
0
A4/
A4
X
X
X
1 (y = 4)
0
TCK/
TCK
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
(1)
4
X = don't care
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10.4 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
PxSEL2.y
PxSEL.y
0
1
DVSS
DVCC
PxOUT.y
0
From Module
1
From Module
3
0
1
1
2
Bus
Keeper
EN
TAx.y
TAxCLK
P1.5/TA0.0/UCB0CLK/
UCA0STE/A5/TMS
P1.6/TA0.1/UCB0SOMI/
UCB0SCL/A6/TDI/TCLK
P1.7/CAOUT/UCB0SIMO/
UCB0SDA/A7/TDO/TDI
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
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Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger (continued)
Table 19. Port P1 (P1.5 to P1.7) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.x = 1)
JTAG Mode
I: 0; O: 1
0
0
0
0
P1.5/
P1.x (I/O)
TA0.0/
TA0.0
1
1
0
0
0
UCB0CLK/
UCB0CLK
from USCI
1
1
0
0
UCA0STE
from USCI
1
1
0
0
UCA0STE/
5
A5/
A5
X
X
X
1 (y = 5)
0
TMS
TMS
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
P1.6/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
TA0.1/
TA0.1
1
1
0
0
0
UCB0SOMI/
UCB0SOMI
from USCI
1
1
0
0
UCB0SCL
from USCI
1
1
0
0
UCB0SCL/
6
A6/
A6
X
X
X
1 (y = 6)
0
TDI/TCLK/
TDI/TCLK
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
UCB0SIMO/
UCB0SIMO
from USCI
1
1
0
0
UCB0SDA/
UCB0SDA
from USCI
1
1
0
0
A7/
7
A7
X
X
X
1 (y = 7)
0
TDO/TDI/
TDO/TDI
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
(1)
X = don't care
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10.5 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
PxSEL2.y
PxSEL.y
PxOUT.y
0
From Timer
1
1
DVSS
0
DVCC
1
1
2
0
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P2.3/TA1.0
P2.4/TA1.2
P2.5/TA1.2
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
46
Interrupt
Edge
Select
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Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger (continued)
Table 20. Port P2 (P2.0 to P2.5) Pin Functions
PIN NAME
(P2.x)
x
FUNCTION
P2.0/
P2.x (I/O)
TA1.0/
Timer1_A3.CCI0A
0
CONTROL BITS / SIGNALS (1)
P2DIR.x
P2SEL.x
P2SEL2.x
I: 0; O: 1
0
0
0
1
0
Timer1_A3.TA0
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.1/
P2.x (I/O)
I: 0; O: 1
0
0
Timer1_A3.CCI1A
0
1
0
Timer1_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.2/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.1/
Timer1_A3.CCI1B
0
1
0
Timer1_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.3/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.0/
Timer1_A3.CCI0B
0
1
0
Timer1_A3.TA0
1
1
0
TA1.1/
1
2
3
Pin Osc
Capacitive sensing
P2.4/
P2.x (I/O)
TA1.2/
Timer1_A3.CCI2A
4
X
0
1
I: 0; O: 1
0
0
0
1
0
Timer1_A3.TA2
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.5/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.2/
Timer1_A3.CCI2B
0
1
0
Timer1_A3.TA2
1
1
0
Capacitive sensing
X
0
1
Pin Osc
(1)
5
X = don't care
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10.6 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6, PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
XIN/P2.6/TA0.1
3
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
48
Interrupt
Edge
Select
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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger (continued)
Table 21. Port P2 (P2.6) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
XIN
XIN
P2.6
P2.x (I/O)
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
0
1
1
0
0
I: 0; O: 1
0
X
0
0
6
TA0.1
Timer0_A3.TA1
1
1
0
0
0
Pin Osc
Capacitive sensing
X
0
X
1
X
(1)
X = don't care
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10.7 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN
LF off
PxSEL.6, PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
from P2.6
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
XOUT/P2.7
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
50
Interrupt
Edge
Select
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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger (continued)
Table 22. Port P2 (P2.7) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS / SIGNALS (1)
x
XOUT/
P2.7/
Pin Osc
(1)
FUNCTION
XOUT
7
P2.x (I/O)
Capacitive sensing
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
1
1
1
0
0
I: 0; O: 1
0
X
0
0
X
0
X
1
X
X = don't care
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
11.1.1.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430
Yes
Yes
2
No
Yes
No
No
No
11.1.1.2 Recommended Hardware Options
11.1.1.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also feature
header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG
programmer and debugger included. The following table shows the compatible target boards and the supported
packages.
Package
Target Board and Programmer Bundle
Target Board Only
28-pin TSSOP (PW)
MSP-FET430U28A
MSP-TS430PW28A
11.1.1.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional
hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools
for details.
11.1.1.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full
list of available tools at www.ti.com/msp430tools.
11.1.1.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
11.1.1.3 Recommended Software Options
11.1.1.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).
11.1.1.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices
delivered in a convenient package. MSP430Ware is available as a component of CCS or as a standalone
package.
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11.1.1.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a
FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.
11.1.1.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
11.1.2 Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three
possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 22 provides a legend for reading the
complete device name for any family member.
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MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
430 MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low Power Microcontroller Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 22. Device Nomenclature
11.2 Documentation Support
11.2.1 Related Documents
The following documents describe the MSP430G2333 device. Copies of these documents are available on the
Internet at www.ti.com.
SLAU144 MSP430x2xx Family User's Guide. Detailed information on the modules and peripherals available in
this device family.
SLAZ427 MSP430G2333 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430G2333 device.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
54
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Community Resources (continued)
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
11.4 Trademarks
MSP430, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2333-Q1
55
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
MSP430G2333IPW0RQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
20
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
G2333Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2014
OTHER QUALIFIED VERSIONS OF MSP430G2333-Q1 :
• Catalog: MSP430G2333
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MSP430G2333IPW0RQ1 TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430G2333IPW0RQ1
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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