IC61LV5128 Document Title 512K x 8 Hight Speed SRAM with 3.3V Revision History Revision No History Draft Date Remark 0A Initial Draft September 11,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 1 IC61LV5128 512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access times: — 8, 10, 12 and 15 ns • High-preformance, lower-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh reguired • TTL compatible inputs and outputs • Single 3.3V ± 10% power supply • Packages available: — 36-pin 400mil SOJ — 44-pin TSOP-2 DESCRIPTION The ICSI IC61LV5128 is a very high-speed, low power, 524,288-word by 8-bit COMS static RAM. The IC61LV5128 is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher preformance and low power consumotion devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. The IC61LV5128 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IC61LV5128 is available in 36-pin, 400mil SOJ and 44-pin TSOP-2 package. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc. 2 Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 IC61LV5128 PIN CONFIGURATION PIN CONFIGURATION 36-Pin SOJ 44-Pin TSOP-2 A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 CE 6 31 OE I/O0 7 30 I/O7 I/O1 8 29 I/O6 Vcc 9 28 GND GND 10 27 Vcc I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE 13 24 A14 A5 14 23 A13 A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A9 18 19 NC PIN DESCRIPTIONS NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC TRUTH TABLE A0-A18 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Not Selected (Power-down) Output Disabled Read Write Vcc Power GND Ground NC No Connection WE CE OE I/O Operation Vcc Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PD Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Value Unit –0.5 to Vcc + 0.5 V –55 to +125 °C –65 to +150 °C 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 3 IC61LV5128 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V –0.3 0.8 V (1) VIL Input LOW Voltage ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –1 –5 1 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –1 –5 1 5 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. — — 300 310 — — 280 290 — — 260 270 — — 240 250 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Com. Ind. — — 55 65 — — 55 65 — — 55 65 — — 55 65 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. — — 10 15 — — 10 15 — — 10 15 — — 10 15 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. 4 Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 IC61LV5128 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Min. Max. -10 Min. Max. -12 Min. Max. -15 Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — 15 — ns tAA Address Access Time — 8 — 10 — 12 — 15 ns tOHA Output Hold Time 3 — 3 — 3 — 3 — ns tACE CE Access Time — 8 — 10 — 12 — 15 ns OE Access Time — 4 — 5 — 6 — 7 ns (2) tHZOE OE to High-Z Output 0 4 — 5 — 6 0 6 ns (2) tLZOE OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZCE(2 CE to High-Z Output 0 4 0 5 0 6 0 6 ns tLZCE(2) CE to Low-Z Output 3 — 3 — 3 — 3 — ns tDOE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%. AC TEST LOADS 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 353 Ω 5 pF Including jig and scope 353 Ω Figure 2. 5 IC61LV5128 AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 IC61LV5128 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter Min. Max. -10 Min. Max. -12 Min. Max. -15 Min. Max. Unit tWC Write Cycle Time 8 — 10 — 12 — 15 — ns tSCE CE to Write End 7 — 8 — 9 — 10 — ns tAW Address Setup Time to Write End 7 — 8 — 9 — 10 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWE WE Pulse Width 7 — 8 — 9 — 10 — ns tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns (2) WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns (2) WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns tHZWE tLZWE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 t HD DATAIN VALID 7 IC61LV5128 WRITE CYCLE NO. 2 (1,2) (WE Controlled, OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 8 Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 IC61LV5128 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed(ns) OrderPartNo. Package 8 IC61LV5128-8T IC61LV5128-8K 10 ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed(ns) OrderPartNo. Package 400mil T SOP-2 400mil SOJ 8 IC61LV5128-8TI IC61LV5128-8KI 400mil T SOP-2 400mil SOJ IC61LV5128-10T IC61LV5128-10K 400mil T SOP-2 400mil SOJ 10 IC61LV5128-10TI IC61LV5128-10KI 400mil T SOP-2 400mil SOJ 12 IC61LV5128-12T IC61LV5128-12K 400mil T SOP-2 400mil SOJ 12 IC61LV5128-12TI IC61LV5128-12KI 400mil T SOP-2 400mil SOJ 15 IC61LV5128-15T IC61LV5128-15K 400mil T SOP-2 400mil SOJ 15 IC61LV5128-15TI IC61LV5128-15KI 400mil T SOP-2 400mil SOJ Integrated Circuit Solution, Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution, Inc. AHSR021-0A 09/11/2001 9