ON NB100LVEP221FA 2.5v/3.3v 1:20 differential hstl/ecl/pecl clock driver Datasheet

NB100LVEP221
2.5V/3.3V1:20 Differential
HSTL/ECL/PECL Clock Driver
The NB100LVEP221 is a low skew 1-to-20 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
single-ended (if the VBB output is used).
The LVEP221 specifically guarantees low output-to-output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50 even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single- ended LVPECL input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 F capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
Single- ended CLK input operation is limited to a VCC ≥ 3.0 V in
LVPECL mode, or VEE ≤ -3.0 V in NECL mode.
•
•
•
•
•
•
•
•
•
•
•
15 ps Typical Output-to-Output Skew
40 ps Typical Device-to- Device Skew
Jitter Less than 2 ps RMS
Maximum Frequency > 1.0 GHz Typical
Thermally Enhanced 52-Lead LQFP
VBB Output
540 ps Typical Propagation Delay
LVPECL and HSTL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = -2.375 V to -3.8 V
Q Output will Default Low with Inputs Open or at VEE
Pin Compatible with Motorola MC100EP221
 Semiconductor Components Industries, LLC, 2003
January, 2003 - Rev. 4
1
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MARKING
DIAGRAM*
NB100
LVEP221
AWLYYWW
52-LEAD LQFP
THERMALLY ENHANCED
CASE 848H
FA SUFFIX
A
WL
YY
WW
52
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, refer to Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
NB100LVEP221FA
LQFP-52
160 Units/Tray
NB100LVEP221FAR2
LQFP-52 1500/Tape & Reel
Publication Order Number:
NB100LVEP221/D
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
VCC0
NB100LVEP221
39
38
37
36
35
34
33
32
31
30
29
28
27
VCC0
40
26
Q12
Q5
41
25
Q12
Q5
42
24
Q13
Q4
43
23
Q13
Q4
44
22
Q14
Q3
45
21
Q14
Q3
46
20
Q15
Q2
47
19
Q15
Q2
48
18
Q16
Q1
49
17
Q16
Q1
50
16
Q17
Q0
51
15
Q17
Q0
52
14
VCC0
10
11
12
13
Q18
CLK1
9
Q18
VBB
8
Q19
7
Q19
6
VEE
5
CLK1
4
CLK0
VCC
3
CLK0
2
CLKSEL
1
VCC0
NB100LVEP221
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 52-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
CLK0*, CLK0**
ECL/PECL Differential Inputs
CLK1*, CLK1**
ECL/PECL or HSTL Differential Inputs
Q0:19, Q0:19
ECL/PECL Differential Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
VBB
Reference Voltage Output
VCC/VCCO
Positive Supply
VEE***
Negative Supply
CLK0
0
CLK0
20
Q0 - Q19
Q0 - Q19
CLK1
20
1
CLK1
VBB
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
CLK_SEL
VCC
VEE
FUNCTION TABLE
CLK_SEL
Active Input
L
H
CLK0, CLK0
CLK1, CLK1
Figure 2. Logic Diagram
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2
NB100LVEP221
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Moisture Sensitivity (Note 1)
Flammability Rating
Level 3
Transistor Count
533 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
(See Application Information)
0 LFPM
500 LFPM
52 LQFP
52 LQFP
35.6
30
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
(See Application Information)
0 LFPM
500 LFPM
52 LQFP
52 LQFP
3.2
6.4
°C/W
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC
VI ≥ VEE
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3)
-40 °C
25°C
85°C
Symbol
IEE
Characteristic
Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
100
125
150
104
130
156
116
145
174
Unit
mA
VOH
Output HIGH Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 4)
555
680
900
555
680
900
555
680
900
mV
VIH
Input HIGH Voltage (Single-Ended) (Note
5)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single-Ended) (Note 5)
555
900
555
900
555
900
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 6)
CLK0/CLK0
CLK1/CLK1
1.2
0.3
2.5
1.6
1.2
0.3
2.5
1.6
1.2
0.3
2.5
1.6
V
V
150
A
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
-150
NOTE:
3.
4.
5.
6.
150
0.5
-150
0.5
-150
A
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is
maintained.
Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V.
All outputs loaded with 50 to VCC - 2.0 V.
Do not use VBB at VCC < 3.0 V.
VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP221
LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
150
104
130
156
116
145
174
mA
VOH
Output HIGH Voltage (Note 8)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 8)
1355
1480
1700
1355
1480
1700
1355
1480
1700
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1700
1355
1700
1355
1700
mV
VBB
Output Reference Voltage (Note 9)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 10)
CLK0/CLK0
CLK1/CLK1
3.3
1.6
1.2
0.3
3.3
1.6
1.2
0.3
3.3
1.6
V
V
150
A
IIH
Input HIGH Current
IIL
Input LOW Current
1875
1.2
0.3
1875
150
CLK
CLK
0.5
-150
1875
150
0.5
-150
A
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V.
8. All outputs loaded with 50 to VCC - 2.0 V.
9. Single-ended input operation is limited VCC ≥ 3.0 V in LVPECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
LVNECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
125
150
104
130
156
116
145
174
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1820
-1600
-1945
-1820
-1600
-1945
-1820
-1600
mV
VIH
Input HIGH Voltage (Single-Ended)
-1 165
-880
-1 165
-880
-1 165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1600
-1945
-1600
-1945
-1600
mV
VBB
Output Reference Voltage (Note 13)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14)
CLK0/CLK0
CLK1/CLK1
0.0
-0.9
V
V
150
A
IIH
Input HIGH Current
IIL
Input LOW Current
-1425
VEE + 1.2
VEE + 0.3
0.0
-0.9
VEE + 1.2
VEE + 0.3
150
CLK
CLK
0.5
-150
0.0
-0.9
-1425
VEE + 1.2
VEE + 0.3
150
0.5
-150
NOTE:
-1425
0.5
-150
A
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All outputs loaded with 50 to VCC-2.0 V.
13. Single-ended input operation is limited VEE ≤ -3.0V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB100LVEP221
HSTL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V
0°C
Symbol
VIH
Min
Characteristic
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Input HIGH Voltage
VIL
CLK1/CLK1
Vx+100
1600
Vx+100
1600
Vx+100
1600
mV
CLK1/CLK1
-300
Vx-100
-300
Vx-100
-300
Vx-100
mV
Input LOW Voltage
VX
Differential Configuration Cross
Point Voltage
680
900
680
900
680
900
mV
IIH
Input HIGH Current
-150
150
-150
150
-150
150
A
IIL
Input LOW Current
NOTE:
CLK1
CLK1
-150
-250
-150
-250
A
-150
-250
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 to -3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 15)
-40 °C
Symbol
VOpp
tPLH/tPHL
Characteristic
Differential Output Voltage
(Figure 3)
fout < 50 MHz
fout < 0.8 GHz
fout < 1.0 GHz
Min
Typ
550
550
500
700
700
700
25°C
Max
Min
Typ
600
550
500
700
700
700
85°C
Max
Min
Typ
600
500
400
700
700
600
Max
Unit
mV
mV
mV
Propagation Delay (Differential Configuration)
CLK0-Qx
CLK1-Qx
540
590
600
640
540
590
660
710
540
590
750
800
ps
ps
tskew
Within-Device Skew (Note 16)
Device-to-Device Skew (Note 17)
15
40
50
200
15
40
50
200
15
40
50
200
ps
ps
tJITTER
Random Clock Jitter (RMS) (Figure 3)
1
2
1
2
1
2
ps
VPP
Input Swing (Differential Configuration)
(Note 18) (Figure 4)
CLK0
CLK1 HSTL
400
300
800
800
1200
1000
400
300
800
800
1200
1000
400
300
800
800
1200
1000
mV
mV
DCO
Output Duty Cycle
49.5
50
50.5
49.5
50
50.5
49.5
50
50.5
%
tr/tf
Output Rise/Fall Time (20%-80%)
100
200
300
100
200
300
150
250
350
ps
15. Measured with 750 mV source (LVPECL) or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to VCC-2 V.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions, outputs and VCC levels.
18. VPP is the differential configuration input voltage swing required to maintain AC characteristics.
900
10
9
800
700
7
6
600
5
500
4
tJITTER ps (RMS)
VOPP (mV)
8
3
400
2
300
1
200
0
0.1
0.2
0.4
0.6
0.8
1.0
fIN, INPUT FREQUENCY (GHz)
Figure 3. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC - VEE = 3.3 V @ 25C)
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NB100LVEP221
VCC(LVPECL)
VIH(DIFF)
VPP
VIHCMR
VPP
VCCO(HSTL)
VIH(DIFF)
VX
VIL(DIFF)
VIL(DIFF)
VEE
VEE
Figure 4. LVPECL Differential Input Levels
Figure 5. HSTL Differential Input Levels
Q
D
Driver
Device
Receiver
Device
Q
D
50 50 VTT
VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405
-
ECL Clock Distribution Techniques
AND8002
-
Marking and Date Codes
AND8009
-
ECLinPS Plus Spice I/O Model Kit
AND8020
-
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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NB100LVEP221
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
NB100LVEP221
The NB100LVEP221 uses a thermally enhanced 52-lead
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP221 high-speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the package and electrical performance of the
NB100LVEP221. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
The recommended thermal land design for
NB100LVEP221 applications on multi-layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 7 providing an efficient heat removal path.
supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 8, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 8. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
All Units mm
0.2
1.0
1.0
4.6
0.2
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
Figure 8. Recommended Solder Mask Openings
All Units mm
Proper thermal management is critical for reliable system
operation. This is especially true for high-fanout and high
output drive capability products.
For thermal system analysis and junction temperature
calculation, the thermal resistance parameters of the
package are provided:
4.6
Table 1. Thermal Resistance *
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
LFPM
JA C/W
JC C/W
0
35.6
3.2
100
32.8
4.9
500
30.0
6.4
* Junction to ambient and Junction to board, four-conductor
layer test board (2S2P) per JESD 51-8
These recommendations are to be used as a guideline,
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP221 package is electrically shorted to the
substrate of the integrated circuit and VEE. The thermal land
should be electrically connected to VEE.
Exposed Pad
Land Pattern
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with
1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
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NB100LVEP221
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD PACKAGE
CASE 848H-01
ISSUE A
4 PL
M
M/2
-Z-
0.20 (0.008) T X−Y Z
AJ AJ
52
40
39
1
PLATING
-X-
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
AA
-Y-
L
B
J
AB
B/2
L/2
D
REF
13
27
0.08 (0.003)
26
14
M
Y T−U
DETAIL AJ-AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MM.
3. DATUM PLANE E" IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING PLANE.
4. DATUM X", Y" AND Z" TO BE DETERMINED AT
DATUM PLANE DATUM E".
5. DIMENSIONS M AND L TO BE DETERMINED AT
BASE
SEATING PLANE DATUM T".
METAL
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLAND E".
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM D DIMENSION
BY MORE THAN 0.08 (0.003). DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
Z
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).
A/2
0.20 (0.008) E X−Y Z
A
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
V
W
AA
AB
AC
AD
AE
DETAIL AH
-E-T-
AG
G
SEATING
PLANE
AG
48 PL
D
0.10 (0.004) T
52 PL
0.08 (0.003)
M
T X−Y
V
Z
0.05 (0.002)
R
S
AC
AD
EXPOSED PAD
14
26
S
C
27
13
W
N
K
P
F
H
AE
DETAIL AH
39
1
52
40
VIEW AG-AG
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8
0.25
GAGE
PLANE
MILLIMETERS
MIN
MAX
10.00 BSC
10.00 BSC
1.30
1.50
0.22
0.40
0.45
0.75
0.65 BSC
1.00 REF
0.09
0.20
0.05
0.20
12.00 BSC
12.00 BSC
0.20 REF
0
7
0
−−−
−−−
1.70
12 REF
12 REF
0.20
0.35
0.07
0.16
0.08
0.20
4.58
4.78
4.58
4.78
INCHES
MIN
MAX
0.394 BSC
0.394 BSC
0.051
0.059
0.009
0.016
0.018
0.030
0.026 BSC
0.039 BSC
0.004
0.008
0.002
0.008
0.472 BSC
0.472 BSC
0.008 REF
0
7
0
−−−
−−−
0.067
12 REF
12 REF
0.008
0.014
0.003
0.006
0.003
0.008
0.180
0.188
0.180
0.188
NB100LVEP221
Notes
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9
NB100LVEP221
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10
NB100LVEP221/D
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