AD ADF4106BRU-REEL Pll frequency synthesizer Datasheet

PLL Frequency Synthesizer
ADF4106
Data Sheet
FEATURES
GENERAL DESCRIPTION
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
14
R COUNTER
LATCH
CLK
DATA
LE
24-BIT INPUT
REGISTER
SDOUT
FUNCTION
LATCH
22
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
HIGH Z
19
AVDD
MUXOUT
MUX
13
N = BP + A
RFINA
RFINB
LOCK
DETECT
13-BIT
B COUNTER
SDOUT
LOAD
PRESCALER
P/P + 1
LOAD
M3 M2 M1
6-BIT
A COUNTER
02720-001
ADF4106
6
CE
AGND
DGND
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2001–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF4106
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Phase Frequency Detector (PFD) and Charge Pump............ 11
Timing Characterisitics ............................................................... 4
MUXOUT and Lock Detect...................................................... 11
Absolute Maximum Ratings............................................................ 6
Input Shift Register .................................................................... 11
ESD Caution .................................................................................. 6
The Function Latch .................................................................... 17
Pin Configurations and Function Descriptions ........................... 7
The Initialization Latch ............................................................. 18
Typical Performance Characteristics ............................................. 8
Applications..................................................................................... 19
General Description ....................................................................... 10
Local Oscillator for LMDS Base Station Transmitter ............ 19
Reference Input Section ............................................................. 10
Interfacing ................................................................................... 20
RF Input Stage ............................................................................. 10
PCB Design Guidelines for Chip Scale Package .................... 20
Prescaler (P/P +1)....................................................................... 10
Outline Dimensions ....................................................................... 21
A Counter and B Counter ......................................................... 10
Ordering Guide .......................................................................... 22
R Counter .................................................................................... 10
REVISION HISTORY
11/12—Rev. D to Rev. E
Changed EVAL-ADF4106EBZ1 to EV-ADF4106SD1Z ...... Universal
Added RFINA to RFINB Parameter, Table 3 .................................... 6
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/11—Rev. C to Rev. D
Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter,
Table 1 ................................................................................................ 4
Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 12,
Table 1 ................................................................................................ 4
Changes to Ordering Guide .......................................................... 22
2/10—Rev. B to Rev. C
Changes to Figure 4 and Table 4 ..................................................... 6
Changes to Figure 12 ........................................................................ 8
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
6/05—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Figure 1 ...........................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................5
Changes to Figure 3 and Figure 4 ....................................................6
Changes to Figure 6 ...........................................................................7
Changes to Figure 10.........................................................................7
Deleted TPC 13 and TPC 14 ............................................................8
Changes to Figure 15.........................................................................8
Changes to Figure 20 Caption ...................................................... 10
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
5/03—Rev. 0 to Rev. A
Edits to Specifications .......................................................................2
Edits to TPC 11 ..................................................................................7
Updated Outline Dimensions ....................................................... 19
10/01—Revision 0: Initial Revision
Rev. E | Page 2 of 24
Data Sheet
ADF4106
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency6
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD7 (AIDD + DIDD)
IDD8 (AIDD + DIDD)
IDD9 (AIDD + DIDD)
IP
Power-Down Mode10
(AIDD + DIDD)
B Version1
B Chips2 (typ)
Unit
0.5/6.0
0.5/6.0
GHz min/max
–10/0
300
–10/0
300
dBm min/max
MHz max
P=8
325
325
MHz max
P = 16
20/300
0.8/VDD
10
±100
20/300
0.8/VDD
10
±100
MHz min/max
V p-p min/max
pF max
μA max
For f < 20 MHz, ensure SR > 50 V/μs
Biased at AVDD/2 (see Note 55)
104
104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
Programmable, see Table 9
5
625
2.5
3.0/11
2
2
5
625
2.5
3.0/11
2
2
mA typ
μA typ
% typ
kΩ typ
nA max
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Table 9
1 nA typical; TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
1.5
2
1.5
2
% typ
% typ
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
1.4
0.6
±1
10
1.4
0.6
±1
10
V min
V max
μA max
pF max
1.4
1.4
V min
VDD − 0.4
100
0.4
VDD − 0.4
100
0.4
V min
μA max
V max
2.7/3.3
AVDD
AVDD/5.5
11
11.5
13
0.4
10
2.7/3.3
AVDD
AVDD/5.5
9.0
9.5
10.5
0.4
10
V min/V max
V min/V max
mA max
mA max
mA max
mA max
μA typ
Rev. E | Page 3 of 24
Test Conditions/Comments
See Figure 18 for input circuit
For lower frequencies, ensure
slew rate (SR) > 320 V/μs
Open-drain output chosen, 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
IOL = 500 μA
AVDD ≤ VP ≤ 5.5V
9.0 mA typ
9.5 mA typ
10.5 mA typ
TA = 25°C
ADF4106
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)11
Normalized 1/f Noise (PN1_f)12
Phase Noise Performance13
900 MHz14
5800 MHz15
5800 MHz16
Spurious Signals
900 MHz14
5800 MHz15
5800 MHz16
Data Sheet
B Version1
B Chips2 (typ)
Unit
Test Conditions/Comments
–223
–223
dBc/Hz typ
−122
−122
dBc/Hz typ
–92.5
−76.5
−83.5
−92.5
−76.5
−83.5
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
PLL loop B/W = 500 kHz, measured at 100 kHz
offset
10 kHz offset; normalized to 1 GHz
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
–90/–92
–65/–70
–70/–75
–90/–92
–65/–70
–70/–75
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
1
Operating temperature range (B Version) is –40°C to +85°C.
The B chip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4
AVDD = DVDD = 3 V.
5
AC coupling ensures AVDD/2 bias.
6
Guaranteed by design. Sample tested to ensure compliance.
7
TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
8
TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
9
TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
10
TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
11
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
12
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
13
The phase noise is measured with the EV-ADF4106SD1Z evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
14
fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
15
fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.
16
fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.
2
3
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
1
Limit1 (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Operating temperature range (B Version) is –40°C to +85°C.
Rev. E | Page 4 of 24
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
Data Sheet
ADF4106
t3
t4
CLOCK
t1
DATA
DB23 (MSB)
t2
DB22
DB2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
02720-002
t5
LE
Figure 2. Timing Diagram
Rev. E | Page 5 of 2
ADF4106
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND 1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
–0.3 V to + 3.6 V
–0.3 V to + 0.3 V
–0.3 V to + 5.8 V
–0.3 V to + 5.8 V
–0.3 V to VDD + 0.3 V
–0.3 V to VP + 0.3 V
–0.3 V to VDD + 0.3 V
±320 mV
–40°C to +85°C
–65°C to +125°C
150°C
112°C/W
30.4°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
260°C
40 sec
6425
303
GND = AGND = DGND = 0 V.
1
Rev. E | Page 6 of 24
Data Sheet
ADF4106
VP
16
CP 2
15
DVDD
3
14
MUXOUT
TOP VIEW 13 LE
(Not to Scale)
12 DATA
RFINA 6
11
CLK
AVDD 7
10
CE
REFIN 8
9
DGND
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
PIN 1
INDICATOR
ADF4106
TOP VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
AVDD 6
AVDD 7
REFIN 8
DGND 9
DGND 10
RFINB 5
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
02720-003
AGND 4
ADF4106
Figure 3. 16-Lead TSSOP Pin Configuration
02720-004
RSET 1
CPGND
20 CP
19 RSET
18 VP
17 DVDD
16 DVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
1
Pin No.
LFCSP
19
Mnemonic
RSET
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
6
7
5
6, 7
RFINA
AVDD
8
8
REFIN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DVDD
16
18
VP
EP
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
I CP MAX =
R SET
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. E | Page 7 of 24
ADF4106
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–40
FREQ UNIT
GHz KEYWORD
R
PARAM TYPE
S
IMPEDANCE 50Ω
DATA FORMAT MA
FREQ MAGS11 ANGS11
3.300
0.42777
–102.748
3.400
0.42859
–107.167
–111.883
0.43365
3.500
–117.548
3.600
0.43849
3.700
0.44475
–123.856
3.800
0.44800
–130.399
3.900
0.45223
–136.744
4.000
0.45555
–142.766
4.100
0.45313
–149.269
4.200
0.45622
–154.884
4.300
0.45555
–159.680
4.400
0.46108
–164.916
0.45325
–168.452
4.500
–173.462
4.600
0.45054
4.700
0.45200
–176.697
4.800
0.45043
178.824
4.900
0.45282
174.947
5.000
0.44287
170.237
5.100
0.44909
166.617
5.200
0.44294
162.786
5.300
0.44558
158.766
5.400
0.45417
153.195
0.46038
147.721
5.500
0.47128
139.760
5.600
5.700
0.47439
132.657
5.800
0.48604
125.782
5.900
0.50637
121.110
6.000
0.52172
115.400
–60
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER
Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)
Figure 5. S-Parameter Data for the RF Input
0
0
REF LEVEL = –14.0dBm
VDD = 3V
VP = 3V
–10
–5
–20
OUTPUT POWER (dB)
RF INPUT POWER (dBm)
02720-008
ANGS11
–17.2820
– 20.6919
– 24.5386
–27.3228
–31.0698
– 34.8623
–38.5574
–41.9093
– 45.6990
–49.4185
–52.8898
–56.2923
–60.2584
–63.1446
–65.6464
–68.0742
–71.3530
–75.5658
–79.6404
–82.8246
–85.2795
–85.6298
–86.1854
–86.4997
–88.8080
–91.9737
–95.4087
–99.1282
OUTPUT POWER (dB)
MAGS11
0.89148
0.88133
0.87152
0.85855
0.84911
0.83512
0.82374
0.80871
0.79176
0.77205
0.75696
0.74234
0.72239
0.69419
0.67288
0.66227
0.64758
0.62454
0.59466
0.55932
0.52256
0.48754
0.46411
0.45776
0.44859
0.44588
0.43810
0.43269
02720-005
FREQ
0.500
0.600
0.700
0.800
0.900
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
10dB/DIV
RL = –40dBc/Hz
RMS NOISE = 0.36°
–50
–10
–15
–20
–30
–40
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–50
–60
–70
TA = +85°C
–91.0dBc/Hz
TA = –40°C
–30
0
1
4
2
3
RF INPUT FREQUENCY (GHz)
–90
02720-006
TA = +25°C
5
–100
–400kHz
6
–200kHz
900MHz
FREQUENCY
200kHz
400kHz
Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)
Figure 6. Input Sensitivity
0
0
–10
–20
–30
–40
REF LEVEL = –10dBm
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–10
–20
OUTPUT POWER (dB)
REF LEVEL = –14.3dBm
–50
–60
–93.0dBc/Hz
–70
–30
–40
–50
–60
–70
–80
02720-007
–80
–90
–100
–2kHz
–1kHz
900MHz
FREQUENCY
1kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–83.5dBc/Hz
02720-010
OUTPUT POWER (dB)
02720-009
–80
–25
–90
–100
–2kHz
2kHz
–1kHz
5800MHz
FREQUENCY
1kHz
2kHz
Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)
Rev. E | Page 8 of 24
Data Sheet
ADF4106
–5
–40
10dB/DIV
RL = –40dBc/Hz
RMS NOISE = 1.8°
–70
–80
–90
–100
–110
02720-011
–120
–130
–25
–35
–45
–55
–65
–75
–85
02720-014
PHASE NOISE (dBc/Hz)
–60
–140
100Hz
VDD = 3V
VP = 5V
–15
FIRST REFERENCE SPUR (dBc)
–50
–95
–105
0
1MHz
1
2
3
TUNNING VOLTAGE (V)
FREQUENCY OFFSET FROM 5800MHz CARRIER
Figure 14. Reference Spurs vs. VTUNE (5.8 GHz,1 MHz, and 100 kHz)
Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
–120
0
–30
–40
VDD = 3V
VP = 5V
–130
–50
–65.0dBc
–66.0dBc
–70
–80
–140
–150
–160
02720-012
–170
–90
–100
–2M
–1M
5800
1M
02720-015
OUTPUT POWER (dB)
–20
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
PHASE NOISE (dBc/Hz)
REF LEVEL = –10dBm
–10
–60
–180
10k
2M
100k
1M
10M
PHASE ETECTOR FREQUENCY (Hz)
FREQUENCY (Hz)
100M
Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency
Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)
–6
–60
VDD = 3V
VP = 3V
–5
–4
VPP = 5V
ICP SETTLING = 5mA
–3
–70
–2
ICP (mA)
PHASE NOISE (dBc/Hz)
5
4
–80
–1
0
1
2
–90
3
–20
0
20
40
TEMPERATURE (°C)
60
80
02720-016
–100
–40
02720-013
4
5
6
100
0
Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature
Rev. E | Page 9 of 24
0.5
1.0
1.5
2.0
2.5
3.0
VCP (V)
3.5
4.0
4.5
Figure 16. Charge Pump Output Characteristics
5.0
ADF4106
Data Sheet
GENERAL DESCRIPTION
REFERENCE INPUT SECTION
A COUNTER AND B COUNTER
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REFIN pin on power-down.
The A counter and B CMOS counter combine with the dual
modulus prescaler to allow a wide ranging division ratio in the
PLL feedback counter. The counters are specified to work when
the prescaler output is 325 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
POWER-DOWN
CONTROL
Pulse Swallow Function
NC
100k
SW2
REFIN
TO R COUNTER
NC
BUFFER
NO
02720-017
SW1
SW3
Figure 17. Reference Input Stage
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500


f
fVCO  P  B   A  REFIN
R
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
RF INPUT STAGE
BIAS
GENERATOR
The A counter and B counter, in conjunction with the dualmodulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is
P is the preset modulus of the dual-modulus prescaler
(8/9, 16/17, etc.).
B is the preset divide ratio of the binary 13-bit counter
(3 to 8191).
1.6V
AVDD
A is the preset divide ratio of the binary 6-bit swallow
counter (0 to 63).
500
fREFIN is the external reference frequency oscillator.
RFINA
N = BP + A
RFINB
13-BIT B
COUNTER
PRESCALER
P/P + 1
MODULUS
CONTROL
Figure 18. RF Input Stage
PRESCALER (P/P +1)
LOAD
LOAD
6-BIT A
COUNTER
N DIVIDER
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A counter and
B counter. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value, and is given by (P2 − P).
Figure 19. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
Rev. E | Page 10 of 24
02720-019
02720-018
AGND
FROM RF
INPUT STAGE
TO PFD
Data Sheet
ADF4106
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the
phase and frequency difference between them. Figure 20 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the reference counter latch, ABP2 and ABP1, control the
width of the pulse. See Table 7.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock is detected, this output is high with narrow, lowgoing pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
MUX
CONTROL
MUXOUT
N COUNTER OUTPUT
VP
SDOUT
CHARGE
PUMP
D1
Q1
UP
U1
DGND
R DIVIDER
CLR1
Figure 21. MUXOUT Circuit
PROGRAMMABLE
DELAY
ABP2
HI
02720-021
HI
INPUT SHIFT REGISTER
U3
CP
ABP1
CLR2 DOWN
D2 Q2
02720-020
U2
N DIVIDER
CPGND
Figure 20. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4106 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
The ADF4106 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Table 6 shows a summary of how
the latches are programmed.
Table 5. C1, C2 Truth Table
Control Bits
C2
C1
0
0
0
1
1
0
1
1
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector cycles is less than
15 ns. With LDP set to 1, five consecutive cycles of less than
15 ns are required to set the lock detect. It stays set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
Rev. E | Page 11 of 24
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
ADF4106
Data Sheet
Table 6. Latch Summary
LOCK
DETECT
PRECISION
REFERENCE COUNTER LATCH
RESERVED
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
X
0
0
LDP
T2
T1
CONTROL
BITS
14-BIT REFERENCE COUNTER
ABP2 ABP1
R14
R13
R12
R11
R10
R9
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R8
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
RESERVED
CP GAIN
N COUNTER LATCH
13-BIT B COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
X
X
G1
B13
B12
B11
B10
B9
B8
B7
B6
CONTROL
BITS
6-BIT A COUNTER
B5
B4
B3
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
A6
A5
A4
A3
A2
A1
C2 (0) C1 (1)
CONTROL
BITS
DB1
DB0
FASTLOCK
ENABLE
CP THREESTATE
PD
POLARITY
POWERDOWN 1
COUNTER
RESET
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
MUXOUT
CONTROL
PRESCALER
VALUE
P2
P1
POWERDOWN 2
FASTLOCK
MODE
FUNCTION LATCH
PD2
CURRENT
SETTING
2
CPI6
CPI5
CPI4
CURRENT
SETTING
1
CPI3
CPI2
CPI1
TIMER COUNTER
CONTROL
TC4
TC3
TC2
TC1
F5
MUXOUT
CONTROL
DB1
DB0
CP THREESTATE
PD
POLARITY
POWERDOWN 1
COUNTER
RESET
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
F3
F2
M3
M2
M1
PD1
F1
P1
PD2
CPI6
CPI5
CPI4
CURRENT
SETTING
1
CPI3
CPI2
CPI1
TIMER COUNTER
CONTROL
TC4
TC3
TC2
TC1
F5
Rev. E | Page 12 of 24
F4
DB0
C2 (1) C1 (1)
02720-022
P2
CURRENT
SETTING
2
FASTLOCK
MODE
CONTROL
BITS
PRESCALER
VALUE
POWERDOWN 2
FASTLOCK
ENABLE
INITIALIZATION LATCH
Data Sheet
ADF4106
LOCK
DETECT
PRECISION
Table 7. Reference Counter Latch Map
RESERVED
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
X
0
0
LDP
T2
T1
ABP2 ABP1
CONTROL
BITS
14-BIT REFERENCE COUNTER
R14
R13
R12
R11
R10
R9
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R8
R7
R6
R5
R4
R3
R2
R1
C2 (0)
C1 (0)
X = DON’T CARE
ABP2
0
0
1
1
ABP1
0
1
0
1
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
0
.
.
.
0
0
0
0
.
.
.
0
0
0
0
.
.
.
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
0
1
1
0
.
.
.
1
0
1
0
.
.
.
1
2
3
4
.
.
.
16380
1
1
1
..........
1
0
0
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
ANTIBACKLASH PULSE WIDTH
2.9ns
1.3ns
6.0ns
2.9ns
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
LDP
0
1
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
02720-023
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
Rev. E | Page 13 of 24
ADF4106
Data Sheet
CP GAIN
Table 8. N (A, B) Counter Latch Map
RESERVED
CONTROL
BITS
6-BIT A COUNTER
13-BIT B COUNTER
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
X
X
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
DB1
DB0
C2 (0) C1 (1)
X = DON’T CARE
B13
B12
B11
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
A6
A5
..........
A2
A1
A COUNTER
DIVIDE RATIO
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
60
61
62
63
B3
B2
B1
B COUNTER DIVIDE RATIO
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
OPERATION
0
0
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
0
1
1
0
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
1
1
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
02720-024
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N × FREF), AT THE
OUTPUT, NMIN IS (P2 – P).
Rev. E | Page 14 of 24
Data Sheet
ADF4106
FASTLOCK
ENABLE
CP THREESTATE
PD
POLARITY
POΩERDOΩN 1
COUNTER
RESET
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
POΩERDOΩN 2
FASTLOCK
MODE
Table 9. Function Latch Map
PRESCALER
VALUE
P1
PD2
CPI6
CPI5
CPI4
CPI2
CPI3
TIMER COUNTER
CONTROL
CPI1
TC4
TC3
TC2
TC1
TC4
TC3
TC2
TC1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3kΩ
1.06
2.12
3.18
4.24
5.30
6.36
7.42
8.50
5.1kΩ
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
CPI6
CPI5
CPI4
CPI3
0
0
0
0
1
1
1
1
CPI2
0
0
1
1
0
0
1
1
CPI1
0
1
0
1
0
1
0
1
PD2
PD1
MODE
X
X
0
1
X
0
1
1
ASYNCHRONOUS POΩER-DOΩN
NORMAL OPERATION
ASYNCHRONOUS POΩER-DOΩN
SYNCHRONOUS POΩER-DOΩN
P1
PRESCALER VALUE
0
1
0
1
8/9
16/17
32/33
64/65
PHASE DETECTOR
POLARITY
F1
0
1
NEGATIVE
POSITIVE
0
1
F3
CHARGE PUMP
OUTPUT
0
1
NORMAL
THREE-STATE
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
DB1
DB0
C2 (1) C1 (0)
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
11kΩ
0.289
0.580
0.870
1.160
1.450
1.730
2.020
2.320
CE PIN
0
0
1
1
F2
CONTROL
BITS
ICP (mA)
0
1
1
1
P2
F5
MUXOUT
CONTROL
02720-025
P2
CURRENT
SETTING
1
CURRENT
SETTING
2
Rev. E | Page 15 of 24
ADF4106
Data Sheet
FASTLOCK
ENABLE
CP THREESTATE
PD
POLARITY
POΩERDOΩN 1
COUNTER
RESET
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
POΩERDOΩN 2
FASTLOCK
MODE
Table 10. Initialization Latch Map
PRESCALER
VALUE
P1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
TIMER COUNTER
CONTROL
CPI1
TC4
TC3
TC2
TC1
TC4
TC3
TC2
TC1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3kΩ
1.06
2.12
3.18
4.24
5.30
6.36
7.42
8.50
5.1kΩ
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
CPI6
CPI5
CPI4
CPI3
0
0
0
0
1
1
1
1
CPI2
0
0
1
1
0
0
1
1
CPI1
0
1
0
1
0
1
0
1
PD2
PD1
MODE
X
X
0
1
X
0
1
1
ASYNCHRONOUS POΩER-DOΩN
NORMAL OPERATION
ASYNCHRONOUS POΩER-DOΩN
SYNCHRONOUS POΩER-DOΩN
P1
PRESCALER VALUE
0
1
0
1
8/9
16/17
32/33
64/65
PHASE DETECTOR
POLARITY
F1
0
1
NEGATIVE
POSITIVE
0
1
F3
CHARGE PUMP
OUTPUT
0
1
NORMAL
THREE-STATE
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
DB1
DB0
C2 (1) C1 (1)
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
11kΩ
0.289
0.580
0.870
1.160
1.450
1.730
2.020
2.320
CE PIN
0
0
1
1
F2
CONTROL
BITS
ICP (mA)
0
1
1
1
P2
F5
MUXOUT
CONTROL
02720-026
P2
CURRENT
SETTING
1
CURRENT
SETTING
2
Rev. E | Page 16 of 24
Data Sheet
ADF4106
THE FUNCTION LATCH
Fastlock Mode Bit
With C2 and C1 set to 1 and 0, respectively, the on-chip
function latch is programmed. Table 9 shows the input data
format for programming the function latch.
DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the N (A, B) counter are reset. For normal operation, this
bit should be 0. When powering up, disable the F1 bit (set to 0).
The N counter will then resume counting in close alignment
with the R counter. (The maximum error is one prescaler cycle).
Power-Down
DB3 (PD1) and DB21 (PD2) provide programmable powerdown modes. They are enabled by the CE pin.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fastlock
when 0 is written to the CP gain bit in the N (A, B) counter
latch.
Fastlock Mode 2
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device
powers down immediately after latching 1 into the PD1 bit,
with the condition that PD2 is loaded with 0.
In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing 1
into the PD1 bit (provided that 1 has also been loaded to PD2),
then the device goes into power-down during the next charge
pump event.
When a power-down is activated (either synchronous or
asynchronous mode, including CE pin activated power-down),
the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load state
conditions.
The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fastlock
under the control of the timer counter. After the timeout
period, which is determined by the value in TC4 to TC1, the CP
gain bit in the N (A, B) counter latch is automatically reset to 0,
and the device reverts to normal mode instead of fastlock. See
Table 9 for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is used when the system is dynamic and in a state of
change (that is, when a new output frequency is programmed).
The normal sequence of events follows.
The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be
2.5 mA as Current Setting 1 and 5 mA as the Current Setting 2.
Simultaneously, the decision must be made as to how long the
secondary current stays active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 to DB11 (TC4 to TC1), in the function latch. The truth
table is given in Table 9.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RFIN input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4106 family. Table 9 shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. When this
bit is 1, fastlock is enabled.
To program a new output frequency, simply program the N (A,
B) counter latch with new values for A and B. Simultaneously,
the CP gain bit can be set to 1, which sets the charge pump with
the value in CPI6 to CPI4 for a period of time determined by
TC4 to TC1. When this time is up, the charge pump current
reverts to the value set by CPI3 to CPI1. At the same time, the
CP gain bit in the N (A, B) counter latch is reset to 0 and is now
ready for the next time the user wishes to change the frequency.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
Rev. E | Page 17 of 24
ADF4106
Data Sheet
Charge Pump Currents
• Do an N (A, B) load (01 in two LSBs).
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table 9.
When the initialization latch is loaded, the following occurs:
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 325 MHz. Therefore,
with an RF frequency of 4 GHz, a prescaler value of 16/17 is
valid, but a value of 8/9 is not valid.
PD Polarity
This bit sets the phase detector polarity bit. See Table 9.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
THE INITIALIZATION LATCH
When C2 and C1 = 1 and 1, respectively, the initialization latch
is programmed. This is essentially the same as the function
latch (programmed when C2 and C1 = 1 and 0, respectively).
However, when the initialization latch is programmed, there is
an additional internal reset pulse applied to the R and N (A, B)
counters. This pulse ensures that the N (A, B) counter is at the
load point when the N (A, B) counter data is latched and the
device begins counting in close phase alignment.
If the latch is programmed for synchronous power-down (CE
pin is high, PD1 bit is high, and PD2 bit is low), the internal
pulse also triggers this power-down. The prescaler reference
and the oscillator input buffer are unaffected by the internal
reset pulse; therefore, close phase alignment is maintained when
counting resumes.
When the first N (A, B) counter data is latched after
initialization, the internal reset pulse is again activated.
However, successive N (A, B) counter loads after this will not
trigger the internal reset pulse.
Device Programming After Initial Power-Up
After initial power up of the device, there are three methods for
programming the device: initialization latch, CE pin, and
counter reset.
Initialization Latch Method
• Apply VDD.
• Program the initialization latch (11 in two LSBs of input
word). Make sure that the F1 bit is programmed to 0.
• Do a function latch load (10 in two LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
• Do an R load (00 in two LSBs).
• The function latch contents are loaded.
• An internal pulse resets the R, N (A, B), and timeout counters
to load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.
• Latching the first N (A, B) counter data after the initialization
word activates the same internal reset pulse. Successive N (A,
B) loads will not trigger the internal reset pulse, unless there
is another initialization.
CE PIN METHOD
• Apply VDD.
• Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
• Program the function latch (10).
• Program the R counter latch (00).
• Program the N (A, B) counter latch (01).
• Bring CE high to take the device out of power-down. The R
and N (A, B) counters now resume counting in close
alignment.
Note that after CE goes high, a 1 µs duration may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it is programmed at least once after VDD is initially
applied.
COUNTER RESET METHOD
• Apply VDD.
• Do a function latch load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
• Do an R counter load (00 in two LSBs).
• Do an N (A, B) counter load (01 in two LSBs).
• Do a function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump but does not trigger
synchronous power-down.
Rev. E | Page 18 of 24
Data Sheet
ADF4106
APPLICATIONS
LOCAL OSCILLATOR FOR LMDS BASE STATION
TRANSMITTER
Loop Bandwidth = 50 kHz
Figure 22 shows the ADF4106 being used with a VCO to
produce the LO for an LMDS base station.
N = 5800
FPFD = 1 MHz
Extra Reference Spur Attenuation = 10 dB
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 Ω termination.
These specifications are needed and used to derive the loop
filter component values shown in Figure 22.
The circuit in Figure 22 shows a typical phase noise
performance of −83.5 dBc/Hz at 1 kHz offset from the carrier.
Spurs are better than −62 dBc.
To achieve a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the
on-chip reference divider of the ADF4106.
The loop filter output drives the VCO, which in turn is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for
the system would be 45°.
In a PLL system, it is important to know when the system
is in lock. In Figure 22, this is accomplished by using the
MUXOUT signal from the synthesizer. The MUXOUT pin
can be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.
Other PLL system specifications include:
KD = 2.5 mA
KV = 80 MHz/V
VDD
VP
RFOUT
100pF
7
1000pF
FREFIN
16
15
AVDD DVDD VP
1000pF
CP 2
8 REFIN
2
100pF
51Ω
4.3kΩ
100pF
14
6.2kΩ
20pF
VCC
18Ω
18Ω
10
V956ME03
18Ω
ADF4106
CE
MUXOUT 14
CLK
DATA
LE
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
LOCK
DETECT
100pF
RFINA 6
51Ω
RFINB 5
DGND
3
4
9
100pF
NOTE
DECOUPLING CAPACITORS (0.1µF/10pF) ON AVDD, DVDD, AND
VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
02720-027
5.1kΩ
RSET
AGND
1
CPGND
SPI®-COMPATIBLE SERIAL BUS
1.5nF
Figure 22. Local Oscillator for LMDS Base Station
Rev. E | Page 19 of 24
ADF4106
Data Sheet
INTERFACING
ADSP2181 Interface
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits clocked into the input
register on each rising edge of CLK are transferred to the
appropriate latch. See Figure 2 for the timing diagram and
Table 5 for the latch truth table.
Figure 24 shows the interface between the ADF4106 and the
ADSP21xx digital signal processor (DSP). The ADF4106
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate for the device is 833 kHz,
or one update every 1.2 µs. This is certainly more than adequate
for systems that have typical lock times in hundreds of
microseconds.
ADuC812 Interface
SCLOCK
Figure 23 shows the interface between the ADF4106 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
is written, the LE input should be brought high to complete
the transfer.
MOSI
ADSP-21xx
Figure 24. ADSP-21xx-to-ADF4106 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the LFCSP (CP-20) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the LFCSP has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with 1 oz. copper to plug the via.
CLK
DATA
LE
ADF4106
The user should connect the PCB thermal pad to AGND.
CE
MUXOUT
(LOCK DETECT)
02720-028
I/O PORTS
ADF4106
Figure 23. ADuC812-to-ADF4106 Interface
Rev. E | Page 20 of 24
02720-029
MUXOUT
(LOCK DETECT)
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that
the maximum rate at which the output frequency can be
changed is 166 kHz.
ADuC812
LE
I/O FLAGS
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
MOSI
DATA
CE
On first applying power to the ADF4106, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
SCLOCK
TFS
CLK
Data Sheet
ADF4106
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.60 MAX
0.60 MAX
15
PIN 1
INDICATOR
20
16
1
PIN 1
INDICATOR
3.75
BCS SQ
0.50
BSC
2.25
2.10 SQ
1.95
EXPOSED
PAD
5
10
1.00
0.85
0.80
SEATING
PLANE
12° MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
6
11
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
Rev. E | Page 21 of 24
0.25 MIN
04-09-2012-B
TOP VIEW
0.75
0.60
0.50
ADF4106
Data Sheet
ORDERING GUIDE
Model 1
ADF4106BRU
ADF4106BRU-REEL
ADF4106BRU-REEL7
ADF4106BRUZ
ADF4106BRUZ-RL
ADF4106BRUZ-R7
ADF4106BCPZ
ADF4106BCPZ-RL
ADF4106BCPZ-R7
EV-ADF4106SD1Z
EV-ADF411XSD1Z
1
Temperature Range
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
Package Description
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Evaluation Board
Z = RoHS Compliant.
Rev. E | Page 22 of 24
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
CP-20-1
CP-20-1
CP-20-1
Data Sheet
ADF4106
NOTES
Rev. E | Page 23 of 24
ADF4106
Data Sheet
NOTES
©2001–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02720-0-11/12(E)
Rev. E | Page 24 of 24