a FEATURES Full Function Monolithic LVDT-to-Digital Converter Absolute Serial Data Output Uncommitted Differential Input Repeatability Remote Diagnostics 14-Bit Resolution Industrial Temperature Range 28-Pin PLCC Low Power APPLICATIONS Industrial Gauging Industrial Process Control Linear Positioning Systems Linear Actuator Control Automotive Motion Sensing and Control Torque Sensing Conditioner AC Strain Gages Conditioning Avionics Low Cost LVDT-to-Digital Converter AD2S93 FUNCTIONAL BLOCK DIAGRAM C3 The AD2S93 is a complete 14-bit resolution tracking LVDT-todigital converter. A Type II tracking loop is employed to track the A–B input and produce a digital output equal to (A–B)/ (REF/2), where REF is a fixed amplitude ac reference phase coherent with the A–B input. This allows the measurement of any 2-, 3-, 4- and 5-wire LVDT or linear amplitude modulated input. The operating frequency range is from 360 Hz to 10 kHz with user definable bandwidth set externally within a range of 45 Hz to 1250 Hz. The AD2S93 has a 16-bit serial output. The MSB (LOS), read first, indicates a loss of the signal A, B, or reference inputs to the converter or transducer. The second and third MSBs are flags indicating whether [–REF/2 (UNR) ≤ A–B ≤ +REF/2 (OVR]) is outside the linear operating range of the converter. The displacement data is presented as 13-bit offset binary giving a ± 12bit operating range. LOS, OVR and UNR are pinned out on the device, in addition a NULL flag is available which is set when (A–B) = 0. Absolute displacement information is accessed when CS is taken LO followed by the application of an external clock (SCLK) with a maximum rate of 2 MHz. Data is read MSB first. When CS is high the DATA output is high impedance; this allows daisy chaining of more than one converter onto a common bus. R6 ERROR AMP REF AC RATIO BRIDGE DIFFERENTIAL (SECONDARY A VOLTAGE) B R4 GAIN VDD LOS OVR UNR DEMODIN PHASE SENSITIVE DEMODULATOR DEMOD OUT R1 DIFF R3 FREQUENCY SHAPING LOS DECODE LOGIC UP-DOWN COUNTER VCO CS DATA R7 INTIN C1 R2 C2 VEL VCO GAIN DIR NULL SCLK GENERAL DESCRIPTION ACERROR REFERENCE (PRIMARY EXCITATION) C4 R5 CLKOUT LATCHES SERIAL INTERFACE AD2S93 DIFF output is the resultant A–B. The AD2S93 operates using ± 5 V ± 5% power supplies and is fabricated on Analog Devices’ linear compatible CMOS process (LC2MOS). The (LC2MOS) is a mixed technology process that combines precision bipolar circuits with low power logic. PRODUCT HIGHLIGHTS Complete LVDT-to-Digital Interface. The AD2S93 provides the complete solution for digitizing LVDT signals to 14bit resolution. Serial 16-Bit Output Data. One 16-bit read from the AD2S93 determines input signal continuity (LOS), over and underrange detection and 13 bits of offset binary displacement information. High Accuracy Grade in Low Cost Package. 0.05% and 0.1% integral linearity over the full –40°C to +85°C operating temperature range. Uncommitted Differential Input. Allows configuration of 2-, 3-, 4- and 5-wire LVDTs. Multiple Converter Interfacing. High impedance data output and a simple three-wire interface reduces cabling and eliminates bus contention. Low Power. 70 mW power consumption (typ). The A, B differential input allows the user to scale the A, B inputs between 1 and 10. This enables the user to accurately set up the inputs matching the REF input to the DIFF output. The REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 V ± 5%; V = –5 V ± 5%, AGND = DGND = 0 V, T = –40°C to +85°C noted) AD2S93–SPECIFICATIONS (Vunless= +5otherwise DD Parameter SIGNAL INPUTS Frequency Max Voltage Level1 Nominal Full Scale2 Input Bias Current Input Impedance CMRR Maximum Sensitivity3 REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance Permissible Phase Shift4 CONVERTER DYNAMICS Bandwidth VCO Mode = 1 VCO Mode = 2 Maximum Slew Rate Mode = 1 Mode = 2 ACCURACY Integral Linearity Differential Linearity Repeatability Zero Position Offset SS Test Conditions A Min Typ Max Units 0.36 0.8 1.0 1.0 1.0 10 1.2 kHz V rms V rms µA MΩ dB µV pk/LSB @ +25°C 1.1 1.0 57 342 VA–B = 1 V rms, G = 1 0.36 1.8 Signal to Reference –10 +10 kHz V rms µA MΩ Degrees Set by User VCO Gain Connected to VCO I/P VCO Gain No Connect 500 45 1250 500 Hz Hz 3000 1000 LSB/ms LSB/ms 0.1 0.05 <2 <1 ±1 3 1 4 2 ± 0.7 % FSD % FSD LSB LSB LSB LSB LSB LSB LSB % FS ± 4.0 ± 250 V dc µA 1.5 500 V dc V dc nA pF 2.0 @ 0 V +25°C 1.0 2400 800 AP BP AP BP AP @ +25°C BP @ +25°C AP @ –40°C to +85°C BP @ –40°C to +85°C –3 –1 –4 –2 Gain Error VELOCITY OUTPUT Max Output Voltage Load Drive Capability Denotes Max Input Speed LOGIC INPUTS SCLK, CS Input High Voltage VINH Input Low Voltage VINL Input Current IIN Input Capacitance LOGIC OUTPUTS OVR, UNR, NULL, DATA, A, B CLKOUT DIR Output High Voltage Output Low Voltage LOS OUTPUT 10 2.2 1 3.5 10 @ 1 mA @ 1 mA 4.0 Open Drain Output Pull-Up to +VDD via 12 kΩ Drive Capability Signal Threshold (A-B) REF Threshold Timeout Threshold 0.1 1.0 V dc V dc 400 µA 0.2 V rms V rms ms 0.22 50 –2– REV. A AD2S93 Parameter Test Conditions SERIAL CLOCK (SCLK) SCK Input Rate Maximum Read Rate (16 Bits) Continuous POWER SUPPLY IDD ISS Min Typ 5 5 7 7 Max Units 2 9.2 MHz µs 10 10 mA mA NOTES 1 The signal input voltage maximum should always be set at 10% less than the reference input. 2 Nominal + FS = V A–B = VREF/2, FS = –VA–B = VREF/2 3 With G = 10; Sensitivity 34.2 µV pk/LSB 4 Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.” Specifications subject to change without notice. TIMING CHARACTERISTICS (VDD = +5 V ± 5%, AGND = DGND = 0 V, TA = –40°C to +85°C unless otherwise noted) Parameter AD2S93 Units Test Conditions t1 1 t2 t3 t4 t5 t6 t7 150 600 250 250 100 600 150 ns max ns min ns min ns min ns max ns min ns max CS to DATA Enable CS to 1st SCLK Positive Edge SCLK High Pulse SCLK Low Pulse SCLK Positive Edge to DATA Valid CS High Pulse Width CS High to DATA High Z (Bus Relinquish) NOTE 1 SCLK can only be applied after t 2 has elapsed. t6 t2 CS t3 SCLK t4 t* MSB DATA LSB t1 t7 t5 t * = THE MINIMUM ACCESS TIME: USER DEPENDENT TOTAL MAX READ TIME = t2 + 16. (t3 + t4 ) + t7 TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns TOTAL MAX READ TIME = 600 + 8000 + 150 ns TOTAL MAX READ TIME = 8.750 µs (SINGLE READ ONLY) Timing Diagram REV. A –3– AD2S93 RECOMMENDED OPERATING CONDITIONS PIN DESIGNATIONS Power Supply Voltage (VDD–VSS) . . . . . . . . . . . ± 5 V dc ± 5% Analog Input Voltage (A, B) . . . . . . . . . . . . . . 1 V rms ± 10% Analog Reference Input (REF) . . . . . . . . . . . . 2 V rms ± 10% Signal and Reference Harmonic Distortion . . . . . . . . . . . <10% Operating Temperature Range Industrial (AP, BP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C VDD to AGND . . . . . . . . . . . . . . . . . . . –0.3 V dc to + 7.0 V dc VSS to AGND . . . . . . . . . . . . . . . . . . . +0.3 V dc to – 7.0 V dc AGND to DGND . . . . . . . . . . . . –0.3 V dc to VDD + 0.3 V dc Analog Inputs to AGND REF . . . . VSS – 0.3 V to VDD + 0.3 V A, B . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Analog Output to AGND VEL . . . . . . . . . . . . . . . . VSS to VDD Digital Inputs to DGND CS, SCLK . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Outputs to DGND NULL, DIR, CLKOUT, DATA . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . +300°C Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . +100 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C 1 28 27 26 B A 2 NC DIFF GAIN 3 AGND LOS Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 DATA 5 25 NC SCLK 6 24 REF CS 7 AD2S93 NC 8 UNR 9 TOP VIEW (Not to Scale) 23 VEL 22 INTIN 21 VCOGAIN CLKOUT 10 20 ACERROR NC 11 19 DEMODIN DEMODOUT VSS VDD DGND DIR OVR NULL 12 13 14 15 16 17 18 NC = NO CONNECT ORDERING GUIDE Model Temperature Range Linearity Package Option AD2S93AP AD2S93BP –40°C to +85°C –40°C to +85°C 0.1% 0.05% P-28A P-28A Mnemonic 1 2 3 AGND DIFF GAIN Description Analog Ground. Output of Signal Input Preamplifier. Connect GAIN Pin to DIFF for nominal × 1. Gains greater than 1 can be resistively scaled. Do not leave unconnected. 4 LOS Denotes A or B lines loss of connection and/or loss of reference to transducer or converter. 5 DATA 16-bit serial data output 13 bits of absolute position information plus overrange and underrange plus LOS. 6 SCLK Serial Clock. Maximum rate = 2 MHz. CS Chip Select. Loads serial interface 7 with current positional information and enable output. 9, 12 UNR, OVR Two pins that denote whether the input signals are underrange or overrange. 10 CLKOUT Updates every LSB. 13 NULL Denotes Null Position. 14 DIR Indicates direction. DIR is HI for positive displacement and LO for negative displacement. 15 DGND Digital Ground. Negative Power Supply –5.0 V dc 16 VSS ± 5%. 17 VDD Positive Power Supply +5.0 V dc ± 5%. 18 DEMODOUT Output of the Phase Sensitive Demodulator. 19 DEMODIN Input to Phase Sensitive Demodulator. 20 ACERROR AC Error Output. 21 VCO GAIN Sets the VCO gain internally. Connect to VEL for 2400 LSB/s. Disconnect for 800 LSB/s. 22 INTIN Determines system dynamics connect C and RC (serial) parallel combination across INTIN and VEL to determine loop dynamics. 23 VEL Analog Velocity Output. 24 REF Single ended input for fixed amplitude reference. 27, 28 B, A Uncommitted differential inputs for the A, B signal inputs. ABSOLUTE MAXIMUM RATINGS* * Pin No. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S93 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD2S93 Because the conversion depends on the ratio of the input signals (ratiometric ac bridge), the AD2S93 is remarkably tolerant of input amplitude and frequency. This, combined with the definable Type 2 tracking closed-loop guarantees the AD2S93's repeatability for a given input. A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null the output of the ACERROR. When this is accomplished the word state of the up/down counter equals within the rated accuracy of the converter, the LVDT position output. GLOSSARY OF TERMS INTEGRAL LINEARITY Integral linearity deviation as a percent of full scale. A 0.1% deviation is equivalent to 8-LSB change on the output. Gain The converter gain is the maximum variation in the ratio of A–B/REF/2 to the maximum digital input. Output Offset The output offset is the digital output code when the analog input signal A–B = 0. For more information on the operation of the converter, see “Circuit Dynamics” section. Overrange (OVR) OVR goes high when A–B is in phase with REF and larger than REF/2. DATA FORMAT OPERATING RANGE Underrange (UNR) The AD2S93 operating range is defined in Figure 2. The linearity and specified operating range of the converter is the central two 12-bit quadrants through zero. The corresponding input relationship is –REF/2 ≤ A–B ≤ +REF/2, (± is used to denote phase coherency). The sign bit is low for inputs with A–B in phase with REF. The two remaining 12-bit quadrants are used to denote over (OVR) and underrange (UNR). OVR goes high when A–B is in phase with REF and larger than REF/2. UNR goes high when A–B is out of phase with REF and larger than REF/2. LOS is an open drain output which pulls high when A and/or B are removed or REF is removed (see “Inbuilt Diagnostics”), or A + B is less than 100 mV. UNR goes high when A–B is out of phase with REF and larger than REF/2. PRINCIPLE OF OPERATION The AD2S93 is based on a Type 2 tracking closed-loop principle. The output tracks the position of the LVDT without the need for external convert and wait states. As the transducer moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB. On the AD2S93, CLKOUT updates corresponding to one LSB increment. Figure 1 illustrates the principle of operation. C3 ACERROR REFERENCE (PRIMARY EXCITATION) R6 ERROR AMP REF AC RATIO BRIDGE DIFFERENTIAL (SECONDARY A VOLTAGE) B R4 GAIN R3 LOS OVR UNR DECODE LOGIC UP-DOWN COUNTER DEMOD OUT VCO DATA SCLK R7 INTIN C1 ±FSR = R2 C2 VEL VCO GAIN DIR NULL CS In order to match the LVDT output to the AD2S93 output, the inputs to the AD2S93 need to be scaled. The operating range is illustrated in Figure 2. The AD2S93 operates across ± 12-bit range where the remaining 12-bit quadrants are used to denote overrange and underrange. The output position word is a function of the ratio between A–B and VREF (see Figure 2) where: PHASE SENSITIVE DEMODULATOR FREQUENCY SHAPING LOS SCALING THE INPUTS DEMODIN R1 DIFF VDD C4 R5 CLKOUT LATCHES SERIAL INTERFACE AD2S93 Figure 1. Functional Block Diagram REV. A –5– (A − B) VREF /2 AD2S93 OUTPUT CODES MAGNITUDE 0100 0000 0000 0000 0100 0100 0000 1111 0000 0000 1111 0000 0000 1111 0000 0001 0000 0001 0001 1111 0000 0000 1111 0000 0000 1111 0000 0001 0001 0001 0011 0011 1111 1111 0000 0000 1111 1111 0000 0000 1110 1111 0000 0001 +VE POSITION FULL SCALE A AA A – B = + REF/2 A–B=0 NULL POSITION A – B = – REF/2 –VE POSITION FULL SCALE A UNDERRANGE LOS 0011 1111 1111 1111 OVR UNR SIGN AA OVERRANGE RANGE –1 0 ≠1 RATIO OF A- B/REF/2 Figure 2. Output Code Format If the maximum operating stroke of an LVDT yielded a 1 V rms A–B output, the weighting of the LVDT to AD2S93 digital output would be: A B GAIN Input Signal Full Scale R4 Full-Scale Operating Range (± 212 ) R3 AGND DIFF 1× 2 2 213 Input Scaling = 345 µV/LSB This can be equated directly to the LVDT sensitivity specification in mm/v/v. Note: The overrange and underrange quadrants can be utilized by decoding the overrange and underrange MSBs and decoding the 12 magnitude bits. This will increase the operating range of the AD2S93 accordingly. However, if the input A–B > VREF then the converter will lose track of the input and will only regain track when the input signal returns to within the operating range of the converter. Figure 3. Pre-Amp Gain Block SETTING THE CONVERTER BANDWIDTH The AD2S93 bandwidth is set by placing three external components, C1, C2, and R2, around the integrator as illustrated by the figure below. C1 R2 THI INPUT GAIN Since the transformation ratio of an LVDT or RVDT from excitation voltage to signal voltage can be 1:0.15, provision for gain scaling has been provided. The gain can, therefore, be selected to ensure that the full-scale output of converter represents the maximum stroke position of the transducer. The gain setting is accomplished by connecting Pin 2, (DIFF) and Pin 3 (GAIN) together (unity gain) or connecting two resistors as shown in Figure 3. R1 CV C2 RV INT VCO 62.5 THO Figure 4. Integrator and VCO Before the bandwidth can be set, the corresponding VCO gain setting must be determined. The VCO gain is directly related to the slew rate of the converter. This is set internally to two different rates defined internally by RV. Typical converter slew rates are defined below, The gain of the input stage is calculated using the following equation: R DIFF ( A – B) = 1+ 3 ( A – B) IN R4 G (1) = 2400 LSB/ms–Mode 1 G (2) = 800 LSB/ms–Mode 2 e.g., For a gain of 5, R3 = 12 kΩ, R4 = 3 kΩ For a gain of 10, R3 = 18 kΩ, R4 = 2 kΩ –6– REV. A AD2S93 Calculation of the component values for the bandwidth is detailed below. For more detailed information on component value selection for the AD2S93, please consult the “Passive Component Selection and Dynamic Modeling Software for the AD2S93 LVDT-to-Digital Converter.” IN-BUILT DIAGNOSTICS The first three bits read from the serial interface preceding the sign and magnitude data can be used to determine whether the data is valid or not. Over and underrange (OVR, UNR) denote the two extremes of the LVDT stroke where linearity of the LVDT may degrade. Loss of signal LOS is an open drain output which pulls high (12 kΩ pull up) when one of the following conditions is satisfied: VCO Gain G (1) Mode 1 The available bandwidth with this option is from 0.5 kHz to 1.25 kHz. 1. A and/or B is disconnected. 2. REF is disconnected. FREF > 8 × Fo C1 = 1/(800 × Fo2) C2 = 8 × C1 R2 = 45 × Fo Note: LOS has a response time of 50 ms max to the conditions stated above, see “Specifications.” Where FREF is the reference frequency, Fo is the closed-loop 3 dB point. CONNECTING THE CONVERTER Positive power supply VDD = +5 V dc ± 5% should be connected to Pin 17 and negative power supply VSS = –5 V dc ± 5% to Pin 16. Reversal of these power supplies will destroy this device. For LVDT connections to the converter please refer to Figures 5 through 7. On all connections, the maximum input reference signal VREF = 2.0 V rms ± 10%. To operate within the standard operating range, A–B should not exceed 1.0 V rms ± 10%. The AD2S93 AGND point is the point at which all analog signal grounds should be connected. Ground returns from the LVDT should be connected to AGND. The AD2S93 DGND pin should be connected to the AD2S93 AGND pin. Ancillary Digital circuitry must be connected to the Star Point and not to the AD2S93 AGND pin. VCO Gain G (2) Mode 2 The available bandwidth with this option is from 45 Hz to 500 Hz. FREF > 8 × Fo C1 = 1/(2400 × Fo2) C2 = 8 C1 R2 = 45 × Fo Where FREF is the reference frequency, Fo is the closed-loop 3 dB point. INTERFACING TO THE AD2S93 (SEE “TIMING CHARACTERISTICS”) In all cases, the AD2S93 has been configured with the following dynamics. The absolute position information is extracted via a three-wire interface, DATA, CS and SCLK. The DATA output is held in a high impedance state when CS is high. Reference Frequency 3 dB Bandwidth Upon the application of logic low to the CS pin, the DATA is enabled and the current position information is transferred from the counters to the serial interface. Data is retrieved by applying an external clock to the SCLK pin. The maximum data rate of the SCLK is 2 MHz. To ensure secure data retrieval, it is important to note that SCLK should not be applied until a minimum period of 600 ns after the application of logic low to CS. Data is then clocked out on successive positive edges of SCLK: 16 clock edges are required to extract the entire data word. Subsequent positive edges greater than the defined resolution of the converter will clock zeros from the data output if CS remains in a low state. The format of the data read is shown in Table I. Vco Gain is set in MODE 1 where VCO GAIN is connected to VEL. Using the procedure described in “setting the converter bandwidth” the following preferred values (E12 series) were calculated: C1 = 3.3 nF C2 = 27 nF R2 = 27 kΩ CALCULATING HF FILTER (C3, C4, R5, R6) 15 kΩ ≤ R5 = R6 ≤ 56 kΩ Table I. Function DB0 DB1 DB2 DB3 DATA DB4–D15 MSB LSB LOS OVR UNR SIGN MAGNITUDE C 3 = C4 = 1 2π R5 F REF So, C3 = 1 nF, R5 = R6 = 33 kΩ, C4 = 1 nF and in all cases R7 = 15 kΩ. If less than the full 16-bit word is required, then the data read can be terminated by releasing CS after the required number of bits have been read. Half-Bridge Type LVDT Connection In this method of connection, it is necessary to add two additional bridge completion resistors RC and RC, in order to derive a reference for the AD2S93. In selecting the bridge completion resistor, it is important to remember that mismatch between RC1 and RC2 will cause nonzero errors at null. If two LVDTs are being used for differential measurements, the resistors can be replaced by the second LVDT. CS can be released a minimum of 100 ns after the last positive edge. If the user is reading data continuously, CS can be reapplied after a minimum of 600 ns after it is released. The minimum repetitive read time of the same converter is given by (16 bits read @ 2 MHz). Min RD Time = [600 + (16 × 500) + 600] = 9.2 µs. REV. A 5 kHz 625 Hz –7– AD2S93 Three- or Four-Wire LVDT Connection linearity in the output. It is up to the user to determine if (A + B) is sufficiently constant over the particular stroke length employed. In this method of connection, shown in Figure 6, the converters digital output is proportional to the ratio: This method will usually restrict the usable LVDT range to half of its full range. The restriction can be eliminated, however, by attenuating DIFF by a factor of 2 or increasing VREF by a factor of 2. This connection method has the tremendous advantage of being insensitive to temperature related phase shifts and excitation oscillator instability effects usually associated with more conventional LVDT conversion systems. (A − B) (A + B) / 2 where A and B are the individual LVDT secondary output voltages. Inspection of Figure 6 should demonstrate why this relationship is true. (A–B) is simply the voltage across the series connected secondaries of the LVDT and is applied to the A, B input to the converter. (A + B)/2 is effectively the average of the two secondary voltages as computed by the balanced bridge completion resistors and the grounding of the secondary center-tap. As in the case of the half-bridge type LVDT connection, RC1 and RC2 are the bridge completion resistors and are matched to a degree sufficient to ensure that the digital output representing the null position does not vary from the LVDT’s natural null position. If null adjustment is required, a potentiometer can be used in place of the common connection between the two resistors. Note: This method of connection is appropriate only for where (A + B) is a constant, independent of LVDT position. Any lack of constancy in (A + B) will be reflected as an additional non- C1 C4 C2 C3 R2 R6 R5 REF 25 24 23 22 21 19 20 R7 NC 26 16 VSS 0V –5V TOP VIEW (Not to Scale) 28 AGND 1 15 DGND DIFF 2 14 DIR GAIN 12kΩ LOS 3 13 NULL 4 12 OVR R3 R4 B AD2S93 A GND A +5V B PISTON RC2 17 V DD VDD 11 CLKOUT UNR NC = NO CONNECT NC 10 9 8 CS DATA 7 NC 6 5 SCLK RC1 DEMODOUT 18 27 Figure 5. Half-Bridge Type LVDT Connection C1 C4 C2 C3 R2 R6 R5 REF 25 24 RC2 20 19 R7 NC 26 18 B 27 17 DEMODOUT V DD A 28 AD2S93 16 VSS AGND 1 15 DGND DIFF 2 TOP VIEW (Not to Scale) GAIN 12kΩ LOS 3 13 NULL 4 12 OVR RC1 R3 R4 +5V 0V –5V 14 DIR VDD 11 NC 10 CLKOUT 9 UNR 8 NC 7 CS 6 SCLK 5 DATA PISTON 23 22 21 NC = NO CONNECT Figure 6. Three- or Four-Wire LVDT Connection –8– REV. A AD2S93 Two-Wire LVDT Connection REMOTE MULTIPLE SENSOR INTERFACING This method should be used in cases where the sum of the LVDT secondary output voltages (A + B) is not constant with LVDT displacement over the desired stroke length. This method of connection, shown in Figure 7, still maintains the ratiometric operation and the insensitivity to variations in reference amplitude and frequency. However, the phase shift between VREF and V1 should be minimized to maintain accuracy (see Section “PHASE SHIFT AND QUADRATURE EFFECTS”). Suggested phase compensation circuits are shown in Figure 7. The DATA output of the AD2S93 is held in a high impedance state until CS is taken LO. This allows a user to operate the AD2S93 in an application with more than one converter connected on the same line. Figure 8 shows four LVDTs interfaced to four AD2S93s. Excitation for the LVDT is provided locally by an oscillator. SCLK, DATA and two address lines are fed down low loss cables suitable for communication links. The two address lines are decoded locally into CS for the individual converters. Data is received and transmitted using transmitters and receivers. PHASE SHIFT AND QUADRATURE EFFECTS Reference to signal phase shift can be high in LVDTs, sometimes in the order of 70 degrees. If the converter is connected as in Figures 5 and 6, any effects due to this phase shift are minimized. This connection method, therefore, provides outstanding benefits. 4 4 4 LVDT 2 When the phase shift between VREF and V1 is zero, additional quadrature on the signal will have no effect on the converter. This is another benefit of the conversion method. For example, when a REF lags (A–B) by approximately 10°, the gain error is approximately 1%. When (A–B) lags REF by approximately 10°, the gain error is approximately 2%. SCLK DATA AD2S93 4 LVDT θ = phase shift between VREF and DIFF. A1 AD2S93 3 4 where CS1 CS2 CS3 CS4 AD2S93 2 LVDT (1 – cos θ) × 100% of FSR A0 AD2S93 1 LVDT The additional gain error caused by reference to signal phase shifts is given by: 2-4 DECODING (74HC139) 2 VDD VSS OSC 0V BUFFER Figure 8. Remote Sensor Interface C1 C4 C2 C3 R2 R6 R5 REF 25 24 PHASE SHIFT CCT 23 22 20 19 TOP VIEW (Not to Scale) 15 DGND 2 14 DIR GAIN 3 13 NULL LOS 4 12 OVR PHASE LAG = ARCTAN 2 π fRC 5 6 7 R 8 9 10 11 NC 1 DIFF CLKOUT AGND NC 16 UNR R –5V AD2S93 AD2S93 CS C 1 2π fRC VSS 28 SCLK PHASE LEAD = ARCTAN VDD +5V A DATA PISTON DEMODOUT 27 12kΩ 17 V DD B R3 R4 R7 18 NC 26 OSC C Figure 7. Two-Wire LVDT Connection REV. A 21 –9– NC = NO CONNECT 0V AD2S93 CIRCUIT DYNAMICS/ERROR SOURCES TRANSFER FUNCTION The AD2S93 operates as a Type 2 tracking servo loop. An integrator and VCO/counter perform the two integrations inherent in a Type 2 loop. The overall system response of the AD2S93 is that of a unity gain second order low-pass filter, with the position of the LVDT as the input and the digital position data as the output. Figure 9 illustrates the AD2S93 system diagram. The AD2S93’s design has been optimized with a critically damped response. The closed-loop transfer function is given by: θOUT = θ IN θOUT 1 + st1 K K (1 + st1 ) = 12 2 1 + st2 θ IN s2 s3t2 s 1 + st1 + + K1K 2 K1K 2 The normalized gain and phase diagrams are given in Figures 10 and 11 with a bandwidth of 1.25 kHz. VEL OUT IN 5 OUT + G1 (s) G2 (s) 0 –5 Figure 9. AD2S93 Transfer Function –10 Note: The AD2S93 has been configured with the following dynamics. –15 Reference Frequency 3 dB Bandwidth –20 10 kHz 1250 Hz –25 –30 VCO Gain is set in MODE 1 where VCOGAIN is connected to VEL. –35 Using the procedure described in “SETTING THE CONVERTER BANDWIDTH,” the following preferred values (E12 series) were calculated: –40 –45 1 10 100 1k 10k FREQUENCY – Hz C1 = 820 pF C2 = 6.8 nF R2 = 56 kΩ Figure 10. AD2S93 Gain Plot 0 C3 = C4 = 470 pF, R7 = 15 kΩ, R5 = R6 = 33 kΩ, C4 = 470 pF –20 The open-loop transfer function is given by: –40 –60 G1(s) = K1 s 1+ st1 1+ st2 –80 –100 G2(s) = K2 s –120 –140 where: –160 –180 C × C2 t2 = R2 1 C1 + C2 t 1 = R 2 C2 1 10 100 1k 10k FREQUENCY – Hz Figure 11. AD2S93 Phase Plot and: 4 ×10 −3 1 = 160 × 10 −9 × = 21 C1 + C2 25 ×10 3 4 K2 = RV × CV K1 = Note A2 has two values depending on which mode is being used K2 (MODE1) = 640 × 103 K2 (MODE2) = 160 × 103 The AD2S93 acceleration constant is given by: Ka = K1 × K2 Therefore in the example given, Ka = K1 × K2 = 21 × 640 × 103 = 13.44 × 106 s–2 –10– REV. A AD2S93 The small step response is given in Figure 12, and is the time taken for the converter to settled to within 1 LSB. SOURCES OF ERROR ACCELERATION ERROR ts = 7 ms (14-bit resolution) The large step response (steps >5% of FSR) applies when the error voltage will exceed the linear range of the converter. Typically it will take three times longer to reach the first peak FSR. In response to a velocity step [VELOUT/(dθ/dt)] the velocity output will exhibit the same response characteristics as outlined above. 2%FS A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant Ka of the converter. Ka = input acceleration position The numerator and denominator’s units must be consistent. Ka does not define maximum input acceleration, only the error due to its acceleration. The maximum acceleration allowable before the converter loses track is dependent on the positional accuracy requirement of the system. POSITION Position Error × Ka = LSB/sec2 Ka can be used to predict the output position error for a given input acceleration. The AD2S93 in the example has a Ka = 13.44 × 106 sec-2 if we apply an input accelerating at 100 × 214 LSB/sec2. [ 0 input acceleration LSB/sec 2 Error in LSBs = 0 4 8 12 16 ] 20 = Figure 12. Small Step Response REV. A [ K a sec -2 –11– 100 × 214 13.44 × 106 = 0.12 LSBs ] OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 0.050 (1.27) BSC 0.025 (0.63) 0.015 (0.38) 26 PIN 1 IDENTIFIER 5 0.180 (4.57) 0.165 (4.19) 25 0.021 (0.53) 0.013 (0.33) C1881–28–1/94 P-28A 0.430 (10.92) 0.390 (9.91) TOP VIEW 0.032 (0.81) 0.026 (0.66) 19 11 12 18 0.040 (1.01) 0.025 (0.64) 0.456 (11.58) 0.450 (11.43) SQ 0.495 (12.57) 0.485 (12.32) SQ 0.110 (2.79) 0.085 (2.16) PRINTED IN U.S.A. 0.020 (0.50) R –12–