ADVANCED LINEAR DEVICES, INC. ALD2724E/ALD2724 DUAL EPAD® PRECISION HIGH SLEW RATE CMOS OPERATIONAL AMPLIFIER KEY FEATURES BENEFITS • • • • • • • Ready to use off the shelf standard part • Custom automated trimming optional • Remote controlled automated trimming • In-System Programming capable • No external components • No internal clocking noise source • Simple and cost effective • Small package size • Extremely small total functional volume size • Low system implementation cost Factory pre-trimmed VOS VOS = 25µV @ IOS = 0.01pA 5 V / µs slew rate EPAD ( Electrically Programmable Analog Device) Rail-to-rail input/output Each amplifier VOS can be user trimmed to a different Vos level (optional) • System level “calibration” capable GENERAL DESCRIPTION The ALD2724E/ALD2724 is a dual monolithic operational amplifier with MOSFET input that has rail-to-rail input and output voltage ranges. The input voltage range and output voltage range are very close to the positive and negative power supply voltages. Typically the input voltage can be beyond positive power supply voltage V+ or the negative power supply voltage V- by up to 300mV. The output voltage swings to within 60mV of either positive or negative power supply voltages at rated load. With high impedance load, the output voltage of the ALD2724E/ALD2724 approaches within 1mV of the power supply rails. This device is designed as an alternative to the popular J-FET input operational amplifier in applications where lower operating voltages, such as 9V battery or ±3.25V to ±5V power supplies are being used. The ALD2724E/ALD2724 offers high slew rate of 5.0V/µs. The rail-to-rail input and output feature of the ALD2724E/ALD2724 expands signal voltage range for a given operating supply voltage and allows numerous analog serial stages to be implemented without losing operating voltage margin. The output stage is designed to drive up to 10mA into 400pF capacitive and 1.5KΩ resistive loads at unity gain and up to 4000pF at a gain of 5. Short circuit protection to either ground or the power supply rails is at approximately 15mA clamp current. Due to complementary output stage design, the output can source and sink 10mA into a load with symmetrical drive and is ideally suited for applications where push-pull voltage drive is desired. For each of the operational amplifier, the offset voltage is trimmed on-chip to eliminate the need for external nulling in many applications. For precision applications, the output is designed to settle to 0.1% in 2µs. In large signal buffer applications, the operational amplifier can function as APPLICATIONS • • • • • • • • • • • • • • Sensor interface circuits Transducer biasing circuits Capacitive and charge integration circuits Biochemical probe interface Signal conditioning Portable instruments High source impedance electrode amplifiers Precision Sample and Hold amplifiers Precision current to voltage converter Error correction circuits Sensor compensation circuits Precision gain amplifiers Periodic In-system calibration System output level shifter PIN CONFIGURATION -IN A 1 14 VE 2A +IN A 2 13 VE 1A N/C 3 12 OUT A V- 4 11 V+ N/C 5 10 OUT B +IN B 6 9 VE 1B -IN B 7 8 VE 2B ORDERING INFORMATION Operating Temperature Range -55°C to +125°C 0°C to +70°C 0°C to +70°C 14-Pin CERDIP Package 14-Pin Small Outline Package (SOIC) 14-Pin Plastic Dip Package ALD2724E DB ALD2724 DB ALD2724E SB ALD2724 SB ALD2724E PB ALD2724 PB TOP VIEW DB, PB, SB PACKAGE * Contact factory for industrial temperature range ©2002 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com GENERAL DESCRIPTION (cont'd) an ultra-high input impedance voltage follower/buffer that allows input and output voltage swings from positive to negative supply voltages. This feature is intended to greatly simplify systems design and eliminate higher voltage power supplies in many applications. Each ALD2724E/ALD2724 operational amplifier features individual, user-programmable offset voltage trimming resulting in significantly enhanced total system performance and user flexibility. EPAD technology is an exclusive ALD design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. It utilizes CMOS FETs as in-circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. Once programmed, the set parameters are stored indefinitely. EPAD offers the circuit designer a convenient and costeffective trimming solution for achieving the very highest amplifier/system performance. FUNCTIONAL DESCRIPTION The ALD2724E/ALD2724 utilizes EPADs as in-circuit elements for trimming of offset voltage bias characteristics. Each ALD2724E/ALD2724 operational amplifier has a pair of EPAD-based circuits connected such that one circuit is used to adjust VOS in one direction and the other circuit is used to adjust VOS in the other direction. While each of the basic EPAD device is a monotonically adjustable (offset voltage trimming) programmable device, the VOS of the ALD2724E can be adjusted many times in both directions. Once programmed, the set VOS levels are stored permanently, even when the device power is removed. Functional Description of ALD2724E/ALD2724 The ALD2724E is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. It also has a guaranteed offset voltage program range, which is ideal for applications that require electrical offset voltage programming. The ALD2724E is an operational amplifier that can be trimmed stand-alone, with user application-specific programming or in-system programming conditions. User application-specific circuit programming refers to a situation where the Total Input Offset Voltage of the ALD2724E can be trimmed with the actual intended operating conditions. Take the example of an application circuit that uses + 5V and -5V power supplies, an operational amplifier input biased at +1V, and an average operating temperature at +85°C; the circuit can be wired up to these conditions within an environmental chamber with the ALD2724E inserted into a test socket while it is being electrically trimmed. Any error in V OS due to these bias conditions can be automatically zeroed out. The Total VOS error, VOST, is now limited only by the adjustable range and the stability of VOS, and the input noise voltage of the operational amplifier. This Total Input Offset Voltage now includes VOS, as VOS is traditionally specified; plus the VOS error contributions from PSRR, CMRR, TCVOS , and noise. Typically, VOST ranges approximately ±25µV for the ALD2724E. In-System Programming refers to the condition where the EPAD adjustment is made after the ALD2724E has been 2 inserted into a circuit board. In this case, the circuit design must provide for the ALD2724E to operate in both normal mode and in programming mode. One of the benefits of insystem programming is that not only the ALD2724E offset voltage from operating bias conditions has been accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be programmed and corrected. In this way, the “insystem” circuit output can be adjusted to a desired level eliminating need for another trimming function. The ALD2724 is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. The ALD2724 offers similar programmable features as the ALD2724E, but with more limited offset voltage program range. It is intended for standard operational amplifier applications where little or no electrical programming by the user is necessary. USER PROGRAMMABLE VOS FEATURE Each ALD2724E/ALD2724 has four additional pins, compared to a conventional dual operational amplifier which has eight pins. These four additional pins are named VE1A, VE2A for op amp A and VE1B, VE2B for op amp B. Each of these pins VE1A, VE2A, VE1B, VE2B (represented by VExx) are connected to a separate, internal offset bias circuit. VExx pins have initial internal bias voltage values of approximately 1 to 2 Volts. The voltage on these pins can be programmed using the ALD E100 EPAD Programmer and the appropriate Adapter Module. The useful programming range of voltages on VExx pins are 1 Volt to 4 Volts. VExx pins are programming pins, used during electrical programming mode to inject charge into the internal EPADs. Increasing voltage on VE1A/VE1B decreases the offset voltage whereas increasing voltage on VE2A/VE2B increases the offset voltage of op amp A and op amp B, respectively. During programming, voltages on VExx pins are increased incrementally to program the offset voltage of the operational amplifier to the desired VOS . Note that desired VOS can be any value within the offset voltage programmable ranges, and can be either equal zero, a positive value or a negative value. This V OS value can also be reprogrammed to a different value at a later time, provided that the useful VE1x or VE2x programming voltage range has not been exceeded. The injected charge is then permanently stored. After programming, VExx pins must be left open in order for these voltages to remain at the programmed levels. Internally, VE1 and VE2 are programmed and connected differentially. Temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer. While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by the EPAD Programmer. In-system programming requires the ALD2722E application circuit to accommodate these programming pulses. If needed, this requirement can be accomplished by adding resistors at certain appropriate circuit nodes. Advanced Linear Devices ALD2724E/ALD2724 ABSOLUTE MAXIMUM RATINGS Supply voltage, V+ Differential input voltage range Power dissipation Operating temperature range PB,SB package DB package Storage temperature range Lead temperature, 10 seconds 13.2V -0.3V to V+ +0.3V 600 mW 0°C to +70°C -55°C to +125°C -65°C to +150°C +260°C OPERATING ELECTRICAL CHARACTERISTICS TA = 25oC VS = ±5.0V unless otherwise specified 2724E Parameter Symbol Supply Voltage VS V+ Min Typ ±3.25 6.5 25 2724 Max Min ±5.25 10.5 ±3.25 6.5 Max ±5.25 10.5 V V Single Supply µV RS ≤ 100KΩ Offset Voltage Program Range 2 ∆VOS Programmed Input Offset Voltage Error 3 VOS 25 100 40 150 µV At user specified target offset voltage Total Input Offset Voltage 4 VOST 25 100 40 150 µV At user specified target offset voltage Input Offset Current 5 IOS 10 0.01 10 pA 240 pA TA = 25°C 0°C ≤ TA ≤ +70°C 0.01 ±0.5 ±2 240 Input Bias Current 5 IB 0.01 10 0.01 240 Input Voltage Range 6 VIR Input Resistance Input Offset Voltage Drift Initial Power Supply mV 10 pA 240 pA TA = 25°C 0°C ≤ TA ≤ +70°C -0.3 5.3 -0.3 5.3 V V+ = +5V -2.8 +2.8 -2.8 +2.8 V VS = ±2.5V 1014 1014 TCVOS 5 5 PSRR i 85 CMRR i RIN 7 150 Test Conditions VOS i ±7 40 Unit Input Offset Voltage1 ±5 100 Typ Ω µV/°C RS ≤ 100KΩ 85 dB RS ≤ 100KΩ 90 90 dB RS ≤ 100KΩ 150 150 V/mV V/mV RL =10KΩ 0°C ≤ TA ≤ +70°C V V RL =1MΩ V =5V 0°C ≤ TA ≤ +70°C V RL =10KΩ 0°C ≤ TA ≤ +70°C Rejection Ratio 8 Initial Common Mode Rejection Ratio 8 Large Signal Voltage Gain AV Output Voltage Range VO low VO high 4.99 VO low VO high 4.90 Output Short Circuit Current -4.998 4.998 -4.99 -4.96 -4.90 ISC 4.95 4.99 4.90 15 -4.998 4.998 -4.99 -4.96 -4.90 4.95 15 V mA * NOTES 1 through 9, see section titled "Definitions and Design Notes". ALD2724E/ALD2724 Advanced Linear Devices 3 OPERATING ELECTRICAL CHARACTERISTICS (cont'd) TA = 25oC VS = ±5.0V unless otherwise specified 2724E Parameter Symbol Supply Current IS Min 2724 Typ Max 5.0 6.5 Min Typ Max 5.0 6.5 Unit mA Test Conditions VIN = 0V No Load Power Dissipation PD Input Capacitance CIN Maximum Load Capacitance 65 65 mW VS = ±2.5V 1 1 pF CL 400 4000 400 4000 pF pF Gain = 1 Gain = 5 Equivalent Input Noise Voltage en 26 26 nV/√Hz f = 1KHz Equivalent Input Noise Current in 0.6 0.6 fA/√Hz f =10Hz Bandwidth BW 2.1 2.1 MHz Slew Rate SR 5.0 5.0 V/µs AV = +1 R L = 2KΩ Rise time tr Overshoot Factor 0.1 0.1 µs R L = 2KΩ 15 15 % R L=2KΩ C L=100pF Settling Time tS Channel Separation CS 2 2 µs 0.1% 140 140 dB A V = 100 A V = -1 R L= 5KΩ C L = 50pF TA = 25o C VS = ±5.0V unless otherwise specified 2724E Parameter Symbol Voltage Stability 9 ∆ VOS ∆ time Initial VE Voltage VE1 i , VE2 i Programmable Change of ∆VE1, ∆VE2 Average Long Term Input Offset Min Typ 2724 Max Min 0.02 Typ 0.02 Max Unit Test Conditions µV/ 1000 hrs 1.5 1.4 2.5 V 2.0 0.5 V 0.1 0.1 % -5 -5 µA VE Range Programmed VE Voltage Error e(VE1-VE2) VE Pin Leakage Current i eb * NOTES 1 through 9, see section titled "Definitions and Design Notes". 4 Advanced Linear Devices ALD2724E/ALD2724 VS = ±5.0V -55°C ≤ TA ≤ +125°C unless otherwise specified 2724E Symbol Initial Input offset Voltage VOS i Input Offset Current IOS 2.0 2.0 nA Input Bias Current IB 2.0 2.0 nA Initial Power Supply PSRR i 85 85 dB RS ≤ 100KΩ Initial Common Mode Rejection Ratio 8 CMRR i 97 97 dB RS ≤ 100KΩ Large Signal Voltage Gain AV 10 25 10 25 V/mV RL = 10KΩ Output Voltage Range VO low VO high 4.8 -4.9 4.9 4.8 -4.9 4.9 V V RL = 10KΩ Rejection Ratio Min Typ 2724 Parameter Max Min 0.7 Typ Max 0.7 Unit Test Conditions mV RS ≤ 100KΩ 8 ALD2724E/ALD2724 -4.8 Advanced Linear Devices -4.8 5 TYPICAL PERFORMANCE CHARACTERISTICS COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE ±7 1000 } -55°C ±6 OPEN LOOP VOLTAGE GAIN (V/mV) COMMON MODE INPUT VOLTAGE RANGE (V) TA = 25°C ±5 ±4 ±3 } +25°C 100 } +125°C 10 RL = 10KΩ RL = 5KΩ ±2 1 ±3 ±2 ±5 ±4 ±6 ±7 SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 8 100 10 1.0 INPUTS GROUNDED OUTPUT UNLOADED 7 SUPPLY CURRENT (mA) VS = ±5.0V 1000 6 5 TA = -55°C 4 -25°C +25°C +80°C +125°C 3 2 1 0 -50 -25 0 25 50 75 100 125 0 ±1 ±2 AMBIENT TEMPERATURE (°C) ±3 ±4 ±5 ±6 ±7 SUPPLY VOLTAGE (V) CHANGE IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2 OPEN LOOP VOLTAGE AS A FUNCTION OF FREQUENCY 10 8 120 100 OPEN LOOP VOLTAGE GAIN (dB) VE2 6 4 2 0 -2 -4 -6 -8 VE1 -10 VS = ±5.0V TA = 25°C 80 60 0 40 45 20 90 0 135 180 -20 0 0.5 1.0 1.5 2.0 2.5 3.0 CHANGE IN VE1 AND VE2 (V) 1 10 100 1K 10K 100K 1M PHASE SHIFT IN DEGREES CHANGE IN INPUT OFFSET VOLTAGE ∆VOS (mV) ±8 ±6 INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE 0.1 6 ±4 SUPPLY VOLTAGE (V) 10000 INPUT BIAS CURRENT (pA) ±2 0 SUPPLY VOLTAGE (V) 10M FREQUENCY (Hz) Advanced Linear Devices ALD2724E/ALD2724 TYPICAL PERFORMANCE CHARACTERISTICS ±7 OUTPUT VOLTAGE SWING (V) LARGE - SIGNAL TRANSIENT RESPONSE OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE 5V/div VS = ±5.0V TA = 25°C RL = 1KΩ CL = 50pF 5V/div 2µs/div ±25°C ≤ TA ≤ 125°C ±6 RL = 10KΩ ±5 RL = 10KΩ ±4 RL = 2KΩ ±3 ±2 0 ±1 ±2 ±4 ±3 ±5 ±6 ±7 SUPPLY VOLTAGE (V) SMALL - SIGNAL TRANSIENT RESPONSE OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF LOAD RESISTANCE 1000 OPEN LOOP VOLTAGE GAIN (V/mV) 100mV/div VS = ± 5.0V TA = 25°C RL = 1.0KΩ CL = 50pF 100 VS = ±5.0V TA = 25°C 10 50mV/div 1µs/div 1 1K 10K 100K 1000K LOAD RESISTANCE (Ω) DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE BEFORE AND AFTER EPAD PROGRAMMING PERCENTAGE OF UNITS (%) 100 80 EXAMPLE A: VOST AFTER EPAD PROGRAMMING VOST TARGET = 0.0µV EXAMPLE B: VOST AFTER EPAD PROGRAMMING VOST TARGET = -750µV 60 VOST BEFORE EPAD PROGRAMMING 40 20 0 -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500 TOTAL INPUT OFFSET VOLTAGE (µV) ALD2724E/ALD2724 Advanced Linear Devices 7 EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE (µV) TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 500 PSRR = 80 dB 400 EXAMPLE A: VOS EPAD PROGRAMMED AT VSUPPLY = +5V 300 EXAMPLE B: VOS EPAD PROGRAMMED AT VSUPPLY = +8V 200 100 0 1 0 2 3 4 5 6 7 8 9 10 EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µV) SUPPLY VOLTAGE (V) THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE 500 VSUPPLY = ±5V CMRR = 80dB 400 300 EXAMPLE B: VOS EPAD PROGRAMMED AT VIN = -4.3V 200 EXAMPLE A: VOS EPAD PROGRAMMED AT VIN = 0V 100 EXAMPLE C: VOS EPAD PROGRAMMED AT VIN = +5V 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µV) COMMON MODE VOLTAGE (V) EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE FOR A COMMON MODE VOLTAGE RANGE OF 0.5V 50 COMMON MODE VOLTAGE RANGE OF 0.5V 40 30 VOS EPAD PROGRAMMED AT COMMON MODE VOLTAGE OF 0.25V 20 CMRR = 80dB 10 0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 COMMON MODE VOLTAGE (V) 8 Advanced Linear Devices ALD2724E/ALD2724 APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING 2500 2500 2000 2000 TOTAL INPUT OFFSET VOLTAGE (µV) TOTAL INPUT OFFSET VOLTAGE (µV) Examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions 1500 1000 VOS BUDGET AFTER EPAD PROGRAMMING 500 0 -500 + X -1000 -1500 -2000 VOS BUDGET BEFORE EPAD PROGRAMMING 1500 VOS BUDGET AFTER EPAD PROGRAMMING 1000 500 + 0 X -500 -1000 -1500 VOS BUDGET BEFORE EPAD PROGRAMMING -2000 -2500 -2500 EXAMPLE B 2500 2500 2000 2000 TOTAL INPUT OFFSET VOLTAGE (µV) TOTAL INPUT OFFSET VOLTAGE (µV) EXAMPLE A 1500 1000 VOS BUDGET BEFORE EPAD PROGRAMMING 500 0 -500 -1000 + X -1500 -2000 VOS BUDGET AFTER EPAD PROGRAMMING 1500 1000 500 + 0 X -500 -1000 -1500 -2000 -2500 VOS BUDGET AFTER EPAD PROGRAMMING VOS BUDGET BEFORE EPAD PROGRAMMING -2500 EXAMPLE C EXAMPLE D Device input VOS PSRR equivalent VOS + Total Input VOS after EPAD Programming CMRR equivalent VOS TA equivalent VOS X Noise equivalent VOS External Error equivalent VOS ALD2724E/ALD2724 Advanced Linear Devices 9 DEFINITIONS AND APPLICATION NOTES: DESIGN NOTES: 1. Initial Input Offset Voltage is the initial offset voltage of the ALD2724E/ALD2724 operational amplifier when shipped from the factory. The device has been pre-programmed and tested for programmability. A. The ALD2724E/ALD2724 is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 70 degrees of phase margin at unity gain frequency. A unity gain buffer using the ALD2724E/ALD2724 will typically drive 400pF of external load capacitance. 2. Offset Voltage Program Range is the range of adjustment of user specified target offset voltage. This is typically an adjustment in either the negative or positive direction of the input offset voltage from an initial input offset voltage. The input offset programming pins, VE1A/VE1B or VE2A/VE2B change the input offset voltages in the negative or positive direction, for each of the amplifier A or B, respectively. User specified target offset voltage can be any offset voltage within this programming range. 3. Programmed Input Offset Voltage Error is the final offset voltage error after programming when the Input Offset Voltage is at target Offset Voltage. This parameter is sample tested. 4. Total Input Offset Voltage is the same as Programmed Input Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, PSRR, CMRR, TCVOS and noise. It can also include errors introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. This parameter is sample tested. 5. The Input Offset and Bias Currents are essentially input protection diode reverse bias leakage currents. This low input bias current assures that the analog signal from the source will not be distorted by it. For applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage having a separate input offset voltage. While Total Input Offset Voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one user selected input bias voltage. Depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. For the ALD2724E/ ALD2724, the switching point between the two stages occur at approximately 1.5V above negative supply voltage. 7. Input Offset Voltage Drift is the average change in Total Input Offset Voltage as a function of ambient temperature. This parameter is sample tested. 8. Initial PSRR and initial CMRR specifications are provided as reference information. After programming, error contribution to the offset voltage from PSRR and CMRR is set to zero under the specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error. 9. Average Long Term Input Offset Voltage Stability is based on input offset voltage shift through operating life test at 125°C extrapolated to TA = 25 °C, assuming activation energy of 1.0eV. This parameter is sample tested. 10 B. The ALD2724E/ALD2724 has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail-to-rail input common mode voltage range. The switching point between the two differential stages is 1.5V above negative supply voltage. For applications such as inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5V operation), the common mode voltage does not make excursions below this switching point. However, this switching does take place if the operational amplifier is connected as a railto-rail unity gain buffer and the design must allow for input offset voltage variations. C. The output stage consists of class AB complementary output drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD2724E/ALD2724 an effective analog signal buffer for high source impedance sensors, transducers, and other circuit networks. D. The ALD2724E/ALD2724 has static discharge protection. Care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages not to exceed 0.3V of the power supply voltage levels. E. VExx are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. For some applications, these terminals may need to be shielded from external coupling sources. For example, digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout to place ground traces around these pins and to isolate them from digital lines will generally eliminate such coupling effects. In addition, optional decoupling capacitors of 1000pF or greater value can be added to VExx terminals. F. The ALD2724E/ALD2724 is designed for use in low voltage, micropower circuits. The maximum operating voltage during normal operation should remain below 10 Volts at all times. Care should be taken to insure that the application in which the device is used do not experience any positive or negative transient voltages that will cause any of the terminal voltages to exceed this limit. G. All inputs or unused pins except VExx pins should be connected to a supply voltage such as Ground so that they do not become floating pins, since input impedance at these pins is very high. If any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. As these devices are built with CMOS technology, normal operating and storage temperature limits, ESD and latchup handling precautions pertaining to CMOS device handling should be observed. Advanced Linear Devices ALD2724E/ALD2724