Hynix HY5DU283222F-5 128m(4mx32) gddr sdram Datasheet

HY5DU283222F
128M(4Mx32) GDDR SDRAM
HY5DU283222F
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2/Sep. 02
1
HY5DU283222F
Rvision History
Revision
No.
History
Draft
Date
0.4
1) Part Number changed from HY5DU283222F to HY6U22F
May.01
0.5
1) tAC/tDQSCK, tRCD/tRP parameters each speed changed as the followings
a) tAC : changed from 0.7ns to 0.9ns at 3.3/4/4.5ns
b) tDQSCK : changed from 0.6ns to 0.7ns at 3.3/4/4.5ns
c) tRCD/tRP : changed from 5clk to 6clk at 3.3ns and 4clk to 5clk at 4/4.5ns
Jun. 01
0.6
1) 222Mhz speed bin removed
2) IDD Specification of 200/250MHz part defined
3) AC parameters of 275MHz part defined
4) ViH/ViL changed Vref+/- 0.35 into Vref +/- 0.45
5) Part number changed from HY6U22F to HY5DU283222F
Oct.01
0.7
1) Pin capacitance defined
a) CK, /CK, All other input-only pins : min 1pF, Max 3PF
b) DQ, DQS, DM : min 3pF, Max 5pF
Nov.01
0.8
1)
2)
3)
4)
5)
200MHz tCK Max. changed from 7ns to 10ns
Device operation and timing diagram removed
tRCD/tRP at 275MHz changed from 6clk to 5clk
tRC/tRFC SPEC newly defined
375/350MHz AC parameters defined
Dec.01
0.9
1)
2)
3)
4)
IDD4 SPEC changed 370mA to 300mA
275/300MHz IDD SPEC defined
tRC/tRFC/tRAS SPEC. updated
Power dissipation SPEC. changed from 1W to 2W
Dec.01
1.0
1) Input leakage current changed from +/-5uA to +/-2uA
May. 02
1.1
1) Defined tPDEX parameter
2) Added AC CHARACTERISTICS-II table
May. 02
1.2
1) Changed VDD/VDDQ value
- 350/375MHz : Changed from 2.66V/2.80V/2.94V to 2.76V/2.90V/3.05V
(min/typ/max)
2) IDD4 SPEC at 200MHz changed 300mA to 370mA
Sep. 02
Rev. 1.2/Sep. 02
Remark
2
HY5DU283222F
DESCRIPTION
The Hynix HY5DU283222F is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
2.5V +/- 5% VDD and VDDQ power supply
supported up to 300/275/250/200MHz
•
2.9V +/- 5% VDD and VDDQ power supply
supported up to 350/375MHz
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
Write mask byte controls by DM (DM0 ~ DM3)
•
Programmable /CAS Latency 3 and 4 supported
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
All inputs and outputs are compatible with SSTL_2
interface
•
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
•
Fully differential clock inputs (CK, /CK) operation
•
Internal 4 bank operations with single pulsed /RAS
•
Double data rate interface
•
tRAS Lock-Out function supported
•
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
•
Auto refresh and self refresh supported
•
4096 refresh cycles / 32ms
•
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
Half strength and Matched Impedance driver option
controlled by EMRS
•
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
ORDERING INFORMATION
Part No.
Power Supply
Clock
Frequency
Max Data Rate
HY5DU283222F-26
VDD 2.9V
375MHz
750Mbps/pin
HY5DU283222F-28
VDDQ 2.9V
350MHz
700Mbps/pin
300MHz
600Mbps/pin
HY5DU283222F-33
HY5DU283222F-36
VDD 2.5V
275MHz
550Mbps/pin
HY5DU283222F-4
VDDQ 2.5V
250MHz
500Mbps/pin
200MHz
400Mbps/pin
HY5DU283222F-5
Rev. 1.2/Sep. 02
interface
SSTL_2
Package
12mm x 12mm
144Ball FBGA
3
HY5DU283222F
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
B
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
C
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
D
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
E
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
F
DQ17
DQ16
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ15
DQ14
G
DQ19
DQ18
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ13
DQ12
H
DQS2
DM2
NC
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
NC
DM1
DQS1
J
DQ21
DQ20
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ11
DQ10
K
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
L
/CAS
/W/E
VDD
VSS
A10
VDD
VDD
NC2
VSS
VDD
NC
NC
M
/RAS
NC
NC
BA1
A2
A11
A9
A5
NC3
CLK
/CLK
NC
N
/CS
NC
BA0
A0
A1
A3
A4
A6
A7
A8/AP
CKE
VREF
14
A
P
Note :
1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.
2. Ball L9(NC2) is reserved for A12.
3. Ball M10(NC3) is reserved for BA2.
ROW and COLUMN ADDRESS TABLE
Rev. 1.2/Sep. 02
Items
4Mx32
Organization
1M x 32 x 4banks
Row Address
A0 ~ A11
Column Address
A0 ~ A7
Bank Address
BA0, BA1
Auto Precharge Flag
A8
Refresh
4K
4
HY5DU283222F
PIN DESCRIPTION
PIN
TYPE
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM0 ~ DM3
Input
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
DQS0 ~ DQS3
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
DQ0 ~ DQ31
I/O
Data input / output pin : Data Bus
VDD/VSS
Supply
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
VREF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
Rev. 1.2/Sep. 02
DESCRIPTION
No connection.
5
HY5DU283222F
FUNCTIONAL BLOCK DIAGRAM
4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM
Input Buffer
32
Write Data Register
2-bit Prefetch Unit
64
1Mx32/Bank0
1Mx32 /Bank2
64
1Mx32 /Bank3
Mode
Register
32
Output Buffer
1Mx32 /Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM(0~3)
DS
DQ[0:31]
Row
Decoder
Column Decoder
A0-11
BA0,BA1
Address
Buffer
DQS(0~3)
Column Address
Counter
Data Strobe
Transmitter
CLK_DLL
DS
CLK,
/CLK
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 1.2/Sep. 02
6
HY5DU283222F
SIMPLIFIED COMMAND TRUTH TABLE
A8/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
H
X
X
X
L
H
H
H
X
1
H
X
L
L
H
H
H
X
L
H
L
H
CA
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
1
H
X
X
X
1
L
V
V
V
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Self Refresh
Precharge Power
Down Mode
Active Power
Down Mode
Exit
L
H
Entry
H
L
Exit
L
H
X
ADDR
RA
BA
V
L
H
L
H
V
V
Note
1
1
1,3
1
1,4
H
X
1,5
L
V
1
1
X
1
1
X
X
1
1
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 1.2/Sep. 02
7
HY5DU283222F
WRITE MASK TRUTH TABLE
CKEn-1
CKEn
/CS, /RAS,
/CAS, /WE
DM(0~3)
Data Write
H
X
X
L
X
1,2
Data-In Mask
H
X
X
H
X
1,2
Function
ADDR
A8/
AP
BA
Note
Note :
1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data.
2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23;
DM3 corresponds to the data on DQ24-Q31.
Rev. 1.2/Sep. 02
8
HY5DU283222F
OPERATION COMMAND TRUTH TABLE - I
Current
State
IDLE
ROW
ACTIVE
READ
WRITE
Rev. 1.2/Sep. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP or power down3
L
H
H
H
X
NOP
NOP or power down3
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4
L
L
H
H
BA, RA
ACT
Row Activation
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
AREF/SREF
Auto Refresh or Self Refresh5
L
L
L
L
OPCODE
MRS
Mode Register Set
H
X
X
X
X
DSEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Begin read : optional AP6
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Begin write : optional AP6
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Precharge7
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Terminate burst
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Term burst, new write:optional AP
9
HY5DU283222F
OPERATION COMMAND TRUTH TABLE - II
Current
State
WRITE
READ
WITH
AUTOPRECHARGE
WRITE
AUTOPRECHARGE
PRECHARGE
Rev. 1.2/Sep. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP-Enter IDLE after tRP
L
H
H
H
X
NOP
NOP-Enter IDLE after tRP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
NOP-Enter IDLE after tRP
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
10
HY5DU283222F
OPERATION COMMAND TRUTH TABLE - III
Current
State
ROW
ACTIVATING
WRITE
RECOVERING
WRITE
RECOVERING
WITH
AUTOPRECHARGE
REFRESHING
Rev. 1.2/Sep. 02
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tRCD
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tRCD
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,9,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tWR
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tWR
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter precharge after tDPL
L
H
H
H
X
NOP
NOP - Enter precharge after tDPL
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,8,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tRC
L
H
H
H
X
NOP
NOP - Enter IDLE after tRC
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
11
HY5DU283222F
OPERATION COMMAND TRUTH TABLE - IV
Current
State
WRITE
MODE
REGISTER
ACCESSING
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Rev. 1.2/Sep. 02
12
HY5DU283222F
CKE FUNCTION TRUTH TABLE
Current
State
CKEn1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
SELF
REFRESH1
POWER
DOWN2
ALL BANKS
IDLE4
ANY STATE
OTHER
THAN
ABOVE
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
Note :
When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 1.2/Sep. 02
13
HY5DU283222F
SIMPLIFIED STATE DIAGRAM
MRS
MODE
REGISTER
SET
SREF
SELF
REFRESH
IDLE
SREX
PDEN
PDEX
AREF
ACT
POWER
DOWN
POWER
DOWN
AUTO
REFRESH
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
WRITE
WRITEAP
WRITE
WITH
AUTOPRECHARGE
PRE(PALL)
READAP
READ
READAP
WITH
AUTOPRECHARGE WRITEAP
READ
WRITE
PRE(PALL)
PRE(PALL)
PRECHARGE
POWER-UP
Command Input
Automatic Sequence
POWER APPLIED
Rev. 1.2/Sep. 02
14
HY5DU283222F
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and
to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to
the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for
CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS
LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee
that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM
requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.)
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.
• VREF tracks VDDQ/2.
• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the
input current from the VTT supply into any pin.
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up.
Votage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2.
Start clock and maintain stable clock for a minimum of 200usec.
3.
After stable power and clock, apply NOP condition and take CKE high.
4.
Issue Extended Mode Register Set (EMRS) to enable DLL.
5.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=High. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
6.
Issue Precharge commands for all banks of the device.
Rev. 1.2/Sep. 02
15
HY5DU283222F
7.
Issue 2 or more Auto Refresh commands.
8.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
/CLK
CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
ADDR
CODE
A10
BA0, BA1
NOP
PRE
MRS
ACT
RD
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
Non-Read
Command
READ
AREF
DM
DQS
DQ'S
T=200usec
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tXSRD*
Power UP
VDD and CK stable
Precharge All
EMRS Set
MRS Set
Reset DLL
(with A8=H)
Precharge All
2 or more
Auto Refresh
MRS Set
(with A8=L)
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Rev. 1.2/Sep. 02
16
HY5DU283222F
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
0
0
A11
A10
RFU
A9
A8
A7
DR
TM
A6
A5
A4
CAS Latency
BA0
MRS Type
A7
Test Mode
0
MRS
0
Normal
1
EMRS
1
Vendor
test mode
A3
A2
BT
A1
A0
Burst Length
Burst Length
Rev. 1.2/Sep. 02
A2
A1
A8
DLL Reset
0
No
0
0
1
Yes
0
A0
Sequential
Interleave
0
Reserved
Reserved
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
A3
Burst Type
1
1
0
Reserved
0
Sequential
1
1
1
Reserved
1
Interleave
17
HY5DU283222F
BURST DEFINITION
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Rev. 1.2/Sep. 02
18
HY5DU283222F
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-topoint environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,
Class II, and Matched impedance driver, about 30% of Full drive strength.
Rev. 1.2/Sep. 02
19
HY5DU283222F
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1
BA0
0
1
A11
A10
A9
RFU*
BA0
MRS Type
0
MRS
1
EMRS
A8
A7
A6
A5
A4
DS
A3
RFU*
A2
A1
A0
DS
DLL
A0
DLL enable
0
Enable
1
Diable
A6
A1
Output Driver Impedance Control
0
0
RFU*
0
1
Half
1
0
RFU*
1
1
Matched Impedance (Weak)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 1.2/Sep. 02
20
HY5DU283222F
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
oC
Storage Temperature
TSTG
-55 ~ 125
oC
VIN, VOUT
-0.5 ~ 3.6
V
VDD
-0.5 ~ 3.6
V
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
2
W
TSOLDER
260 ⋅ 10
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Soldering Temperature ⋅ Time
o
C ⋅ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
Symbol
Power Supply Voltage
VDD
Power Supply Voltage
VDDQ
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Min
Typ.
Max
2.375
2.5
2.625
2.76
2.9
3.05
2.375
2.5
2.625
2.76
2.9
3.05
Unit
V
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
Note
350/375MHz
1
350/375MHz
2
3
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with ≤ 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak to peak noise on VREF may not exceed ± 2% of the DC value.
DC CHARACTERISTICS I
Parameter
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-2
2
uA
1
Output Leakage Current
ILO
-5
5
uA
2
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 1.2/Sep. 02
21
HY5DU283222F
DC CHARACTERISTICS II
Parameter
Operating Current
Sym
bol
IDD1
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
Test Condition
Unit Note
Burst length=4, One bank active
tRC ≥ tRC(min), IOL=0mA
Precharge Standby
Current in Power Down IDD2P CKE ≤ VIL(max), tCK=min
Mode
26
28
33
36
4
5
300
300
280
280
280
260
mA
30
30
30
30
30
20
mA
1
Precharge Standby
Current in Non Power
Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD2N tCK = min, Input signals are
changed one time during 2clks
100
100
90
90
90
80
mA
Active Standby Current in Power Down
Mode
IDD3P CKE ≤ VIL(max), tCK=min
35
35
35
35
35
25
mA
Active Standby Current in Non Power
Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD3N tCK=min, Input signals are
changed one time during 2clks
160
160
130
130
130
100
mA
Burst Mode Operating
Current
CL=4
630
600
470
450
450
370
mA
1
IDD4
CL=3
630
600
470
450
450
370
mA
1
300
300
270
270
270
mA
1,2
3
3
3
3
3
mA
tCK ≥ tCK(min), IOL=0mA
All banks active
tRC ≥ tRFC(min),
All banks active
Auto Refresh Current
IDD5
Self Refresh Current
IDD6 CKE ≤ 0.2V
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.2/Sep. 02
22
HY5DU283222F
AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.45
V
Up to 350MHz
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
V
Up to 350MHz
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
V
375MHz only
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
VREF - 0.7
V
375MHz only
Input Differential Voltage, CK and /CK inputs
VID(AC)
0.7
VDDQ + 0.6
V
1
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
VREF - 0.45
VREF + 0.7
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.45
V
Up to 350MHz
AC Input Low Level Voltage (VIL, max)
VREF - 0.45
V
Up to 350MHz
AC Input High Level Voltage (VIH, min)
VREF + 0.7
V
375MHz only
AC Input Low Level Voltage (VIL, max)
VREF - 0.7
V
375MHz only
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 1.2/Sep. 02
Unit
23
HY5DU283222F
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
26
28
33
Unit
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
59.8
-
61.6
-
62.7
-
ns
Auto Refresh Row Cycle Time
tRFC
65
-
64.4
-
66
-
ns
Row Active Time
tRAS
41.6
120K
42
120K
42.9
120K
ns
Row Address to Column Address Delay for Read
tRCDRD
7
-
7
-
6
-
CK
Row Address to Column Address Delay for Write
tRCDWR
4
-
4
-
3
-
CK
Row Active to Row Active Delay
tRRD
2
-
2
-
2
-
CK
Column Address to Column Address Delay
tCCD
1
-
1
-
1
-
CK
Row Precharge Time
tRP
7
-
7
-
6
-
CK
Write Recovery Time
tWR
3
-
3
-
3
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
10
-
10
-
9
-
CK
2.6
6
2.8
6
3.3
6
ns
-
-
-
-
-
-
ns
System Clock Cycle Time
CL=4
CL=3
tCK
Note
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.9
0.9
-0.9
0.9
-0.9
0.9
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.7
0.7
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
-
0.4
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1,5
tQHS
-
0.5
-
0.5
-
0.5
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
0.75
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
0.75
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
0.4
-
0.4
-
ns
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
0.4
-
0.4
-
ns
3
tRPRE
0.7
1.1
0.7
1.1
0.7
1.1
CK
Data Hold Skew Factor
Read DQS Preamble Time
Rev. 1.2/Sep. 02
24
HY5DU283222F
Parameter
Symbol
26
28
33
Unit
Min
Max
Min
Max
Min
Max
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
1.5
-
1.5
-
1.5
-
ns
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
Power Down Exit Time
tPDEX
2tCK
+ tIS
-
2tCK
+ tIS
-
2tCK
+ tIS
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
us
Read DQS Postamble Time
Note
4
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.2/Sep. 02
25
HY5DU283222F
AC CHARACTERISTICS - I (continue)
Parameter
Symbol
36
4
5
Unit
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
61.2
-
60
-
60
-
ns
Auto Refresh Row Cycle Time
tRFC
64.8
-
64
-
65
-
ns
Row Active Time
tRAS
43.2
120K
40
120K
40
120K
ns
Row Address to Column Address Delay for Read
tRCDRD
5
-
5
-
4
-
CK
Row Address to Column Address Delay for Write
tRCDWR
3
-
3
-
2
-
CK
Row Active to Row Active Delay
tRRD
2
-
2
-
2
-
CK
Column Address to Column Address Delay
tCCD
1
-
1
-
1
-
CK
Row Precharge Time
tRP
5
-
5
-
4
-
CK
Write Recovery Time
tWR
3
-
3
-
2
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
8
-
8
-
6
-
CK
3.6
6
4
6
-
-
ns
-
-
-
-
5
10
ns
System Clock Cycle Time
CL=4
CL=3
tCK
Note
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.9
0.9
-0.9
0.9
-0.9
0.9
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.7
0.7
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
-
0.4
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1,5
tQHS
-
0.5
-
0.6
-
0.6
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
1.0
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
1.0
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
0.45
-
0.5
-
ns
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
0.45
-
0.5
-
ns
3
Data Hold Skew Factor
Rev. 1.2/Sep. 02
26
HY5DU283222F
Parameter
Symbol
36
4
5
Unit
Min
Max
Min
Max
Min
Max
Read DQS Preamble Time
tRPRE
0.7
1.1
0.7
1.1
0.8
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
1.5
-
1.5
-
1.5
-
ns
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
Power Down Exit Time
tPDEX
1tCK
+ tIS
-
1tCK
+ tIS
-
1tCK
+ tIS
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
us
Note
4
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.2/Sep. 02
27
HY5DU283222F
AC CHARACTERISTICS - II
Frequency
CL
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tDAL
Unit
375MHz (2.6ns)
4
23
25
16
7
4
7
10
tCK
350MHz (2.8ns)
4
22
23
15
7
4
7
10
tCK
300MHz (3.3ns)
4
19
20
13
6
3
6
9
tCK
275MHz (3.6ns)
4
17
18
12
5
3
5
8
tCK
250MHz (4.0ns)
4
15
16
10
5
3
5
8
tCK
200MHz (5.0ns)
3
12
13
8
4
2
4
6
tCK
Rev. 1.2/Sep. 02
28
HY5DU283222F
CAPACITANCE (TA=25oC, f=1MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
CK, /CK
CCK
1
3
pF
Input Capacitance
All other input-only pins
CIN
1
3
pF
Input / Output Capacitance
DQ, DQS, DM
CIO
3
5
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
V TT
R T =50Ω
Output
Zo=50Ω
V REF
C L=30pF
Rev. 1.2/Sep. 02
29
HY5DU283222F
PACKAGE INFORMATION
12mm x 12mm, 144ball Fine-pitch Ball Grid Array
12mm± 0.1
1.2 mm max
0.76mm ± 0.05
12mm± 0.1
Detailed “A”
8.8mm
0.35mm ± 0.05
0.8mm
Detailed “A”
8.8mm
0.12mm
0.5mm Diameter
0.55Max
0.45Min
[ Ball Location ]
Ball existing
Optional (Vss thermal ball)
Rev. 1.2/Sep. 02
30
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