LTC3787 PolyPhase Synchronous Boost Controller FEATURES DESCRIPTION n The LTC®3787 is a high performance PolyPhase® single output synchronous boost converter controller that drives two N-channel power MOSFET stages out-of-phase. Multiphase operation reduces input and output capacitor requirements and allows the use of smaller inductors than the single-phase equivalent. Synchronous rectification increases efficiency, reduces power losses and eases thermal requirements, enabling high power boost applications. n n n n n n n n n n n n n 2-Phase Operation Reduces Required Input and Output Capacitance and Power Supply Induced Noise Synchronous Operation for Highest Efficiency and Reduced Heat Dissipation Wide VIN Range: 4.5V to 38V (40V Abs Max) and Operates Down to 2.5V After Start-Up Output Voltage Up to 60V ±1% 1.200V Reference Voltage RSENSE or Inductor DCR Current Sensing 100% Duty Cycle Capability for Synchronous MOSFET Low Quiescent Current: 135μA Phase-Lockable Frequency (75kHz to 850kHz) Programmable Fixed Frequency (50kHz to 900kHz) Power Good Output Voltage Monitor Low Shutdown Current, IQ < 8μA Internal LDO Powers Gate Drive from VBIAS or EXTVCC Thermally Enhanced Low Profile 28-Pin 4mm × 5mm QFN Package and Narrow SSOP Package The SS pin ramps the output voltage during start-up. The PLLIN/MODE pin selects Burst Mode® operation, pulseskipping mode or forced continuous mode at light loads. APPLICATIONS n n n n A 4.5V to 38V input supply range encompasses a wide range of system architectures and battery chemistries. When biased from the output of the boost converter or another auxiliary supply, the LTC3787 can operate from an input supply as low as 2.5V after start-up. The operating frequency can be set for a 50kHz to 900kHz range or synchronized to an external clock using the internal PLL. PolyPhase operation allows the LTC3787 to be configured for 2-, 3-, 4-, 6- and 12-phase operation. Industrial Automotive Medical Military L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. TYPICAL APPLICATION Efficiency and Power Loss vs Output Current 12V to 24V/10A 2-Phase Synchronous Boost Converter VIN 4.5V TO 24V START-UP VOLTAGE OPERATES THROUGH TRANSIENTS DOWN TO 2.5V 100 VIN 10000 90 BOOST1 TG2 BOOST2 0.1μF SW1 80 47μF 3.3μH 0.1μF VOUT 24V AT 10A SW2 LTC3787 12.1k 100 50 40 10 VIN = 12V 1 VOUT = 24V Burst Mode OPERATION FIGURE 10 CIRCUIT 0 0.1 0.1 1 10 0.00001 0.0001 0.001 0.01 OUTPUT CURRENT (A) 20 10 15nF 8.66k 60 30 BG1 BG2 SENSE1+ – SENSE1 SENSE2+ VFB SENSE2– FREQ PGND PLLIN/MODE ITH SS SGND 232k 1000 70 POWER LOSS (mW) TG1 VBIAS INTVCC 3.3μH 4mΩ EFFICIENCY (%) 4.7μF 4.7μF 4mΩ 220μF 3787 TA01b BURST EFFICIENCY BURST LOSS 100pF 0.1μF 3787 TA01a 3787fc 1 LTC3787 ABSOLUTE MAXIMUM RATINGS (Notes 1, 3) VBIAS ........................................................ –0.3V to 40V BOOST1 and BOOST2 ................................ –0.3V to 76V SW1 and SW2............................................ –0.3V to 70V RUN ............................................................. –0.3V to 8V Maximum Current Sourced into Pin From Source >8V ..............................................100μA PGOOD, PLLIN/MODE ................................. –0.3V to 6V INTVCC, (BOOST1 - SW1), (BOOST2 - SW2) ...–0.3V to 6V EXTVCC ........................................................ –0.3V to 6V SENSE1+, SENSE1–, SENSE2+, SENSE2– ... –0.3V to 40V (SENSE1+ - SENSE1–), (SENSE2+ - SENSE2–) ...–0.3V to 0.3V ILIM, SS, ITH, FREQ, PHASMD, VFB ..... –0.3V to INTVCC Operating Junction Temperature Range (Note 2)........................................–55°C to 150°C Storage Temperature Range .................. –65°C to 150°C PIN CONFIGURATION TOP VIEW 26 TG1 SGND 8 RUN 9 SS 10 23 VBIAS CLKOUT 3 21 BG1 22 PGND PLLIN/MODE 4 20 VBIAS 21 EXTVCC 19 PGND 29 GND SGND 5 18 EXTVCC 17 INTVCC RUN 6 20 INTVCC 16 BG2 SS 7 19 BG2 18 BOOST2 SENSE2+ 12 17 TG2 VFB 13 16 SW2 ITH 14 15 NC 15 BOOST2 9 10 11 12 13 14 SENSE2+ SENSE2– 11 SENSE2– 8 TG2 7 24 BG1 SW2 PLLIN/MODE 6 22 BOOST1 PHASMD 2 NC CLKOUT 5 25 BOOST1 ITH PHASMD 4 28 27 26 25 24 23 FREQ 1 VFB FREQ TG1 27 SW1 3 SW1 2 SENSE1– PGOOD SENSE1+ ILIM 28 PGOOD SENSE1+ 1 SENSE1– TOP VIEW ILIM UFD PACKAGE 28-LEAD (4mm s 5mm) PLASTIC QFN GN PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND TJMAX = 125°C, θJA = 90°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3787EUFD#PBF LTC3787EUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3787IUFD#PBF LTC3787IUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3787HUFD#PBF LTC3787HUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C LTC3787MPUFD#PBF LTC3787MPUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –55°C to 150°C LTC3787EGN#PBF LTC3787EGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 125°C LTC3787IGN#PBF LTC3787IGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 125°C LTC3787HGN#PBF LTC3787HGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 150°C LTC3787MPGN#PBF LTC3787MPGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3787fc 2 LTC3787 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop VBIAS Chip Bias Voltage Operating Range 4.5 VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) IFB Feedback Current (Note 4) VREFLNREG Reference Line Voltage Regulation VBIAS = 6V to 38V VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ΔITH Voltage = 1.2V to 2V l 1.188 38 1.200 1.212 V ±5 ±50 nA 0.002 0.02 %/V l 0.01 0.1 % l –0.01 –0.1 % gm Error Amplifier Transconductance ITH = 1.2V IQ Input DC Supply Current Pulse-Skipping or Forced Continuous Mode Sleep Mode Shutdown (Note 5) RUN = 5V; VFB = 1.25V (No Load) RUN = 5V; VFB = 1.25V (No Load) RUN = 0V INTVCC Undervoltage Lockout Thresholds VINTVCC Ramping Up VINTVCC Ramping Down l l 4.1 3.8 4.3 3.6 VRUN Rising l 1.18 1.28 1.38 UVLO VRUN RUN Pin ON Threshold VRUNHYS RUN Pin Hysteresis IRUNHYS RUN Pin Hysteresis Current IRUN V 2 1.2 135 8 mmho 300 20 mA μA μA V V V 100 mV VRUN > 1.28V 4.5 μA RUN Pin Current VRUN < 1.28V 0.5 μA ISS Soft-Start Charge Current VSS = GND VSENSE1,2(MAX) Maximum Current Sense Threshold VFB = 1.1V, ILIM = INTVCC VFB = 1.1V, ILIM = Float VFB = 1.1V, ILIM = GND VSENSE(MATCH) Matching Between VSENSE1(MAX) and VSENSE2(MAX) VFB = 1.1V, ILIM = INTVCC VFB = 1.1V, ILIM = Float VFB = 1.1V, ILIM = GND VSENSE(CM) SENSE Pins Common Mode Range (BOOST Converter Input Supply Voltage VIN) ISENSE1,2+ SENSE+ Pin Current VFB = 1.1V, ILIM = Float ISENSE1,2– SENSE– Pin Current VFB = 1.1V, ILIM = Float tr(TG1,2) Top Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns tf(TG1,2) Top Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns tr(BG1,2) Bottom Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns tr(BG1,2) Bottom Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns RUP(TG1,2) Top Gate Pull-Up Resistance 1.2 Ω RDN(TG1,2) Top Gate Pull-Down Resistance 1.2 Ω RUP(TG1,2) Bottom Gate Pull-Up Resistance 1.2 Ω RDN(TG1,2) Bottom Gate Pull-Down Resistance 1.2 Ω tD(TG/BG) Top Gate Off to Bottom Gate On Switch-On Delay Time CLOAD = 3300pF (Each Driver) 70 ns tD(BG/TG) Bottom Gate Off to Top Gate On Switch-On Delay Time CLOAD = 3300pF (Each Driver) 70 ns DFBG1,2(MAX) Maximum BG Duty Factor 96 % tON(MIN) Minimum BG On-Time 7 10 13 μA l l l 90 68 42 100 75 50 110 82 56 mV mV mV l l l –12 –10 –9 0 0 0 12 10 9 mV mV mV 38 V 300 μA ±1 μA 2.5 (Note 7) 200 110 ns 3787fc 3 LTC3787 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 5.2 5.4 5.6 V 0.5 2 % 5.2 5.4 5.6 V 0.5 2 % 4.5 4.8 5 V INTVCC Linear Regulator VINTVCC(VIN) Internal VCC Voltage 6V < VBIAS < 38V, VEXTVCC = 0 VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA VINTVCC(EXT) Internal VCC Voltage VEXTVCC = 6V VLDO EXT INTVCC Load Regulation ICC = 0mA to 40mA, VEXTVCC = 6V VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VLDOHYS EXTVCC Hysteresis l 250 mV Oscillator and Phase-Locked Loop fPROG Programmable Frequency RFREQ = 25k RFREQ = 60k RFREQ = 100k 335 105 400 760 465 kHz kHz kHz fLOW Lowest Fixed Frequency VFREQ = 0V 320 350 380 kHz fHIGH Highest Fixed Frequency VFREQ = INTVCC 488 535 585 kHz fSYNC Synchronizable Frequency PLLIN/MODE = External Clock 850 kHz VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPGOOD PGOOD Trip Level VFB with Respect to Set Regulated Voltage l 75 PGOOD Output tPGOOD(DELAY) PGOOD Delay 0.2 0.4 V ±1 μA VFB Ramping Negative Hysteresis –12 –10 2.5 –8 % % VFB Ramping Positive Hysteresis 8 10 2.5 12 % % PGOOD Going High to Low 25 μs VSW1,2 = 12V; VBOOST1,2 – VSW1,2 = 4.5V; FREQ = 0V, Forced Continuous or Pulse-Skipping Mode 55 μA BOOST1 and BOOST2 Charge Pump IBOOST1,2 BOOST Charge Pump Available Output Current Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3787 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3787E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3787I is guaranteed over the –40°C to 125°C operating junction temperature range, the LTC3787H is guaranteed over the –40°C to 150°C operating temperature range and the LTC3787MP is tested and guaranteed over the full –55°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA), where θJA = 43°C/W for the QFN package and θJA = 90°C/W for the SSOP package. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: The LTC3787 is tested in a feedback loop that servos VFB to the output of the error amplifier while maintaining ITH at the midpoint of the current limit range. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: see Minimum On-Time Considerations in the Applications Information section. 3787fc 4 LTC3787 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss vs Output Current Efficiency and Power Loss vs Output Current 100 10000 100 1000 80 90 EFFICIENCY (%) 50 10 40 30 20 1 VIN = 12V VOUT = 24V FIGURE 10 CIRCUIT 10 0 0.01 60 40 0.1 3787 G01 VIN = 12V 1 VOUT = 24V 10 Burst Mode OPERATION FIGURE 10 CIRCUIT 0 0.1 0.1 1 10 0.00001 0.0001 0.001 0.01 OUTPUT CURRENT (A) 3787 G02 BURST EFFICIENCY BURST LOSS Load Step Forced Continuous Mode Efficiency vs Load Current 100 VIN = 12V ILOAD = 2A FIGURE 10 CIRCUIT 99 98 10 30 BURST LOSS PULSE-SKIPPING LOSS FORCED CONTINUOUS MODE LOSS BURST EFFICIENCY PULSE-SKIPPING EFFICIENCY FORCED CONTINUOUS MODE EFFICIENCY 100 50 20 10 0.1 1 OUTPUT CURRENT (A) 1000 70 POWER LOSS (mW) 100 60 POWER LOSS (mW) 70 EFFICIENCY (%) 90 80 EFFICIENCY (%) 10000 LOAD STEP 5A/DIV 97 96 VOUT = 12V VOUT = 24V INDUCTOR CURRENT 5A/DIV 95 94 93 VOUT 500mV/DIV 92 91 90 0 5 15 10 INPUT VOLTAGE (V) 20 200μs/DIV VIN = 12V VOUT = 24V LOAD STEP FROM 100mA TO 5A FIGURE 10 CIRCUIT 25 3787 G03 3787 G04 Load Step Pulse-Skipping Mode Load Step Burst Mode Operation LOAD STEP 5A/DIV LOAD STEP 5A/DIV INDUCTOR CURRENT 5A/DIV INDUCTOR CURRENT 5A/DIV VOUT 500mV/DIV VOUT 500mV/DIV 200μs/DIV VIN = 12V VOUT = 24V LOAD STEP FROM 100mA TO 5A FIGURE 10 CIRCUIT 3787 G05 200μs/DIV VIN = 12V VOUT = 24V LOAD STEP FROM 100mA TO 5A FIGURE 10 CIRCUIT 3787 G06 3787fc 5 LTC3787 TYPICAL PERFORMANCE CHARACTERISTICS Inductor Current at Light Load Soft Start-Up FORCED CONTINUOUS MODE VOUT 5V/DIV Burst Mode OPERATION 5A/DIV PULSE-SKIPPING MODE 0V 5μs/DIV VIN = 12V VOUT = 24V ILOAD = 200μA FIGURE 10 CIRCUIT 3787 G07 20ms/DIV VIN = 12V VOUT = 24V FIGURE 10 CIRCUIT Regulated Feedback Voltage vs Temperature Soft-Start Pull-Up Current vs Temperature 11.0 1.212 1.209 SOFT-START CURRENT (μA) REGULATED FEEDBACK VOLTAGE (V) 3787 G08 1.206 1.203 1.200 1.197 1.194 10.5 10.0 9.5 1.191 1.188 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G09 9.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G10 Shutdown Current vs Temperature 11.0 10.5 Shutdown Current vs Input Voltage 20 VIN = 12V 9.5 9.0 8.5 8.0 7.5 7.0 6.5 SHUTDOWN CURRENT (μA) SHUTDOWN CURRENT (μA) 10.0 15 10 5 6.0 5.5 5.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G11 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 3787 G12 3787fc 6 LTC3787 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown (RUN) Threshold vs Temperature Quiescent Current vs Temperature 1.40 180 1.35 RUN PIN VOLTAGE (V) QUIESCENT CURRENT (μA) VIN = 12V VFB = 1.25V 170 RUN = GND 160 150 140 130 RUN RISING 1.30 1.25 1.20 RUN FALLING 1.15 120 1.10 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 110 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G14 3787 G13 Undervoltage Lockout Threshold vs Temperature INTVCC Line Regulation 4.4 5.5 4.3 5.4 INTVCC RISING 5.3 4.1 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 4.2 4.0 3.9 INTVCC FALLING 3.8 3.7 5.2 5.1 5.0 4.9 4.8 3.6 4.7 3.5 4.6 3.4 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G15 4.5 0 EXTVCC = 0V 5.30 5.25 5.20 EXTVCC = 6V 5.15 35 40 3787 G16 5.8 EXTVCC AND INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 5.40 5.35 15 20 25 30 INPUT VOLTAGE (V) 6.0 VIN = 12V 5.45 10 EXTVCC Switchover and INTVCC Voltages vs Temperature INTVCC vs INTVCC Load Current 5.50 5 5.10 5.6 5.4 INTVCC 5.2 5.0 4.8 EXTVCC RISING 4.6 4.4 EXTVCC FALLING 4.2 5.05 5.00 0 20 40 60 80 100 120 140 160 180 200 INTVCC LOAD CURRENT (mA) 3787 G17 4.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G18 3787fc 7 LTC3787 TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Temperature Oscillator Frequency vs Input Voltage 360 600 FREQ = INTVCC OSCILLATOR FREQUENCY (kHz) 550 FREQUENCY (kHz) FREQ = GND 358 500 450 400 FREQ = GND 350 356 354 352 350 348 346 344 342 340 300 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 5 10 20 25 30 15 INPUT VOLTAGE (V) 35 3787 G19 SENSE Pin Input Current vs Temperature 120 100 PULSE-SKIPPING MODE SENSE CURRENT (μA) MAXIMUM CURRENT SENSE VOLTAGE (mV) Maximum Current Sense Threshold vs ITH Voltage 80 Burst Mode OPERATION 60 40 20 ILIM = GND ILIM = FLOAT ILIM = INTVCC 0 –20 FORCED CONTINUOUS MODE –40 –60 0 0.2 0.4 0.6 0.8 1.0 ITH VOLTAGE (V) 1.2 1.4 260 VSENSE = 12V 240 ILIM = FLOAT 220 SENSE+ PIN 200 180 160 140 120 100 80 60 40 20 SENSE – PIN 0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3787 G22 3787 G21 SENSE Pin Input Current vs VSENSE Voltage VSENSE = 12V SENSE+ PIN ILIM = INTVCC ILIM = FLOAT SENSE CURRENT (μA) SENSE CURRENT (μA) SENSE Pin Input Current vs ITH Voltage 260 240 220 200 180 160 140 120 100 80 60 40 20 0 ILIM = GND SENSE – PIN 0 0.5 ILIM = INTVCC ILIM = FLOAT ILIM = GND 2 1.5 1 ITH VOLTAGE (V) 40 3787 G20 2.5 3 3787 G23 260 240 220 200 180 160 140 120 100 80 60 40 20 0 SENSE+ PIN ILIM = INTVCC ILIM = FLOAT ILIM = GND SENSE – PIN 2.5 ILIM = INTVCC ILIM = FLOAT ILIM = GND 7.5 12.5 17.5 22.5 27.5 32.5 37.5 VSENSE COMMON MODE VOLTAGE (V) 3787 G24 3787fc 8 LTC3787 TYPICAL PERFORMANCE CHARACTERISTICS Charge Pump Charging Current vs Operating Frequency 120 Charge Pump Charging Current vs Switch Voltage 80 ILIM = INTVCC 100 ILIM = FLOAT 80 60 ILIM = GND 40 20 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 80 T = –60°C 70 T = –45°C 60 50 T = 25°C 40 T = 130°C 30 T = 155°C 20 10 0 50 150 250 350 450 550 650 750 OPERATING FREQUENCY (kHz) 3787 G25 PIN FUNCTIONS CHARGE PUMP CHARGING CURRENT (μA) CHARGE PUMP CHARGING CURRENT (μA) MAXIMUM CURRENT SENSE VOLTAGE (mV) Maximum Current Sense Threshold vs Duty Cycle 3787 G26 FREQ = GND 70 FREQ = INTVCC 60 50 40 30 20 10 0 5 10 15 25 30 20 SWITCH VOLTAGE (V) 35 40 3787 G27 (QFN/SSOP) FREQ (Pin 1/Pin 4): Frequency Control Pin for the Internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting the pin to INTVCC forces the VCO to a fixed high frequency of 535kHz. The frequency can be programmed from 50kHz to 900kHz by connecting a resistor from the FREQ pin to GND. The resistor and an internal 20μA source current create a voltage used by the internal oscillator to set the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. PHASMD (Pin 2/Pin 5): This pin can be floated, tied to SGND, or tied to INTVCC to program the phase relationship between the rising edges of BG1 and BG2, as well as the phase relationship between BG1 and CLKOUT. CLKOUT (Pin 3/Pin 6): A Digital Output Used for Daisychaining Multiple LTC3787 ICs in Multiphase Systems. The PHASMD pin voltage controls the relationship between BG1 and CLKOUT. This pin swings between SGND and INTVCC. PLLIN/MODE (Pin 4/Pin 7): External Synchronization Input to Phase Detector and Forced Continuous Mode Input. When an external clock is applied to this pin, it will force the controller into forced continuous mode of operation and the phase-locked loop will force the rising BG1 signal to be synchronized with the rising edge of the external clock. When not synchronizing to an external clock, this input determines how the LTC3787 operates at light loads. Pulling this pin to ground selects Burst Mode operation. An internal 100k resistor to ground also invokes Burst Mode operation when the pin is floated. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 1.2V and less than INTVCC – 1.3V selects pulse-skipping operation. This can be done by adding a 100k resistor between the PLLIN/ MODE pin and INTVCC. SGND (Pin 5/Pin 8): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at a single point. RUN (Pin 6/Pin 9): Run Control Input. Forcing this pin below 1.28V shuts down the controller. Forcing this pin below 0.7V shuts down the entire LTC3787, reducing quiescent current to approximately 8μA. An external resistor divider connected to VIN can set the threshold for converter operation. Once running, a 4.5μA current is sourced from the RUN pin allowing the user to program hysteresis using the resistor values. 3787fc 9 LTC3787 PIN FUNCTIONS (QFN/SSOP) SS (Pin 7/Pin 10): Output Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage during start-up. PGND (Pin 19/Pin 22): Driver Power Ground. Connects to the sources of bottom (main) N-channel MOSFETs and the (–) terminal(s) of CIN and COUT. SENSE2– , SENSE1– (Pin 8, Pin 28/Pin 11, Pin 3): Negative Current Sense Comparator Input. The (–) input to the current comparator is normally connected to the negative terminal of a current sense resistor connected in series with the inductor. BG2, BG1 (Pin 16, Pin 21/Pin 19, Pin 24): Bottom Gate. Connect to the gate of the main N-channel MOSFET. SENSE2+, SENSE1+ (Pin 9, Pin 27/Pin 12, Pin 2): Positive Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the positive terminal of a current sense resistor. The current sense resistor is normally placed at the input of the boost controller in series with the inductor. This pin also supplies power to the current comparator. The common mode voltage range on SENSE+ and SENSE– pins is 2.5V to 38V (40V abs max). VFB (Pin 10/Pin 13): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. ITH (Pin 11/Pin 14): Current Control Threshold and Error Amplifier Compensation Point. The voltage on this pin sets the current trip threshold. NC (Pin 12/Pin 15): No Connect. SW2, SW1 (Pin 13, Pin 24/Pin 16, Pin 27): Switch Node. Connect to the source of the synchronous N-channel MOSFET, the drain of the main N-channel MOSFET and the inductor. TG2, TG1 (Pin 14, Pin 23/Pin 17, Pin 26): Top Gate. Connect to the gate of the synchronous N-channel MOSFET. BOOST2, BOOST1 (Pin 15, Pin 22/Pin 18, Pin 25): Floating power supply for the synchronous N-channel MOSFET. Bypass to SW with a capacitor and supply with a Schottky diode connected to INTVCC. INTVCC (Pin 17/Pin 20): Output of Internal 5.4V LDO. Power supply for control circuits and gate drivers. Decouple this pin to GND with a minimum 4.7μF low ESR ceramic capacitor. EXTVCC (Pin 18/Pin 21): External Power Input. When this pin is between 4.8V and 6V, an internal switch bypasses the internal regulator and supply power to INTVCC directly from EXTVCC. Do not float this pin. It can be connected to ground when not used. VBIAS (Pin 20/Pin 23): Main Supply Pin. It is normally tied to the input supply VIN or to the output of the boost converter. A bypass capacitor should be tied between this pin and the signal ground pin. The operating voltage range on this pin is 4.5V to 38V (40V abs max). PGOOD (Pin 25/Pin 28): Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is more than ±10 % away from the regulated output voltage. To avoid false trips the output voltage must be outside the range for 25μs before this output is activated. ILIM (Pin 26/Pin 1): Current Comparator Sense Voltage Range Input. This pin is used to set the peak current sense voltage in the current comparator. Connect this pin to SGND, open, and INTVCC to set the peak current sense voltage to 50mV, 75mV and 100mV, respectively. GND (Exposed Pad Pin 29) UFD Package: Ground. Must be soldered to the PCB for rated thermal performance. 3787fc 10 LTC3787 BLOCK DIAGRAM PHASMD INTVCC CLKOUT DUPLICATE FOR SECOND CONTROLLER CHANNEL S BOOST DB TG CB Q R SHDN SWITCHING LOGIC AND CHARGE PUMP 20μA FREQ CLK2 VCO 0.425V CLK1 + COUT INTVCC BG SLEEP PGND – PFD – ICMP + – + + IREV – + – VOUT SW L SENSE – 2mV 2.8V 0.7V PLLIN/ MODE SENSE+ SLOPE COMP SYNC DET VIN CIN + 100k SENS LO – 2.5V ILIM VFB CURRENT LIMIT + EA – – VBIAS SHDN EXTVCC EN 5.4V LDO EN – 0.5μA/ 4.5μA + 10μA 3.8V 1.32V 11V – + – 1.32V ITH PGOOD CC CC2 RC – + 4.8V 1.2V SS + OV 5.4V LDO RSENSE VFB INTVCC SGND SHDN SENS LO RUN + SS 1.08V – CSS 3787 BD OPERATION Main Control Loop The LTC3787 uses a constant-frequency, current mode step-up architecture with the two controller channels operating out of phase. During normal operation, each external bottom MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The error amplifier compares the output voltage feedback signal at the VFB pin (which is generated with an external resistor divider connected across the output voltage, VOUT , to ground), to the internal 1.200V reference voltage. In a boost converter, the required inductor current is determined by the load current, VIN and VOUT . When the load current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current in each channel matches the new requirement based on the new load current. After the bottom MOSFET is turned off each cycle, the top MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator, IR, or the beginning of the next clock cycle. 3787fc 11 LTC3787 OPERATION INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is tied to a voltage less than 4.8V, the VBIAS LDO (low dropout linear regulator) supplies 5.4V from VBIAS to INTVCC. If EXTVCC is taken above 4.8V, the VBIAS LDO is turned off and an EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO supplies 5.4V from EXTVCC to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from an external source, thus removing the power dissipation of the VBIAS LDO. Shutdown and Start-Up (RUN and SS Pins) The two internal controllers of the LTC3787 can be shut down using the RUN pin. Pulling this pin below 1.28V shuts down the main control loops for both phases. Pulling this pin below 0.7V disables both controllers and most internal circuits, including the INTVCC LDOs. In this state, the LTC3787 draws only 8μA of quiescent current. NOTE: Do not apply a heavy load for an extended time while the chip is in shutdown. The top MOSFETs will be turned off during shutdown and the output load may cause excessive dissipation in the body diodes. The RUN pin may be externally pulled up or driven directly by logic. When driving the RUN pin with a low impedance source, do not exceed the absolute maximum rating of 8V. The RUN pin has an internal 11V voltage clamp that allows the RUN pin to be connected through a resistor to a higher voltage (for example, VIN), as long as the maximum current into the RUN pin does not exceed 100μA. An external resistor divider connected to VIN can set the threshold for converter operation. Once running, a 4.5μA current is sourced from the RUN pin allowing the user to program hysteresis using the resistor values. The start-up of the controller’s output voltage VOUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 1.2V internal reference, the LTC3787 regulates the VFB voltage to the SS pin voltage instead of the 1.2V reference. This allows the SS pin to be used to program a soft-start by connecting an external capacitor from the SS pin to SGND. An internal 10μA pull-up current charges this capacitor creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 1.2V (and beyond up to INTVCC), the output voltage rises smoothly to its final value. Light Load Current Operation—Burst Mode Operation, Pulse-Skipping or Continuous Conduction (PLLIN/MODE Pin) The LTC3787 can be enabled to enter high efficiency Burst Mode operation, constant-frequency, pulse-skipping mode or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to ground (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/ MODE pin to a DC voltage greater than 1.2V and less than INTVCC – 1.3V. When the controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to approximately 30% of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the required current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. In sleep mode much of the internal circuitry is turned off and the LTC3787 draws only 135μA of quiescent current. In sleep mode the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low and the controller resumes normal operation by turning on the bottom external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the top external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous current operation. 3787fc 12 LTC3787 OPERATION In forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see the Frequency Selection and Phase-Locked Loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry, as it maintains constant-frequency operation independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode, the LTC3787 operates in PWM pulse-skipping mode at light loads. In this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external bottom MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and PLLIN/MODE Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3787’s controllers can be selected using the FREQ pin. If the PLLIN/MODE pin is not being driven by an external clock source, the FREQ pin can be tied to SGND, tied to INTVCC, or programmed through an external resistor. Tying FREQ to SGND selects 350kHz while tying FREQ to INTVCC selects 535kHz. Placing a resistor between FREQ and SGND allows the frequency to be programmed between 50kHz and 900kHz, as shown in Figure 6. A phase-locked loop (PLL) is available on the LTC3787 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. The LTC3787’s phase detector adjusts the voltage (through an internal lowpass filter) of the VCO input to align the turn-on of the first controller’s external bottom MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of the second controller’s external bottom MOSFET is 180 or 240 degrees out-of-phase to the rising edge of the external clock source. The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock’s to the rising edge of BG1. The ability to prebias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. The typical capture range of the LTC3787’s PLL is from approximately 55kHz to 1MHz, and is guaranteed to lock to an external clock source whose frequency is between 75kHz and 850kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling). PolyPhase Applications (CLKOUT and PHASMD Pins) The LTC3787 features two pins, CLKOUT and PHASMD, that allow other controller ICs to be daisychained with the LTC3787 in PolyPhase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. The PHASMD pin is used to adjust the phase of the CLKOUT signal as well as the relative phases between the two internal controllers, as summarized in Table 1. The phases are calculated relative to the zero degrees phase being defined as the rising edge of the bottom gate driver output of controller 1 (BG1). Depending on the phase selection, a PolyPhase application with 3787fc 13 LTC3787 OPERATION multiple LTC3787s can be configured for 2-, 3-, 4- , 6- and 12-phase operation. Power Good CLKOUT is disabled when the controller is in shutdown or in sleep mode. The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 1.2V reference voltage. The PGOOD pin is also pulled low when the corresponding RUN pin is low (shut down). When the VFB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V (abs max). Operation When VIN > Regulated VOUT Operation at Low SENSE Pin Common Mode Voltage When VIN rises above the regulated VOUT voltage, the boost controller can behave differently depending on the mode, inductor current and VIN voltage. In forced continuous mode, the loop works to keep the top MOSFET on continuously once VIN rises above VOUT. The internal charge pump delivers current to the boost capacitor to maintain a sufficiently high TG voltage. The amount of current the charge pump can deliver is characterized by two curves in the Typical Performance Characteristics section. The current comparator in the LTC3787 is powered directly from the SENSE+ pin. This enables the common mode voltage of the SENSE+ and SENSE– pins to operate at as low as 2.5V, which is below the UVLO threshold. The figure on the first page shows a typical application in which the controller’s VBIAS is powered from VOUT while the VIN supply can go as low as 2.5V. If the voltage on SENSE+ drops below 2.5V, the SS pin will be held low. When the SENSE voltage returns to the normal operating range, the SS pin will be released, initiating a new soft-start cycle. Table 1. VPHASMD CONTROLLER 2 PHASE (°C) CLKOUT PHASE (°C) GND 180 60 Floating 180 90 INTVCC 240 120 In pulse-skipping mode, if VIN is between 100% and 110% of the regulated VOUT voltage, TG turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. This threshold current is set to approximately 6%, 4% or 3% of the maximum ILIM current when the ILIM pin is grounded, floating or tied to INTVCC, respectively. If the controller is programmed to Burst Mode operation under this same VIN window, then TG remains off regardless of the inductor current. If VIN rises above 110% of the regulated VOUT voltage in any mode, the controller turns on TG regardless of the inductor current. In Burst Mode operation, however, the internal charge pump turns off if the chip is asleep. With the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient TG voltage needed to keep the top MOSFET completely on. To prevent excessive power dissipation across the body diode of the top MOSFET in this situation, the chip can be switched over to forced continuous mode to enable the charge pump or a Schottky diode can also be placed in parallel to the top MOSFET. BOOST Supply Refresh and Internal Charge Pump Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each cycle through an external diode when the bottom MOSFET turns on. There are two considerations for keeping the BOOST supply at the required bias level. During start-up, if the bottom MOSFET is not turned on within 100μs after UVLO goes low, the bottom MOSFET will be forced to turn on for ~400ns. This forced refresh generates enough BOOST-SW voltage to allow the top MOSFET ready to be fully enhanced instead of waiting for the initial few cycles to charge up. There is also an internal charge pump that keeps the required bias on BOOST. The charge pump always operates in both forced continuous mode and pulse-skipping mode. In Burst Mode operation, the charge pump is turned off during sleep and enabled when the chip wakes up. The internal charge pump can normally supply a charging current of 55μA. 3787fc 14 LTC3787 APPLICATIONS INFORMATION The Typical Application on the first page is a basic LTC3787 application circuit. LTC3787 can be configured to use either inductor DCR (DC resistance) sensing or a discrete sense resistor (RSENSE) for current sensing. The choice between the two current sensing schemes is largely a design tradeoff between cost, power consumption and accuracy. DCR sensing is becoming popular because it does not require current sensing resistors and is more power-efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. Note that the two controller channels of the LTC3787 should be designed with the same components. The SENSE+ pin also provides power to the current comparator. It draws ~200μA during normal operation. There is a small base current of less than 1μA that flows into the SENSE– pin. The high impedance SENSE– input to the current comparators allows accurate DCR sensing. Filter components mutual to the sense lines should be placed close to the LTC3787, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. TO SENSE FILTER, NEXT TO THE CONTROLLER SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 2.5V to 38V. The current sense resistor is normally placed at the input of the boost controller in series with the inductor. VBIAS VIN INDUCTOR OR RSENSE 3787 F01 Figure 1. Sense Lines Placement with Inductor or Sense Resistor VBIAS VIN VIN SENSE+ SENSE+ C1 (OPTIONAL) R2 DCR SENSE– SENSE– INTVCC INTVCC R1 LTC3787 LTC3787 BOOST BOOST TG TG VOUT SW INDUCTOR L VOUT SW BG BG SGND SGND 3787 F02b 3787 F02a PLACE C1 NEAR SENSE PINS (2a) Using a Resistor to Sense Current (R1||R2) • C1 = L DCR RSENSE(EQ) = DCR • R2 R1 + R2 (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current 3787fc 15 LTC3787 APPLICATIONS INFORMATION Sense Resistor Current Sensing Inductor DCR Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. For applications requiring the highest possible efficiency at high load currents, the LTC3787 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor can be less than 1mΩ for high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor could reduce the efficiency by a few percent compared to DCR sensing. The current comparator has a maximum threshold VSENSE(MAX). When the ILIM pin is grounded, floating or tied to INTVCC, the maximum threshold is set to 50mV, 75mV or 100mV, respectively. The current comparator threshold sets the peak of the inductor current, yielding a maximum average inductor current, IMAX, equal to the peak value less half the peak-to-peak ripple current, ΔIL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) ΔI IMAX + L 2 The actual value of IMAX for each channel depends on the required output current IOUT(MAX) and can be calculated using: ⎛ IOUT(MAX) ⎞ ⎛ VOUT ⎞ IMAX = ⎜ ⎟ • ⎜⎝ V ⎟⎠ 2 ⎝ ⎠ IN When using the controller in low VIN and very high voltage output applications, the maximum inductor current and correspondingly the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty factor. A curve is provided in the Typical Performance Characteristics section to estimate this reduction in peak inductor current level depending upon the operating duty factor. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature. Consult the manufacturers’ data sheets for detailed information. Using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: VSENSE(MAX) ΔI IMAX + L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (VSENSE(MAX)). RSENSE(EQUIV) = Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for the maximum inductor temperature (TL(MAX)) is 100°C. 3787fc 16 LTC3787 APPLICATIONS INFORMATION To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV) DCRMAX at TL(MAX) C1 is usually selected to be in the range of 0.1μF to 0.47μF. This forces R1|| R2 to around 2k, reducing error that might have been caused by the SENSE– pin’s ±1μA current. The equivalent resistance R1|| R2 is scaled to the room temperature inductance and maximum DCR: R1||R2 = L (DCR at 20°C) • C1 The sense resistor values are: R1= R1• RD R1||R2 ; R2 = RD 1− RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at VIN = 1/2VOUT : (VOUT − VIN ) • VIN R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. PLOSS _ R1 = Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. Why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and switching losses. Also, at higher frequency the duty cycle of body diode conduction is higher, which results in lower efficiency. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance or frequency and increases with higher VIN: ΔIL = VIN f •L ⎛ VIN ⎞ ⎜⎝ 1− V ⎟⎠ OUT Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL occurs at VIN = 1/2VOUT. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ΔIL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Once the value of L is known, an inductor with low DCR and low core losses should be selected. 3787fc 17 LTC3787 APPLICATIONS INFORMATION Power MOSFET Selection Two external power MOSFETs must be selected for each controller in the LTC3787: one N-channel MOSFET for the bottom (main) switch, and one N-channel MOSFET for the top (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.4V during start-up (see EXTVCC pin connection). Consequently, logic-level threshold MOSFETs must be used in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturer’s data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT − VIN VOUT Synchronous Switch Duty Cycle = VIN VOUT If the maximum output current is IOUT(MAX) and each channel takes one half of the total output current, the MOSFET power dissipations in each channel at maximum output current are given by: 2 ⎛ IOUT(MAX) ⎞ (V − V )V PMAIN = OUT 2IN OUT • ⎜ ⎟ • (1+ δ ) 2 ⎝ ⎠ V IN • RDS(ON) + k • V 3OUT • IOUT(MAX) 2 • VIN • CMILLER • f V PSYNC = IN VOUT 2 ⎛ IOUT(MAX) ⎞ •⎜ ⎟ • (1+ δ ) • RDS(ON) 2 ⎝ ⎠ where δ is the temperature dependency of RDS(ON) (approximately 1Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. Both MOSFETs have I2R losses while the bottom N-channel equation includes an additional term for transition losses, which are highest at low input voltages. For high VIN the high current efficiency generally improves with larger MOSFETs, while for low VIN the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the bottom switch duty factor is low or during overvoltage when the synchronous switch is on close to 100% of the period. The term (1+ δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. 3787fc 18 LTC3787 APPLICATIONS INFORMATION The input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. The input capacitor CIN voltage rating should comfortably exceed the maximum input voltage. Although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. Be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. The value of CIN is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. The required amount of input capacitance is also greatly affected by the duty cycle. High output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of DC current and ripple current. In a boost converter, the output has a discontinuous current, so COUT must be capable of reducing the output voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady ripple voltage due to charging and discharging the bulk capacitance in a single phase boost converter is given by: VRIPPLE = IOUT(MAX) • (VOUT − VIN(MIN) ) COUT • VOUT • f V where COUT is the output filter capacitor. The steady ripple due to the voltage drop across the ESR is given by: ΔVESR = IL(MAX) • ESR The LTC3787 is configured as a 2-phase single output converter where the outputs of the two channels are connected together and both channels have the same duty cycle. With 2-phase operation, the two channels are operated 180 degrees out-of-phase. This effectively interleaves the output capacitor current pulses, greatly reducing the output capacitor ripple current. As a result, the ESR requirement of the capacitor can be relaxed. Because the ripple current in the output capacitor is a square wave, the ripple current requirements for the output capacitor depend on the duty cycle, the number of phases and the maximum output current. Figure 3 illustrates the normalized output capacitor ripple current as a function of duty cycle in a 2-phase configuration. To choose a ripple current rating for the output capacitor, first establish the duty cycle range based on the output voltage and range of input voltage. Referring to Figure 3, choose the worstcase high normalized ripple current as a percentage of the maximum load current. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient. Capacitors are now available with low ESR and high ripple current ratings (e.g., OS-CON and POSCAP). IORIPPLE /IOUT CIN and COUT Selection 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0.1 1-PHASE 2-PHASE 0.2 0.3 0.4 0.5 0.6 0.7 0.8 DUTY CYCLE OR (1-VIN /VOUT) 0.9 3787 F03 Figure 3. Normalized Output Capacitor Ripple Current (RMS) for a Boost Converter PolyPhase Operation For output loads that demand high current, multiple LTC3787s can be cascaded to run out-of-phase to provide more output current and at the same time to reduce input and output voltage ripple. The PLLIN/MODE pin allows the LTC3787 to synchronize to the CLKOUT signal of another LTC3787. The CLKOUT signal can be connected to the PLLIN/MODE pin of the following LTC3787 stage to line up both the frequency and the phase of the entire system. 3787fc 19 LTC3787 APPLICATIONS INFORMATION Tying the PHASMD pin to INTVCC, SGND or floating generates a phase difference (between PLLIN/MODE and CLKOUT) of 240°, 60° or 90°, respectively, and a phase difference (between CH1 and CH2) of 120°, 180° 0,240 VOUT or 180°. Figure 4 shows the connections necessary for 3-, 4-, 6- or 12-phase operation. A total of 12 phases can be cascaded to run simultaneously out-of-phase with respect to each other. 120, CHANNEL 2 NOT USED +120 PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PHASMD LTC3787 PHASMD LTC3787 SS RUN VFB SS RUN VFB ITH ITH INTVCC (4a) 3-Phase Operation 0,180 VOUT 90,270 +90 PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PHASMD LTC3787 PHASMD LTC3787 SS RUN VFB SS RUN VFB ITH ITH (4b) 4-Phase Operation 0,180 VOUT 60,240 +60 120,300 +60 PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PHASMD LTC3787 PHASMD LTC3787 PHASMD LTC3787 SS RUN VFB SS RUN VFB ITH SS RUN VFB ITH ITH (4c) 6-Phase Operation 0,180 VOUT 60,240 +60 120,300 +60 +90 PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PHASMD LTC3787 PHASMD LTC3787 PHASMD LTC3787 SS RUN VFB VFB ITH 210,30 SS RUN VFB ITH 270,90 +60 SS RUN ITH 330,150 +60 PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PLLIN/MODE CLKOUT PHASMD LTC3787 PHASMD LTC3787 PHASMD LTC3787 SS RUN VFB ITH SS RUN VFB ITH SS RUN VFB ITH 3787 F04 (4d) 12-Phase Operation Figure 4. PolyPhase Operation 3787fc 20 LTC3787 APPLICATIONS INFORMATION Setting Output Voltage INTVCC Regulators The LTC3787 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 5. The regulated output voltage is determined by: The LTC3787 features two separate internal P-channel low dropout linear regulators (LDO) that supply power at the INTVCC pin from either the VBIAS supply pin or the EXTVCC pin depending on the connection of the EXTVCC pin. INTVCC powers the gate drivers and much of the LTC3787’s internal circuitry. The VBIAS LDO and the EXTVCC LDO regulate INTVCC to 5.4V. Each of these can supply at least 50mA and must be bypassed to ground with a minimum of 4.7μF ceramic capacitor. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. ⎛ R ⎞ VOUT = 1.2V ⎜ 1+ B ⎟ ⎝ RA ⎠ Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Also keep the VFB node as small as possible to avoid noise pickup. VOUT RB LTC3787 VFB RA 3787 F05 Figure 5. Setting Output Voltage Soft-Start (SS Pin) The start-up of VOUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the internal 1.2V reference, the LTC3787 regulates the VFB pin voltage to the voltage on the SS pin instead of 1.2V. Soft-start is enabled by simply connecting a capacitor from the SS pin to ground, as shown in Figure 6. An internal 10μA current source charges the capacitor, providing a linear ramping voltage at the SS pin. The LTC3787 will regulate the VFB pin (and hence, VOUT) according to the voltage on the SS pin, allowing VOUT to rise smoothly from VIN to its final regulated value. The total soft-start time will be approximately: t SS = CSS • High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3787 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the VBIAS LDO or the EXTVCC LDO. When the voltage on the EXTVCC pin is less than 4.8V, the VBIAS LDO is enabled. In this case, power dissipation for the IC is highest and is equal to VBIAS • IINTVCC. The gate charge current is dependent on operating frequency, as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, at 70°C ambient temperature, the LTC3787 INTVCC current is limited to less than 32mA in the QFN package from a 40V VBIAS supply when not using the EXTVCC supply: TJ = 70°C + (32mA)(40V)(43°C/W) = 125°C In an SSOP package, the INTVCC current is limited to less than 15mA from a 40V supply when not using the EXTVCC supply: TJ = 70°C + (15mA)(40V)(90°C/W) = 125°C 1.2V 10µA LTC3787 SS CSS SGND 3787 F06 Figure 6. Using the SS Pin to Program Soft-Start To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (PLLIN/MODE = INTVCC) at maximum VIN. When the voltage applied to EXTVCC rises above 4.8V, the VIN LDO is turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to 3787fc 21 LTC3787 APPLICATIONS INFORMATION EXTVCC remains above 4.55V. The EXTVCC LDO attempts to regulate the INTVCC voltage to 5.4V, so while EXTVCC is less than 5.4V, the LDO is in dropout and the INTVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than 5.4V, up to an absolute maximum of 6V, INTVCC is regulated to 5.4V. Significant thermal gains can be realized by powering INTVCC from an external supply. Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to 79°C in a QFN package: TJ = 70°C + (32mA)(5V)(43°C/W) = 77°C and from 125°C to 74°C in an SSOP package: TJ = 70°C + (15mA)(5V)(90°C/W) = 77°C If more current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Make sure that in all cases EXTVCC ≤ VBIAS (even at start-up and shutdown). The following list summarizes possible connections for EXTVCC: EXTVCC Grounded. This will cause INTVCC to be powered from the internal 5.4V regulator resulting in an efficiency penalty at high input voltages. EXTVCC Connected to an External Supply. If an external supply is available in the 5V to 6V range, it may be used to provide power. Ensure that EXTVCC is always lower than VBIAS. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Block Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate and source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VOUT and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the output voltage: VBOOST = VOUT + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VOUT(MAX). The external diode DB can be a Schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. Pay close attention to the reverse leakage at high temperatures where it generally increases substantially. Each of the topside MOSFET drivers includes an internal charge pump that delivers current to the bootstrap capacitor from the BOOST pin. This charge current maintains the bias voltage required to keep the top MOSFET on continuously during dropout/overvoltage conditions. The Schottky/silicon diodes selected for the topside drivers should have a reverse leakage less than the available output current the charge pump can supply. Curves displaying the available charge pump current under different operating conditions can be found in the Typical Performance Characteristics section. A leaky diode DB in the boost converter can not only prevent the top MOSFET from fully turning on but it can also completely discharge the bootstrap capacitor CB and create a current path from the input voltage to the BOOST pin to INTVCC. This can cause INTVCC to rise if the diode leakage exceeds the current consumption on INTVCC. This is particularly a concern in Burst Mode operation where the load on INTVCC can be very small. The external Schottky or silicon diode should be carefully chosen such that INTVCC never gets charged up much higher than its normal regulation voltage. Fault Conditions: Overtemperature Protection At higher temperatures, or in cases where the internal power dissipation causes excessive self heating on-chip (such as an INTVCC short to ground), the overtemperature shutdown circuitry will shut down the LTC3787. When the junction temperature exceeds approximately 170°C, the overtemperature circuitry disables the INTVCC LDO, causing the INTVCC supply to collapse and effectively shut down 3787fc 22 LTC3787 APPLICATIONS INFORMATION the entire LTC3787 chip. Once the junction temperature drops back to approximately 155°C, the INTVCC LDO turns back on. Long term overstress (TJ > 125°C) should be avoided as it can degrade the performance or shorten the life of the part. Since the shutdown may occur at full load, beware that the load current will result in high power dissipation in the body diodes of the top MOSFETs. In this case, PGOOD output may be used to turn the system load off. Phase-Locked Loop and Frequency Synchronization The LTC3787 has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a lowpass filter and a voltage-controlled oscillator (VCO). This allows the turn-on of the bottom MOSFET of channel 1 to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The turn-on of channel 2’s bottom MOSFET is thus 180 degrees out-of-phase with the external clock. The phase detector is an edge-sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO input. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the VCO input. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the internal filter capacitor, CLP , holds the voltage at the VCO input. Typically, the external clock (on the PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.2V. Note that the LTC3787 can only be synchronized to an external clock whose frequency is within range of the LTC3787’s internal VCO, which is nominally 55kHz to 1MHz. This is guaranteed to be between 75kHz and 850kHz. Rapid phase locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased at a frequency corresponding to the frequency set by the FREQ pin. Once prebiased, the PLL only needs to adjust the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. 1000 900 FREQUENCY (kHz) 800 700 600 500 400 300 200 100 0 15 25 35 45 55 65 75 85 95 105 115 125 FREQ PIN RESISTOR (k) 3787 F07 Figure 7. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin 3787fc 23 LTC3787 APPLICATIONS INFORMATION Table 2 summarizes the different states in which the FREQ pin can be used. INTVCC regulator current, 3) I2R losses, 4) bottom MOSFET transition losses, 5) body diode conduction losses. Table 2. 1. The VBIAS current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VBIAS current typically results in a small (<0.1%) loss. FREQ PIN PLLIN/MODE PIN FREQUENCY 0V DC Voltage 350kHz INTVCC DC Voltage 535kHz Resistor DC Voltage 50kHz to 900kHz Any of the Above External Clock Phase Locked to External Clock Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3787 is capable of turning on the bottom MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit. In forced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles but the output will continue to be regulated. More cycles will be skipped when VIN increases. Once VIN rises above VOUT, the loop keeps the top MOSFET continuously on. The minimum on-time for the LTC3787 is approximately 110ns. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. 3. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor, inductor and PC board traces and cause the efficiency to drop at high output currents. 4. Transition losses apply only to the bottom MOSFET(s), and become significant only when operating at low input voltages. Transition losses can be estimated from: V OUT3 IOUT(MAX) Transition Loss = (1.7) • •CRSS • f VIN 2 5. Body diode conduction losses are more significant at higher switching frequency. During the dead time, the loss in the top MOSFETs is IOUT • VDS, where VDS is around 0.7V. At higher switching frequency, the dead time becomes a good percentage of switching cycle and causes the efficiency to drop. Other hidden losses, such as copper trace and internal battery resistances, can account for an additional efficiency degradation in portable systems. It is very important to include these system-level losses during the design phase. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3787 circuits: 1) IC VBIAS current, 2) 3787fc 24 LTC3787 APPLICATIONS INFORMATION Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of COUT . ΔILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior, but it also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 10 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly to optimize transient response once the final PC layout is complete and the particular output capacitor type and value have been determined. The output capacitors must be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET and load resistor directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus, a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. Design Example As a design example, assume VIN = 12V (nominal), VIN = 22V (max), VOUT = 24V, IOUT(MAX) = 8A, VSENSE(MAX) = 75mV, and f = 350kHz. The components are designed based on single channel operation. The inductance value is chosen first based on a 30% ripple current assumption. Tie the PLLIN/MODE pin to GND, generating 350kHz operation. The minimum inductance for 30% ripple current is: VIN ⎛ VIN ⎞ 1− f • L ⎜⎝ VOUT ⎟⎠ The largest ripple happens when VIN = 1/2VOUT = 12V, where the average maximum inductor current for each channel is: ΔIL = ⎛ IOUT(MAX) ⎞ ⎛ VOUT ⎞ IMAX = ⎜ ⎟ • ⎜⎝ V ⎟⎠ = 8A 2 ⎝ ⎠ IN 3787fc 25 LTC3787 APPLICATIONS INFORMATION A 6.8μH inductor will produce a 31% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 9.25A. The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: RSENSE ≤ 75mV = 0.008Ω 9.25A Choosing 1% resistors: RA = 5k and RB = 95.3k yields an output voltage of 24.072V. The power dissipation on the top side MOSFET in each channel can be easily estimated. Choosing a Vishay Si7848BDP MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF. At maximum input voltage with T (estimated) = 50°C: PMAIN = (24V – 12V) 24V 2 (12V) • (4A)2 • ⎡⎣1+ (0.005)(50°C – 25°C)⎤⎦ • 0.008Ω 4A (150pF)(350kHz) = 0.7W 12V COUT is chosen to filter the square current in the output. The maximum output current peak is: + (1.7)(24V)3 ⎛ 31% ⎞ IOUT(PEAK) = 8 • ⎜ 1+ = 9.3A ⎝ 2 ⎟⎠ A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 46.5mV (assuming ESR dominate ripple). PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 8. Figure 9 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2 and the top N-channel MOSFETs MTOP1 and MTOP2 in one compact area with COUT . 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The path formed by the bottom N-channel MOSFET and the capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the source terminals of the bottom MOSFETs. 3. Does the LTC3787 VFB pin’s resistive divider connect to the (+) terminal of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground and placed close to the VFB pin. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2) and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposites channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and, therefore, should be kept on the output side of the LTC3787 and occupy a minimal PC trace area. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. 3787fc 26 LTC3787 APPLICATIONS INFORMATION SENSE1– SENSE1+ LTC3787 fIN PHSMD CLKOUT FREQ PLLIN/MODE ILIM PGOOD SW1 TG1 VPULL-UP L1 RSENSE1 CB1 BOOST1 + M1 M2 BG1 VBIAS + GND PGND EXTVCC INTVCC SGND RUN VFB ITH BG2 CB2 M3 VIN + M4 VOUT BOOST2 SS TG2 SW2 SENSE2+ SENSE2– L2 RSENSE2 3787 F08 Figure 8. Recommended Printed Circuit Layout Diagram RSENSE1 L1 SW1 VOUT VIN RIN CIN COUT RSENSE2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. RL L2 SW2 3787 F09 Figure 9. Branch Current Waveforms 3787fc 27 LTC3787 APPLICATIONS INFORMATION PC Board Layout Debugging Start with one controller on at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold— typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point while the other channel is turning on its bottom MOSFET. This occurs around the 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation with high duty cycle. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. An embarrassing problem which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hook-up will still be maintained, but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage. 3787fc 28 LTC3787 TYPICAL APPLICATIONS SENSE1– PGOOD SENSE1+ ILIM TG1 PHASMD SW1 CLKOUT PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN INTVCC MTOP1 SS L1 3.3μH RSENSE1 4mΩ COUTB1 220μF MBOT1 CINT 4.7μF CIN 22μF s2 D2 ITH + D1 PGND RITH, 8.66k COUTA1 22μF s4 CB1, 0.1μF VBIAS INTVCC FREQ CSS, 0.1μF CITH, 15nF 100k BG2 VIN 5V TO 24V VOUT 24V, 10A* MBOT2 CB2, 0.1μF CITHA, 220pF L2 3.3μH BOOST2 RSENSE2 4mΩ SW2 RA, 12.1k RB 232k VFB SENSE2+ SENSE2– TG2 MTOP2 COUTA2 22μF s4 + COUTA1 6.8μF ×4 + COUTB2 220μF 3787 F10 CIN, COUTA1, COUTA2: TDK C4532X5R1E226M COUTB1, COUTB2: SANYO, 50CE220LX L1, L2: PULSE PA1494.362NL MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H D1, D2: BAS140W *WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. Figure 10. High Efficiency 2-Phase 24V Boost Converter SENSE1– PGOOD SENSE1+ TG1 ILIM PHASMD SW1 CLKOUT PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN INTVCC MTOP1 SS L1 3.3μH RSENSE1 4mΩ MBOT1 D1 CINT 4.7μF CIN 6.8μF ×4 PGND D2 RITH, 8.66k ITH COUTB1 220μF CB1, 0.1μF VBIAS INTVCC FREQ CSS, 0.1μF CITH, 15nF 100k BG2 VIN 5V TO 28V VOUT 28V, 8A MBOT2 CB2, 0.1μF CITHA, 220pF L2 3.3μH BOOST2 RSENSE2 4mΩ SW2 RA, 12.1k RB 271k VFB SENSE2+ SENSE2– TG2 CIN, COUTA1, COUTA2: TDK C4532X7RIH685K COUTB1, COUTB2: SANYO, 50CE220LX L1, L2: PULSE PA1494.362NL MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H D1, D2: BAS140W MTOP2 COUTA2 6.8μF ×4 + COUTB2 220μF 3787 F11 Figure 11. High Efficiency 2-Phase 28V Boost Converter 3787fc 29 LTC3787 TYPICAL APPLICATIONS SENSE1– SENSE1+ ILIM 100k PGOOD TG1 PHASMD SW1 CLKOUT PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN MTOP1 SS L1 10.2μH RSENSE1 5mΩ COUTB1 220μF MBOT1 CINT 4.7μF CIN 6.8μF ×4 D2 ITH + D1 PGND RITH, 3.57k COUTA1 6.8μF ×4 CB1, 0.1μF VBIAS INTVCC FREQ CSS, 0.1μF CITH, 15nF INTVCC BG2 VIN 5V TO 36V VOUT 36V, 6A MBOT2 CB2, 0.1μF CITHA, 220pF L2 10.2μH BOOST2 RSENSE2 5mΩ SW2 RA, 12.1k RB 348k VFB SENSE2+ SENSE2– TG2 MTOP2 COUTA2 6.8μF ×4 + COUTA1 6.8μF ×4 + COUTB2 220μF 3787 F12 CIN, COUTA1, COUTA2: TDK C4532X7RIH685K COUTB1, COUTB2: SANYO, 50CE220LX L1, L2: PULSE PA2050.103NL MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJICO652DPB D1, D2: BAS170W Figure 12. High Efficiency 2-Phase 36V Boost Converter SENSE1– SENSE1+ ILIM CSS, 0.1μF PHASMD SW1 CLKOUT PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN VBIAS FREQ INTVCC SS CITH, 10nF 100k PGOOD TG1 INTVCC MTOP1 L1 16μH RSENSE1 8mΩ CB1, 0.1μF MBOT1 D1 CINT 4.7μF CIN 6.8μF ×4 PGND D2 RITH, 23.7k ITH COUTB1 220μF BG2 VIN 5V TO 38V VOUT 48V, 4A MBOT2 CB2, 0.1μF CITHA, 220pF L2 16μH BOOST2 RSENSE2 8mΩ SW2 RA, 12.1k RB 475k VFB SENSE2+ SENSE2– TG2 MTOP2 COUTA2 6.8μF ×4 + COUTB2 220μF 3787 F13 CIN, COUTA1, COUTA2: TDK C4532X7RIH685K COUTB1, COUTB2: SANYO, 63CE220K L1, L2: PULSE PA2050.163NL MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0652DPB D1, D2: BAS170W Figure 13. High Efficiency 2-Phase 48V Boost Converter 3787fc 30 LTC3787 TYPICAL APPLICATIONS RS1, 53.6, 1% RS2 26.1k 1% C1 0.1μF C3 0.1μF INTVCC RFREQ, 41.2k SENSE1– SENSE1+ ILIM PHASMD SW1 CLKOUT PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN FREQ CSS, 0.1μF SS CITH, 15nF 100k PGOOD TG1 INTVCC MTOP1 D3 L1 10.2μH COUTA1 6.8μF s4 + COUTB1 220μF CB1, 0.1μF MBOT1 VIN 5V TO 24V D1 VBIAS INTVCC CINT 4.7μF PGND CINA 22μF s4 + COUTA2 6.8μF s4 + VOUT 24V, 8A CINB 220μF D2 RITH, 8.87k, 1% ITH BG2 MBOT2 CB2, 0.1μF CITHA, 220pF L2 10.2μH BOOST2 RA 12.1k, 1% SW2 RS 232k 1% RS4 26.1k 1% VFB TG2 MTOP2 D4 C4 0.1μF SENSE2+ C2 0.1μF SENSE2– COUTB2 220μF RS3, 53.6k, 1% 3787 F14 COUTA1, COUTA2: C4532x7R1H685K COUTB1, COUTB2: SANYO 63CE220KX CINA: TDK C4532X5R1E226M CINB: SANYO 50CE220AX L1, L2: PULSE PA2050.103NL MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0305 D1, D2: BAS140W D3, D4: DIODES INC. B340B Figure 14. High Efficiency 2-Phase 24V Boost Converter with Inductor DCR Current Sensing 3787fc 31 LTC3787 TYPICAL APPLICATIONS SENSE1+ SENSE1– 100k PGOOD TG1 INTVCC ILIM SW1 PHASMD PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN FREQ CSS, 0.1μF SS CITH, 15nF INTVCC MTOP1 L1 3.3μH RSENSE1 4mΩ L2 3.3μH RSENSE2 4mΩ COUTA1 22μF s4 + COUTA2 22μF s4 + CINA 22μF s4 + COUTA3 22μF s4 + COUTA4 22μF s4 + COUTB1 220μF CB1, 0.1μF MBOT1 D1 VBIAS INTVCC CINT1 4.7μF PGND D2 RITH, 8.66k ITH BG2 MBOT2 CB2, 0.1μF CITHA, 220pF BOOST2 SW2 RA, 12.1k VFB RB 232k CLKOUT TG2 MTOP2 SENSE2– SENSE2+ SENSE1+ SENSE1– 100k PGOOD TG1 ILIM MTOP3 L3 3.3μH RSENSE3 4mΩ L4 3.3μH RSENSE4 4mΩ SW1 PHASMD PLLIN/MODE BOOST1 SGND BG1 EXTVCC LTC3787 RUN FREQ INTVCC COUTB2 220μF VIN 5V to 24V CINB 220μF VOUT 24V, 20A* COUTB3 220μF CB3, 0.1μF MBOT3 D3 VBIAS INTVCC CINT2 4.7μF PGND D4 SS BG2 MBOT4 CB4, 0.1μF ITH BOOST2 SW2 VFB CLKOUT TG2 MTOP4 SENSE2– SENSE2+ 3787 F15 COUTB4 220μF CINA, COUTA1, COUTA2, COUTA3, COUTA4: TDK C4532X5R1E226M CINB, COUTB1, COUTB2, COUTB3, COUTB4: SANYO, 50CE220LX L1, L2, L3, L4: PULSE PA1494.362NL MBOT1, MBOT2, MBOT3, MBOT4, MTOP1, MTOP2, MTOP3, MTOP4: RENESAS HAT2169H D1, D2, D3, D4: BAS140W *WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. Figure 15. 4-Phase Single Output Boost Converter 3787fc 32 LTC3787 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .386 – .393* (9.804 – 9.982) .045 ±.005 28 27 26 25 24 23 22 21 20 19 18 17 1615 .254 MIN .033 (0.838) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ±.0015 .150 – .157** (3.810 – 3.988) .0250 BSC 1 RECOMMENDED SOLDER PAD LAYOUT .015 ±.004 w 45° (0.38 ±0.10) .0075 – .0098 (0.19 – 0.25) 2 3 4 5 6 7 8 .0532 – .0688 (1.35 – 1.75) 9 10 11 12 13 14 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN28 REV B 0212 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3787fc 33 LTC3787 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ± 0.10 (2 SIDES) 3.50 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3787fc 34 LTC3787 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 12/10 Updated PGND, BG2, BG1, INTVCC and EXTVCC Pin numbers Updated Block Diagram Updated Figures 11, 12, 13 Updated Related Parts B C 9/11 4/12 Updated graphs on TA01b, G02, G09, G10, G11, G13, G14, G15, G18, G19, G22, and G26. 10 11 29, 30 36 1, 5, 6, 7, 8, 9 Updated the Storage Temperature Range 2 Updated Topside MOSFET Driver Supply (CB, DB) section 22 Updated Related Parts List 36 Added H and MP grades 2, 4 3787fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3787 TYPICAL APPLICATION IIN CIN 12V I1 BG1 TG1 PHASMD 0° I1 BOOST: 24V, 5A LTC3787 I2 I2 BG2 TG2 CLKOUT +90° 180° BOOST: 24V, 5A I3 24V, 20A I3 90,270 CLKOUT PHASMD BG1 TG1 I4 90° BOOST: 24V, 5A COUT ICOUT LTC3787 I4 BG2 TG2 I*IN 270° BOOST: 24V, 5A I*COUT REFER TO FIGURE 15 FOR APPLICATION CIRCUITS * RIPPLE CURRENT CANCELLATION INCREASES THE RIPPLE FREQUENCY AND REDUCES THE RMS INPUT/OUTPUT RIPPLE CURRENT, THUS SAVING INPUT/OUTPUT CAPACITORS 3787 F16 Figure 16. PolyPhase Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3788/LTC3788-1 Multiphase, Dual Output Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28 LTC3786 Low IQ Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E LTC3862/LTC3862-1 Multiphase, Dual Channel Single Output Current Mode Step-Up DC/DC Controller 4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24 LT3757/LT3758 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E LTC1871/LTC1871-1/ LTC1871-7 Wide Input Range, No RSENSE Low Quiescent Current Flyback, Boost and SEPIC Controller 2.5V ≤ VIN ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency, IQ = 250μA , MSOP-10 LTC3859 Low IQ, Triple Output Buck/Buck/Boost Synchronous DC/DC Controller All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 55μA LTC3789 High Efficiency Synchronous 4-Switch Buck-Boost DC/DC Controller 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, 4mm × 5mm QFN-28 and SSOP-2 3787fc 36 Linear Technology Corporation LT 0412 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010