AD AD8592 Cmos single supply rail-to-rail input/output operational amplifiers with shutdown Datasheet

a
CMOS Single Supply
Rail-to-Rail Input/Output
Operational Amplifiers with Shutdown
AD8591/AD8592/AD8594
FEATURES
Single Supply Operation: +2.5 V to +6 V
High Output Current: ⴞ250 mA
Extremely Low Shutdown Supply Current: 100 nA
Low Supply Current: 750 ␮A/Amp
Wide Bandwidth: 3 MHz
Slew Rate: 5 V/␮s
No Phase Reversal
Very Low Input Bias Current
High Impedance Outputs When in Shutdown Mode
Unity Gain Stable
APPLICATIONS
Mobile Communication Handset Audio
PC Audio
PCMCIA/Modem Line Driving
Battery Powered Instrumentation
Data Acquisition
ASIC Input or Output Amplifier
LCD Display Reference Level Driver
GENERAL DESCRIPTION
The AD8591, AD8592 and AD8594 are single, dual and quad
rail-to-rail input and output single supply amplifiers featuring
250 mA output drive current and a power saving shutdown
mode. The AD8592 includes an independent shutdown function for each amplifier. When both amplifiers are in shutdown
mode the total supply current is reduced to less than 1 µA. The
AD8591 and AD8594 include a single master shutdown function that reduces total supply current to less than 1 µA. All
amplifier outputs are in a high impedance state when in shutdown mode.
These amplifiers have very low input bias currents, making them
suitable for integrators and diode amplification. Outputs are
stable with virtually any capacitive load. Supply current is less
than 750 µA per amplifier in active mode.
Applications for these amplifiers include audio amplification for
portable computers, portable phone headsets, sound ports, sound
cards and set-top boxes. The AD859x family is capable of driving
heavy capacitive loads such as LCD panel reference levels.
The ability to swing rail-to-rail at both the input and output
enables designers to buffer CMOS DACs, ASICs and other
wide output swing devices in single supply systems.
PIN CONFIGURATIONS
6-Lead SOT
(RT Suffix)
6
OUT A 1
V2 2
AD8591
V1
5 SD
1IN A 3
4 2IN A
10-Lead ␮SOIC
(RM Suffix)
10 V+
OUT A 1
9 OUT B
–IN A
2
+IN A
3
V–
4
7 +IN B
SDA
5
6 SDB
AD8592
8
(Not to Scale)
–IN B
16-Lead Narrow SOIC
(R Suffix)
OUT A 1
16 OUT D
2IN A 2
15 2IN D
14 1IN D
1IN A 3
V1 4
AD8594
13 V2
TOP VIEW
1IN B 5 (Not to Scale) 12 1IN C
2IN B 6
11 2IN C
OUT B 7
10 OUT C
NC 8
9
SD
NC = NO CONNECT
16-Lead TSSOP
(RU Suffix)
OUT A
2IN A
1IN A
V1
1IN B
2IN B
OUT B
NC
1
16
AD8594
8
9
OUT D
2IN D
1IN D
V2
+IN C
2IN C
OUT C
SD
NC = NO CONNECT
The AD8591, AD8592 and AD8594 are specified over the industrial (–40°C to +85°C) temperature range. The AD8591, single,
is available in the tiny 6-lead SOT package. The AD8592, dual, is
available in the 10-lead µSOIC surface mount package. The
AD8594, quad, is available in 16-lead narrow SOIC and 16-lead
TSSOP packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD8591/AD8592/AD8594–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = +2.7 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS␣
Offset Voltage
VOS
CM
= +1.35 V, TA = +25ⴗC unless otherwise noted)
Conditions
Min
Typ
–40°C < TA < +85°C
Input Bias Current
IB
5
–40°C < TA < +85°C
Input Offset Current
1
IOS
–40°C < TA < +85°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
AVO
∆VOS /∆T
∆IB /∆T
∆IOS /∆T
VCM = 0 V to +2.7 V
RL = 2 kΩ , VO = +0.3 V to +2.4 V
VOH
IL = 10 mA
–40°C to +85°C
IL = 10 mA
–40°C to +85°C
Output Voltage Low
VOL
Output Current
Open-Loop Impedance
IOUT
ZOUT
POWER SUPPLY␣
Power Supply Rejection Ratio
Supply Current/Amplifier
0
38
+2.55
+2.5
45
ISD1
ISD2
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
Logic Input Current
VINH
VINL
IIN
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
+1.6
DYNAMIC PERFORMANCE␣
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
tS
GBP
Φo
CS
RL = 2 kΩ
To 0.01%
NOISE PERFORMANCE␣
Voltage Noise Density
en
Current Noise Density
in
Supply Current Shutdown Mode
ISD
25
30
50
60
25
30
+2.7
mV
mV
pA
pA
pA
pA
V
dB
V/mV
µV/°C
fA/°C
fA/°C
+2.61
± 250
60
VS = +2.5 V to +6 V
VO = 0 V
–40°C < TA < +85°C
All Amplifiers Shut Down
–40°C < TA < +85°C
Amplifier 1 Shut Down (AD8592)
Amplifier 2 Shut Down (AD8592)
PSRR
ISY
Units
45
25
20
50
20
60
f = 1 MHz, AV = 1
Max
100
125
55
0.1
V
V
mV
mV
mA
Ω
1
1.25
1
1
1.4
1.4
dB
mA
mA
µA
µA
mA
mA
+0.5
1
V
V
µA
f = 1 kHz, RL = 2 kΩ
3.5
1.4
2.2
67
65
V/µs
µs
MHz
Degrees
dB
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
–2–
REV. A
AD8591/AD8592/AD8594
ELECTRICAL CHARACTERISTICS (V = +5.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS␣
Offset Voltage
VOS
CM
= +2.5 V, TA = +25ⴗC unless otherwise noted)
Conditions
Min
Typ
Max
Units
2
25
30
50
60
25
30
+5
mV
mV
pA
pA
pA
pA
V
dB
V/mV
µV/°C
fA/°C
fA/°C
–40°C < TA < +85°C
Input Bias Current
IB
5
–40°C < TA < +85°C
Input Offset Current
1
IOS
–40°C < TA < +85°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
AVO
∆VOS /∆T
∆IB /∆T
∆IOS /∆T
VCM = 0 V to +5 V
RL = 2 kΩ , VO = +0.5 V to +4.5 V
–40°C < TA < +85°C
VOH
IL = 10 mA
–40°C to +85°C
IL = 10 mA
–40°C to +85°C
Output Voltage Low
VOL
Output Current
Open-Loop Impedance
IOUT
ZOUT
POWER SUPPLY␣
Power Supply Rejection Ratio
Supply Current/Amplifier
0
38
15
+4.9
+4.85
± 250
40
f = 1 MHz, AV = 1
45
ISD1
ISD2
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
Logic Input Current
VINH
VINL
IIN
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
+2.4
DYNAMIC PERFORMANCE␣
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
Φo
CS
RL = 2 kΩ
1% Distortion
To 0.01%
NOISE PERFORMANCE␣
Voltage Noise Density
en
Current Noise Density
in
Supply Current-Shutdown Mode
ISD
100
125
55
0.1
V
V
mV
mV
mA
Ω
1.25
1.75
1
1
1.6
1.6
dB
mA
mA
µA
µA
mA
mA
+0.8
1
V
V
µA
f = 1 kHz, RL = 10 kΩ
5
325
1.6
3
70
65
V/µs
kHz
µs
MHz
Degrees
dB
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
REV. A
+4.94
50
VS = +2.5 V to +6 V
VO = 0 V
–40°C < TA < +85°C
All Amplifiers Shut Down
–40°C < TA < +85°C
Amplifier 1 Shut Down (AD8592)
Amplifier 2 Shut Down (AD8592)
PSRR
ISY
47
30
20
50
20
–3–
AD8591/AD8592/AD8594
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Output Short Circuit2
Duration to GND . . . . . . . . . . . . Observe Derating Curves
Storage Temperature Range
R, RT, RM, RU Packages . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD8591/AD8592/AD8594 . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
R, RT, RM, RU Packages . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
␪JA1
␪JC
Units
6-Lead SOT-23 (RT)
10-Lead µSOIC (RM)
16-Lead SOIC (R)
16-Lead TSSOP (RU)
230
200
120
180
92
44
36
35
°C/W
°C/W
°C/W
°C/W
NOTE
1
θJA is specified for worst case conditions, i.e., θJA is specified for device in socket
for surface mount packages.
ORDERING GUIDE
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
For supplies less than ± 5 V the differential input voltage is limited to the supplies.
Model
Temperature
Range
Package
Description
Package
Option
AD8591ART
AD8592ARM
AD8594AR
AD8594ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
6-Lead SOT-23
10-Lead µSOIC
16-Lead SOIC
16-Lead TSSOP
RT-6
RM-10
R-16A
RU-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8591/AD8592/AD8594 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Typical Performance Characteristics
10k
1k
SINK
10
1
0.1
0.01
0.1
1
10
100
LOAD CURRENT – mA
1k
Figure 1. Output Voltage to Supply
Rail vs. Load Current
SUPPLY CURRENT/AMPLIFIER – mA
∆OUTPUT VOLTAGE – mV
∆OUTPUT VOLTAGE – mV
100
SOURCE
0.90
VS = +5V
TA = +258C
VS = +2.7V
TA = +258C
1k
100
SOURCE
SINK
10
1
0.1
0.01
0.1
100
1
10
LOAD CURRENT – mA
1k
Figure 2. Output Voltage to Supply
Rail vs. Load Current
–4–
0.85
0.80
0.75
0.70
VS = +5V
0.65
0.60
VS = +2.7V
0.55
0.50
240 220
0
20
40
60
TEMPERATURE – 8C
80
100
Figure 3. Supply Current per
Amplifier vs. Temperature
REV. A
AD8591/AD8592/AD8594
22
0.5
0.4
0.3
0.2
0.1
0.75
1.25
1.75
2.25
2.75
SUPPLY VOLTAGE – 6Volts
26
27
235
215
5
25
45
TEMPERATURE – 8C
1
0
21
22
250
235
215
5
25
45
TEMPERATURE – 8C
Figure 7. Input Offset Current vs.
Temperature
135
0
180
10k
100k
1M
10M
FREQUENCY – Hz
100M
Figure 10. Open-Loop Gain and
Phase vs. Frequency
85
65
VS = +2.7V
RL = NO LOAD
TA = +258C
45
40
90
20
135
0
180
2
0
1
2
3
4
COMMON-MODE VOLTAGE – Volts
5
1k
3
2
1
0
1k
10k
100k
1M
10M
FREQUENCY – Hz
100M
Figure 9. Open-Loop Gain and Phase
vs. Frequency
5
VS = +2.7V
RL = 2kV
TA = +258C
VIN = 2.5V p-p
4
OUTPUT SWING – V p-p
20
PHASE SHIFT – Degrees
90
215
5
25
45
TEMPERATURE – 8C
3
45
40
REV. A
4
5
VS = +5V
RL = NO LOAD
TA = +258C
60
1k
5
Figure 8. Input Bias Current vs.
Common-Mode Voltage
80
235
60
6
1
85
65
4
80
GAIN – dB
INPUT BIAS CURRENT – pA
2
5
Figure 6. Input Bias Current vs.
Temperature
VS = +5V
TA = +258C
7
3
6
2
250
85
65
8
VS = +2.7V, +5V
VCM = VS / 2
7
3
Figure 5. Input Offset Voltage vs.
Temperature
4
INPUT OFFSET CURRENT – pA
25
28
250
3
Figure 4. Supply Current per
Amplifier vs. Supply Voltage
GAIN – dB
24
4
OUTPUT SWING – V p-p
0
23
PHASE SHIFT – Degrees
0.6
VS = +2.7V, +5V
VCM = VS/2
INPUT BIAS CURRENT – pA
0.7
8
VS = +5V
VCM = +2.5V
TA = +258C
INPUT OFFSET VOLTAGE – mV
SUPPLY CURRENT/AMPLIFIER – mA
0.8
VS = +5V
RL = 2kV
TA = +258C
VIN = 4.9V p-p
3
2
1
10k
100k
1M
FREQUENCY – Hz
10M
Figure 11. Closed-Loop Output
Voltage Swing vs. Frequency
–5–
0
1k
10k
100k
1M
FREQUENCY – Hz
10M
Figure 12. Closed-Loop Output
Voltage Swing vs. Frequency
AD8591/AD8592/AD8594
110
200
140
100
80
CMRR – dB
90
120
AV = 10
100
80
80
40
240
10k
100k
1M
10M
FREQUENCY – Hz
50
1k
100M
260
100
10M
100k
1M
FREQUENCY – Hz
2PSRR
+PSRR
40
20
0
220
240
1k
10k
100k
FREQUENCY – Hz
1M
Figure 16. Power Supply Rejection
Ratio vs. Frequency
+OS
40
2OS
30
20
10
0
10
10M
10k
100k
FREQUENCY – Hz
1M
10M
60
VS = +2.5V
RL = 2kV
TA = +258C
SMALL SIGNAL OVERSHOOT – %
80
SMALL SIGNAL OVERSHOOT – %
100
50
1k
Figure 15. Power Supply Rejection
Ratio vs. Frequency
60
VS = +5V
TA = +258C
120
PSRR – dB
10k
Figure 14. Common-Mode Rejection
Ratio vs. Frequency
140
260
100
2PSRR
20
220
60
Figure 13. Closed-Loop Output
Impedance vs. Frequency
60
+PSRR
40
0
20
0
1k
60
70
AV = 1
60
VS = +2.5V
TA = +258C
120
100
160
IMPEDANCE – V
140
VS = +5V
TA = +258C
PSRR – dB
180
VS = +5V
TA = +258C
100
1k
CAPACITANCE – pF
10k
Figure 17. Small Signal Overshoot
vs. Load Capacitance
50
VS = +5V
RL = 2kV
TA = +258C
40
2OS
30
+OS
20
10
0
10
100
1k
CAPACITANCE – pF
10k
Figure 18. Small Signal Overshoot
vs. Load Capacitance
VS = 61.35V
AV = 1
100
90
RL = 2kV
0V
VS = 61.35V
VIN = 650mV
AV = 1
RL = 2kV
CL = 300pF
TA = +258C
500 ns/DIV
Figure 19. Small Signal Transient
Response
20mV/DIV
20mV/DIV
TA = +258C
0V
VS = 62.5V
VIN = 650mV
AV = 1
RL = 2kV
CL = 300pF
TA = +258C
10
0%
500mV
500ns
500 ns/DIV
Figure 20. Small Signal Transient
Response
–6–
Figure 21. Large Signal Transient
Response
REV. A
AD8591/AD8592/AD8594
100
90
10ms
1V
100
RL = 2kV
90
TA = +258C
VS = 62.5V
AV = 1
10
10
0%
0%
500mV
TA = +258C
1V
500ns
CURRENT NOISE DENSITY – pA/ Hz
1
VS = 62.5V
AV = 1
VS = +5V
TA = +258C
0.1
0.01
10
100mV/DIV
90
VS = +5V
AV = 1000
TA = +258C
FREQUENCY = 1kHz
100
90
10
10
0%
0%
1k
10k
FREQUENCY – Hz
100k
Figure 24. Current Noise Density vs.
Frequency
VS = +5V
A V = 1000
500
TA = +258C
FREQUENCY = 10kHz
200mV/DIV
100
Figure 23. No Phase Reversal
QUANTITY – Amplifiers
Figure 22. Large Signal Transient
Response
100
VS = +2.7V
VCM = +1.35V
TA = +258C
400
300
200
100
MARKER 25.9 mV/ Hz
MARKER 41mV/ Hz
–12 –10 –8 –6 –4 –2 0
2
4
INPUT OFFSET VOLTAGE – mV
Figure 25. Voltage Noise Density vs.
Frequency
Figure 26. Voltage Noise Density vs.
Frequency
VS = +5V
VCM = +2.5V
TA = +258C
QUANTITY – Amplifiers
500
400
300
200
100
–12 –10 –8 –6 –4 –2 0
2
4
INPUT OFFSET VOLTAGE – mV
Figure 28. Input Offset Voltage
Distribution
REV. A
–7–
Figure 27. Input Offset Voltage
Distribution
AD8591/AD8592/AD8594
AD8591/AD8592/AD8594 APPLICATION SECTION
Theory of Operation
Output Phase Reversal
The AD8591/AD8592/AD8594 are immune to output voltage
phase reversal with an input voltage within the supply voltages
of the device. However, if either of the device’s inputs exceeds
+0.6␣ V outside of the supply rails, the output could exhibit
phase reversal. This is due to the ESD protection diodes becoming forward biased, thus causing the polarity of the input
terminals of the device to switch.
The AD859x family of amplifiers are all CMOS, high output drive,
rail-to-rail input and output single supply amplifiers designed for
low cost and high output current drive. The parts include a power
saving shutdown function making the AD8591/AD8592/AD8594
op amps ideal for portable multimedia and telecom applications.
Figure 29 shows the simplified schematic for an AD8591/AD8592/
AD8594 amplifier. Two input differential pairs, consisting of an
n-channel pair (M1-M2) and a p-channel pair (M3-M4), provide
a rail-to-rail input common-mode range. The outputs of the input
differential pairs are combined in a compound folded-cascode
stage, which drives the input to a second differential pair gain
stage. The outputs of the second gain stage provide the gate voltage drive to the rail-to-rail output stage.
The technique recommended in the Input Overvoltage Protection
section should be applied in applications where the possibility of
input voltages exceeding the supply voltages exists.
Output Short Circuit Protection
To achieve high output current drive and rail-to-rail performance,
the outputs of the AD859x family do not have internal short circuit protection circuitry. Although these amplifiers are designed to
sink or source as much as 250␣ mA of output current, shorting the
output directly to the positive supply could damage or destroy the
device. To protect the output stage, the maximum output current
should be limited to ± 250␣ mA.
The rail-to-rail output stage consists of M15 and M16, which are
configured in a complementary common-source configuration.
As with any rail-to-rail output amplifier, the gain of the output
stage, and thus the open-loop gain of the amplifier, is dependent
on the load resistance. Also, the maximum output voltage swing
is directly proportional to the load current. The difference between the maximum output voltage to the supply rails, known as
the dropout voltage, is determined by the AD8591/AD8592/
AD8594 output transistors’ on-channel resistance. The output
dropout voltage is given in Figure 1 and Figure 2.
*
*
M337
M5
M3
M30
M8
VB2
M1
20mA
M12
M4
VSY
250 mA
(2)
For a +5 V single supply application, RX should be at least 20␣ Ω.
Because RX is inside the feedback loop, VOUT is not affected. The
tradeoff in using RX is a slight reduction in output voltage swing
under heavy output current loads. RX will also increase the effective output impedance of the amplifier to RO + RX, where RO is
the output impedance of the device.
*
*
100mA
M11
INV
SD
RX ≥
V+
100mA
50mA
By placing a resistor in series with the output of the amplifier as
shown in Figure 30, the output current can be limited. The
minimum value for RX can be found from Equation 2.
+5V
M15
IN–
M6
IN+
VB3
20mA
M7
AD8592
M16
M9
INV
M340
*
50mA
VIN
OUT
M2
M10
*
M13
Figure 30. Output Short Circuit Protection
M31
Power Dissipation
Although the AD859x family of amplifiers are able to provide
load currents of up to 250␣ mA, proper attention should be
given to not exceeding the maximum junction temperature for
the device. The equation for finding the junction temperature is
given as:
*NOTE: ALL CURRENT SOURCES GO
TO 0 mA IN SHUTDOWN MODE
Figure 29. AD8591/AD8592/AD8594 Simplified Schematic
TJ = PDISS × θ JA + TA
Input Voltage Protection
Although not shown on the simplified schematic, ESD protection diodes are connected from each input to each power supply
rail. These diodes are normally reverse biased, but will turn on
if either input voltage exceeds either supply rail by more than
+0.6 V. Should this condition occur, the input current should
be limited to less than ± 5 mA. This can be done by placing a
resistor in series with the input(s). The minimum resistor value
should be:
VIN , MAX
5 mA
VOUT
M14
V–
RIN ≥
RX
20V
(3)
Where TJ = AD859x junction temperature
PDISS = AD859x power dissipation
θJA = AD859x junction-to-ambient thermal resistance
of the package; and
TA = The ambient temperature of the circuit
(1)
–8–
REV. A
AD8591/AD8592/AD8594
In any application, the absolute maximum junction temperature
must be limited to +150°C. If this junction temperature is exceeded, the device could suffer premature failure. If the output
voltage and output current are in phase, for example, with a
purely resistive load, the power dissipated by the AD859x can
be found as:
(
PDISS = I LOAD × VSY – VOUT
Where
)
50mV
100
47nF LOAD
ONLY
(4)
SNUBBER
IN CIRCUIT
10ms
Figure 33. Snubber Network Reduces Overshoot and
Ringing Caused from Driving Heavy Capacitive Loads
By calculating the power dissipation of the device and using the
thermal resistance value for a given package type, the maximum
allowable ambient temperature for an application can be found
using Equation 3.
The optimum values for the snubber network should be determined
empirically based on the size of the capacitive load. Table I shows a
few sample snubber network values for a given load capacitance.
Capacitive Loading
Table I. Snubber Networks for Large Capacitive Loads
The AD859x exhibits excellent capacitive load driving capabilities
and can drive up to 10 nF directly. Although the device is stable
with large capacitive loads, there is a decrease in amplifier bandwidth as the capacitive load increases. Figure 31 shows a graph of
the AD8592 unity gain bandwidth under various capacitive loads.
4
VS = 62.5V
Load Capacitance
(CL)
Snubber Network
(RS, CS)
0.47 nF
4.7 nF
47 nF
300 Ω, 0.1 µF
30 Ω, 1 µF
5 Ω, 1 µF
RL = 1kV
A PC-98 Compliant Headphone/Speaker Amplifier
TA = +258C
Because of its high output current performance and shutdown
feature, the AD8592 makes an excellent amplifier for driving an
audio output jack in a computer application. Figure 34 shows
how the AD8592 can be interfaced with an AC97 codec to drive
headphones or speakers.
3
BANDWIDTH – MHz
10
0%
50mV
ILOAD = AD859x output load current
VSY = AD859x supply voltage; and
VOUT = The output voltage
3.5
90
2.5
2
+5V
1.5
+5V
VDD
1
VDD 28
U1-A
0.5
LEFTOUT 35
0
0.01
0.1
1
CAPACITIVE LOAD – nF
Figure 31. Unity Gain Bandwidth vs. Capacitive Load
C2
100mF
7
U1-B
8
NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY
NC
9
R5
20V
R3
2kV
U1 = AD8592
Figure 34. A PC-98 Compliant Headphone/Line Out Amplifier
When headphones are plugged into the jack, the normalizing contacts disconnect from the audio contacts. This allows the voltage to
the AD8592 shutdown pins to be pulled up to +5 V, activating the
amplifiers. With no plug in the output jack, the shutdown voltage is
pulled to 100 mV through the R1 and R3␣ +␣ R5 voltage divider.
This powers the AD8592 down when it is not needed, saving
current from the power supply or battery.
VOUT
CL
47nF
Figure 32. Configuration for Snubber Network to
Compensate for Capacitive Loads
REV. A
R2
2kV
R1
100kV
VSS
RS
5V
CS
1mF
+5V
R4
20V
6
RIGHTOUT 36
+5V
AD8592
1
5
AD1881
(AC97)
When driving heavy capacitive loads directly from the AD859x
output, a snubber network can be used to improve transient
response. This network consists of a series R-C connected from
the amplifier’s output to ground, placing it in parallel with the
capacitive load. The configuration is shown in Figure 32. Although this network will not increase the bandwidth of the amplifier, it will significantly reduce the amount of overshoot, as
shown in Figure 33.
VIN
100mV p-p
4
3
100
10
C1
100mF
10
2
–9–
AD8591/AD8592/AD8594
If gain is required from the output amplifier, four additional
resistors should be added as shown in Figure 35. The gain of
the AD8592 can be set as:
AV =
R7
R6
A Combined Microphone and Speaker Amplifier for
Cellphone and Portable Headsets
(5)
+5V
The dual amplifiers in the AD8592 make an efficient design for
interfacing with a headset containing a microphone and speaker.
Figure 36 demonstrates a simple method for constructing an
interface to a codec.
R7
20kV
VDD
LEFTOUT 35
R1
2.2kV
+5V
VDD 38
R6
10kV
C1
100mF
10
2
U1-A
R4
20V
1
4
3
+5V
5
R2
2kV
C1
0.1mF
R6
10kV
RIGHTOUT 36
U1-B
9
8
U1-A
3
R7
1kV
MIC + SPEAKER
JACK
5
+5V
R8
100kV
VREF
FROM CODEC
6
C2
10mF
R5
20V
7
9
NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY
AV =
R3
2kV
U1 = AD8592
(RIGHT OUT)
Figure 36. A Speaker/Mic Headset Amplifier Circuit
= +6dB WITH VALUES SHOWN
R6
U1-A is used as a microphone preamplifier, where the gain of
the preamplifier is set as R3/R2. R1 is used to bias an electret
microphone and C1 blocks any dc voltages from the amplifier.
U1-B is the speaker amplifier, and its gain is set at R5/R4. To
sum a stereo output, R6 should be added, equal in value to R4.
Using the same principle as described in the previous section,
the normalizing contact on the microphone/speaker jack can be
used to put the AD8592 into shutdown when the headset is not
plugged in. The AD8592 shutdown inputs can also be controlled with TTL or CMOS compatible logic, allowing microphone or speaker muting if desired.
R4 and R5 help protect the AD8592 output in case the output
jack or headphone wires accidentally get shorted to ground.
The output coupling capacitors C1 and C2 block dc current
from the headphones and create a high-pass filter with a corner
frequency of:
(
2π C1 R4 + RL
R6
10kV
(OPTIONAL)
U1 = AD8592
Input coupling capacitors are not required for either circuit as
the reference voltage is supplied from the AD1881.
1
FROM CODEC
MONO OUT
(OR LEFT OUT)
8
Figure 35. A PC-98 Compliant Headphone/Line Out
Amplifier With Gain
f –3 dB =
R4
10kV
U1-B
R5
10kV
R7
TO
CODEC
1
4
VSS
R7
20kV
10
2
6
7
+5V
NC
VREF 27
C2
100mF
R2
10kV
NC
R1
100kV
AD1881
(AC97)
R3
100kV
+5V
)
Where RL is the resistance of the headphones.
An Inexpensive Sample-and-Hold Circuit
(6)
The independent shutdown control of each amplifier in the
AD8592 allows a degree of flexibility in circuit design. One particular application for which this feature is useful is in designing a
sample-and-hold circuit for data acquisition. Figure 37 shows a
schematic of a simple, yet extremely effective sample-and-hold
circuit using a single AD8592 and one capacitor.
8
+5V
2
10
U1-B
U1-A
VIN
4
3
5
SAMPLE
CLOCK
1
C1
1nF
7
6
9
SAMPLE
AND HOLD
OUTPUT
+5V
U1 = AD8592
Figure 37. An Efficient Sample-and-Hold Circuit
–10–
REV. A
AD8591/AD8592/AD8594
The U1-A amplifier is configured as a unity gain buffer driving a
1 nF capacitor. The input signal is connected to the noninverting
input, while the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows VIN. Once the sample clock goes
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
The U1-B amplifier is used as a unity gain buffer to prevent loading on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is very little voltage droop from C1
during the Hold period. This circuit can be used with sample
frequencies as high as 500␣ kHz and as low as below 1␣ Hz. Even
lower voltage droop can be achieved for very low sample rates
by increasing the value of C1.
Single Supply Differential Line Driver
Figure 39 shows a single supply differential line driver circuit that
can drive a 600␣ Ω load with less than 0.7% distortion from 20 Hz
to 15 kHz with an input signal of 4 V p-p and a single +5 V supply.
The design uses an AD8594 to mimic the performance of a fully
balanced transformer based solution. However, this design occupies much less board space while maintaining low distortion and
can operate down to dc. Like the transformer based design, either
output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1.
R3
10kV
3
R2
10kV
Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface)
P1
Tx GAIN
ADJUST
TO TELEPHONE
LINE
1:1
6.2V
ZO
600V
R2
9.09kV
1
R5
10kV
2
A1
C1
R1
10kV 0.1mF
TRANSMIT
TxA
R6
10kV
9
6
8
7
R10
10kV
R9
10kV
2
R11
10kV
R12
10kV
3
5
A3
1
R13
R14
10kV 14.3kV
8
6
7
A4
P2
Rx GAIN
ADJUST
2kV
9
7
R10
10kV
8
9
A1
4
R11
R12
10kV 10kV
R9
100kV
8
7
A2
R8
100kV
7
9
R14
50V
RL
600V
C2
1mF
C4
47mF
R13
10kV
VO2
SET: R6, R12, R13 = R3
Figure 39. A Low Noise, Single Supply Differential
Line Driver
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the input’s dc voltage is equal to half of
the supply voltage.
The circuit can also be configured to provide additional gain if
desired. The gain of the circuit is:
Where:
R8
10kV
RECEIVE
RxA
C2
0.1mF
Figure 38. A Single Supply Direct Access Arrangement for
PCMCIA Modems
REV. A
+5V
10
1
SET: R7, R10, R11 = R2
R7
10kV
10mF
VO1
R6
10kV
R7
10kV
4
GAIN = R3
R2
SHUTDOWN
A2
3
10
A1
A1, A2 = 1/2 AD8592
+5V
T1
MIDCOM
671-8005
2
C3
47mF
+5V
R1
10kV
3
5
6.2V
A1, A2 = 1/2 AD8592
A3, A4 = 1/2 AD8592
VIN
AV =
2kV
R3
360V
C1
22mF
1
A2
+5V
Figure 38 illustrates a +5␣ V transmit/receive telephone line
interface for 600␣ Ω systems. It allows full duplex transmission of
signals on a transformer-coupled 600␣ Ω line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the AD8594’s high output
current drive and low dropout voltages, the largest signal available on a single +5␣ V supply is approximately 4.5␣ V␣ p-p into a
600␣ Ω transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons: (1)␣ It prevents the transmit
signal from interfering with the receive signal and (2)␣ it extracts
the receive signal from the transmission line for amplification by
A4. Amplifier A4’s gain can be adjusted in the same manner as
A1’s to meet the modem’s input signal requirements. Standard
resistor values permit the use of SIP (Single In-line Package)
format resistor arrays. Couple this with the AD8594 16-lead
TSSOP or SOIC footprint, and this circuit offers a compact,
cost effective solution.
R5
50V
2
–11–
VOUT
R3
=
VIN
R2
VOUT = VO1␣ –␣ VO2,
R2 = R7 = R10 = R11 and,
R3 = R6 = R12 = R13
(7)
AD8591/AD8592/AD8594
SPICE Model for the AD8591/AD8592/AD8594 Amplifier
The SPICE model for the AD8591/AD8592/AD8594 amplifier is
one of the more realistic computer simulation macro-models
available, providing a high degree of realism with respect to characteristics of the actual amplifier. This model, shown in Listing 1,
is based on typical values for the device and can be downloaded
from Analog Devices’ Internet site at www.analog.com.
The model uses a common source output stage to provide railto-rail performance. This allows realistic simulation of openloop gain dependency on load resistance as well as maximum
output voltage versus output current. Two differential pairs are
used in the input stage of the model, simulating the rail-to-rail
input stage of the AD8591/AD8592/AD8594 amplifier.
The EOS voltage source establishes the input offset voltage and
is also used to simulate the common-mode rejection power
supply rejection, and input voltage noise characteristics for the
model. In addition, G2, R2 and CF are used to help set the
open-loop gain and gain-bandwidth product of the model.
A number of secondary characteristics are also accurately portrayed in the SPICE model. Flicker noise is accurately modeled
with the 1/f corner frequency set through the KF and AF terms
in the input stage transistors. C1 and C2 are used in the input
section to create secondary poles to achieve an accurate phase
margin characteristic for the model.
The AD8591/AD8592/AD8594 shutdown circuitry is included
in the model. Switches S1 through S7 deactivate the op amp
circuitry in shutdown mode. The logic threshold for the shutdown circuitry is accurately modeled through the VSWITCH
model parameters near the end of the listing. The active supply
current versus supply voltage is also modeled through the voltage-controlled current source GSY.
Characteristics of this model are based on typical values for the
AD8591/AD8592/AD8594 amplifier at +27°C. The model’s
characteristics are optimized specifically at +27°C, and may lose
accuracy at different simulation temperatures.
–12–
REV. A
AD8591/AD8592/AD8594
Listing 1: AD859x SPICE Macro-Model
* AD8592 SPICE Macro-Model Typical Values
* 9/98, Ver. 1
* TAM / ADSC
*
* Copyright 1998 by Analog Devices
*
* Refer to “README.DOC” file for License
* Statement. Use of this
* model indicates your acceptance of the
* terms and provisions in
* the License Statement.
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
| output
*
|
|
|
| |
shutdown
*
|
|
|
| |
|
.SUBCKT AD8592
1
2
99 50 45 80
*
* INPUT STAGE
*
M1
4 1 3 3 PIX L=0.8E-6 W=125E-6
M2
6 7 3 3 PIX L=0.8E-6 W=125E-6
RC1 4 50 4E3
RC2 6 50 4E3
C1
4 6 2E-12
I1 99 8 100E-6
M3
M4
RC3
RC4
C2
I2
10
11
10
11
10
13
1
7
99
99
11
50
12 12 NIX L=0.8E-6 W=125E-6
12 12 NIX L=0.8E-6 W=125E-6
4E3
4E3
2E-12
100E-6
EOS 7 2 POLY(3) (21,98) (73,98) (61,0)
+1E-3 1 1 1
IOS 1 2 2.5E-12
V1 99 9 0.9
D1
3 9 DX
V2 14 50 0.9
D2 14 12 DX
S1
3 8 (82,98) SOPEN
S2 99 8 (98,82) SCLOSE
S3 12 13 (82,98) SOPEN
S4 13 50 (98,82) SCLOSE
*
* CMRR=64dB, ZERO AT 20kHz
*
ECM1 20 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 20 21 79.6E3
CCM1 20 21 100E-12
RCM2 21 98 50
*
* PSRR=80dB, ZERO AT 200Hz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5
REV. A
–13–
AD8591/AD8592/AD8594
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 80
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 POLY(1) (99,50) 20E-6 10E-7
*
* SHUTDOWN SECTION
*
E1 81 98 (80,50) 1
R1 81 82 1E3
C3 82 98 1E-9
*
* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz)
*
VN1 60 0 0
RN1 60 0 16.45E-3
HN 61 0 VN1 30
RN2 61 0 1
*
* GAIN STAGE
*
G2 98 30 POLY(2) (4,6) (10,11) 0 2.19E-5 +2.19E-5
R2 30 98 13E6
CF 45 30 5E-12
S5 30 98 (98,82) SCLOSE
D3 30 31 DX
D4 32 30 DX
V3 99 31 0.6
V4 32 50 0.6
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=0.8E-6 W=16E-3
M6 45 47 50 50 NOX L=0.8E-6 W=16E-3
EG1 99 48 POLY(1) (98,30) 1.06 1
EG2 49 50 POLY(1) (30,98) 1.05 1
RG1 48 46 10E3
RG2 49 47 10E3
S6 46 99 (98,82) SCLOSE
S7 47 50 (98,82) SCLOSE
*
* MODELS
*
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL POX PMOS (LEVEL=2,KP=8E-6,VTO=-1, LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=13.4E-6,VTO=1, LAMBDA=0.067)
.MODEL SOPEN VSWITCH(VON=2.4,VOFF=0.8, RON=10,ROFF=1E9)
.MODEL SCLOSE VSWITCH(VON=-0.8,VOFF=-2.4, RON=10,ROFF=1E9)
.MODEL DX D(IS=1E-14)
.ENDS AD8592
–14–
REV. A
AD8591/AD8592/AD8594
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.124 (3.15)
0.112 (2.84)
0.122 (3.10)
0.106 (2.70)
6
0.071 (1.80)
0.059 (1.50)
5
1
10
4
2
C3456a–0–2/99
10-Lead ␮SOIC
(RM-10)
6-Lead SOT
(RT-6)
0.118 (3.00)
0.098 (2.50)
3
6
0.124 (3.15)
0.112 (2.84)
0.199 (5.05)
0.187 (4.75)
1
5
PIN 1
0.037 (0.95) BSC
PIN 1
0.0197 (0.50) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.020 (0.50) SEATING
0.010 (0.25) PLANE
0.059 (0.15)
0.000 (0.00)
108
0.009 (0.23) 08
0.003 (0.08)
0.038 (0.97)
0.030 (0.76)
0.022 (0.55)
0.014 (0.35)
0.122 (3.10)
0.110 (2.79)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
16-Lead Thin Shrink Small Outline
(RU-16)
0.016 (0.41)
0.006 (0.15)
0.1574 (4.00)
0.1497 (3.80) 1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
9
PIN 1
PIN 1
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
0.0500
SEATING (1.27)
PLANE BSC
88
08
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0° 0.0500 (1.27)
0.0160 (0.41)
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
9
8
0.0098 (0.25)
0.0040 (0.10)
8
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.022 (0.56)
0.021 (0.53)
0.3937 (10.00)
0.3859 (9.80)
16
1
68
SEATING
08
0.011 (0.28)
PLANE
0.003 (0.08)
16-Lead Narrow Body SO
(R-16A)
0.201 (5.10)
0.193 (4.90)
16
0.120 (3.05)
0.112 (2.84)
REV. A
–15–