Ramtron FM25C160-GA 16kb fram serial memory Datasheet

AEC Q100 Grade 1 Compliant
FM25C160 – Automotive Temp.
16Kb FRAM Serial Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• 10 µA Standby Current
Very Fast Serial Peripheral Interface - SPI
• Up to 15 MHz maximum Bus Frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Industry Standard Configuration
• Automotive Temperature -40° C to +125° C
o Qualified to AEC Q100 Specification
• “Green”/RoHS 8-pin SOIC
Description
Pin Configuration
The FM25C160 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
Unlike serial EEPROMs, the FM25C160 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array
immediately after it has been successfully transferred
to the device. The next bus cycle may commence
immediately. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM25C160 is capable of
supporting up to 1012 read/write cycles -- far more
than most systems will require from a serial memory.
These capabilities make the FM25C160 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding automotive controls where the long write
time of EEPROM can cause data loss.
CS
SO
WP
1
8
2
7
3
6
VSS
4
5
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
5V
Ground
Ordering Information
FM25C160-GA
The FM25C160 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25C160 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. The specifications are
guaranteed over an automotive temperature range of
-40°C to +125°C.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.1
July 2007
VDD
HOLD
SCK
SI
“Green” 8-pin SOIC, Automotive Grade 1
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
FM25C160 - Automotive Temp.
WP
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
HOLD
SCK
512 x 32
FRAM Array
Instruction Register
Address Register
Counter
11
SI
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Description
Pin Name
/CS
I/O
Input
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 3.1
July 2007
Pin Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 15 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the status register. This
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided on page 6. *Note that
the function of /WP is different from the FM25160.
Serial Input: All data is input to the device on this pin. The pin is sampled on the rising
edge of SCK and is ignored at other times. It should always be driven to a valid logic
level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output. SO is the data output pin. It is driven actively during a read and remains
tri-state at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Supply Voltage. 5V
Ground
Page 2 of 13
FM25C160 - Automotive Temp.
Overview
Serial Peripheral Interface – SPI Bus
The FM25C160 is a serial FRAM memory. The
memory array is logically organized as 2,048 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25C160 and a serial
EEPROM with the same pin-out relates to its
superior write performance. It also differs from
Ramtron’s 25160 by supporting SPI mode 3 and the
industry standard 16-bit addressing protocol. This
makes the FM25C160 a drop-in replacement for most
16Kb SPI EEPROMs that support modes 0 & 3.
The FM25C160 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 15
MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25C160 operates in SPI Mode 0 and 3.
Memory Architecture
When accessing the FM25C160, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code and a
two-byte address. The upper 5 bits of the address
range are ‘don’t care’ values. The complete address
of 11-bits specifies each byte address uniquely.
Most functions of the FM25C160 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation essentially is zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
Users expect several obvious system benefits from
the FM25C160 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note: The FM25C160 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within data sheet tolerances to
prevent incorrect operation. It is recommended
that the part is not powered down with chip
enable active.
Rev. 3.1
July 2007
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25C160 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25C160 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the Hold pin. Figure 3 shows a
configuration that uses only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25C160 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25C160 supports modes 0 and 3. Figure 4 shows
the required signal relationships for modes 0 and 3.
For both modes, data is clocked into the FM25C160
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Page 3 of 13
FM25C160 - Automotive Temp.
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 3.1
July 2007
Page 4 of 13
FM25C160 - Automotive Temp.
Data Transfer
All data transfers to and from the FM25C160 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25C160. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name
Description
WREN
WRDI
RDSR
WRSR
READ
WRITE
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Op-code value
0000_0110b
0000_0100b
0000_0101b
0000_0001b
0000_0011b
0000_0010b
WREN - Set Write Enable Latch
The FM25C160 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the status register
and writing the memory.
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write to
the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further writes
without another WREN command. Figure 5 below
illustrates the WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
status register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 3.1
July 2007
Page 5 of 13
FM25C160 - Automotive Temp.
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25C160 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25C160, /WP only prevents writing to
the Status register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch. The bus
timing for RDSR and WRSR are shown below.
Figure 7. RDSR Bus Timing
Figure 8. WRSR Bus Timing
Status Register & Write Protection
The write protection features of the FM25C160 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status register. As described above,
writes to the status register are performed using the
WRSR command and subject to the /WP pin. The
Status register is organized as follows.
Table 2. Status Register
Bit
Name
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (/RDY in EEPROMs) is wired low
since FRAM writes have no delay and the memory is
never busy. All EEPROMs use Ready to indicate
whether a write cycle is complete or not. The WPEN,
BP1 and BP0 control write protection features. They
Rev. 3.1
July 2007
are nonvolatile (shaded yellow). The WEL flag
indicates the state of the Write Enable Latch. This bit
is internally set by the WREN command and is
cleared by terminating a write cycle (/CS high) or by
using the WRDI command.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
None
0
1
600h to 7FFh (upper ¼)
1
0
400h to 7FFh (upper ½)
1
1
000h to 7FFh (all)
Page 6 of 13
FM25C160 - Automotive Temp.
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
register is write protected if WPEN=1 and /WP=0.
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, with its relatively high maximum
clock frequency, highlights the fast write capability
of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25C160 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value. The upper 5-bits of the address are don’t care.
In total, the 11-bits specify the address of the first
byte of the write operation. Subsequent bytes are data
and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of 7FFh
is reached, the counter will roll over to 0000h. Data is
written MSB first.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /CS terminates a
WRITE op-code operation.
Rev. 3.1
July 2007
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and /WP is
set to 0. This occurs because the block protect bits
prevent writing memory and the /WP signal in
hardware prevents altering the block protect bits (if
WPEN is high). Therefore in this condition, hardware
must be involved in allowing a write operation. The
following table summarizes the write protection
conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a twobyte address value. The upper 5-bits of the address
are don’t care. In total, the 11-bits specify the address
of the first byte of the read operation. After the opcode and address are complete, the SI line is ignored.
The bus master issues 8 clocks, with one bit read out
for each. Addresses are incremented internally as
long as the bus master continues to issue clocks. If
the last address of 7FFh is reached, the counter will
roll over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
The bus configuration for read and write operations is
shown below.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master takes
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
Page 7 of 13
FM25C160 - Automotive Temp.
Figure 9. Memory Write
Figure 10. Memory Read
Endurance
Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore,
endurance cycles are applied for each access: read or
write. The FRAM architecture is based on an array of
rows and columns. Each access causes an endurance
cycle for an entire row. Therefore, data locations
targeted for substantially differing numbers of cycles
Rev. 3.1
July 2007
should not be located within the same row. In the
FM25C160, there are 512 rows each 32 bits wide.
Regardless, FRAM read and write endurance is
effectively unlimited at the 15 MHz clock speed.
Even at 2000 accesses per second to the same row, 15
years time will elapse before 1012 endurance cycles
occur.
Page 8 of 13
FM25C160 - Automotive Temp.
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Charged Device Model (JEDEC Std JESD22-C101-A)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
4kV
1kV
400V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 125° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
4.5
5.0
5.5
V
IDD
VDD Supply Current
mA
0.5
@ SCK = 1.0 MHz
mA
6.5
@ SCK = 15.0 MHz
ISB
Standby Current
10
@ 85°C
µA
30
@ 125°C
µA
ILI
Input Leakage Current
±1
µA
ILO
Output Leakage Current
±1
µA
VIL
Input Low Voltage
-0.3
0.25 VDD
V
VIH
Input High Voltage
0.75 VDD
VDD + 0.3
V
VOL
Output Low Voltage
0.4
V
@ IOL = 2 mA
VDD – 0.8
VOH
Output High Voltage
V
@ IOH = -2 mA
VHYS
Input Hysteresis
0.05 VDD
V
Notes
1
2
3
3
4
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VIN or VOUT = VSS to VDD.
4. This parameter is characterized but not 100% tested. Applies only to /CS and SCK pins.
Rev. 3.1
July 2007
Page 9 of 13
FM25C160 - Automotive Temp.
AC Parameters (TA = -40° C to +125° C, VDD = 4.5V to 5.5V unless otherwise specified)
Min
Max
Symbol
Parameter
fCK
SCK Clock Frequency
0
15
tCH
Clock High Time
30
tCL
Clock Low Time
30
tCSU
Chip Select Setup
10
tCSH
Chip Select Hold
10
tOD
Output Disable
25
tODV
Output Data Valid
25
tOH
Output Hold
0
tD
Deselect Time
80
tR
Data In Rise Time
50
tF
Data In Fall Time
50
tSU
Data Setup Time
5
tH
Data Hold Time
5
tHS
/Hold Setup Time
10
tHH
/Hold Hold Time
10
tHZ
/Hold Low to Hi-Z
25
tLZ
/Hold High to Data Active
20
Notes
1.
2.
3.
Notes
1
1
2
2,3
2,3
2
2
tCH + tCL = 1/fCK.
This parameter is characterized and not 100% tested.
Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V)
Symbol
Parameter
CO
Output Capacitance (SO)
CI
Input Capacitance
Notes
1.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
This parameter is characterized and not 100% tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Rev. 3.1
July 2007
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Page 10 of 13
FM25C160 - Automotive Temp.
Serial Data Bus Timing
tD
tF
tCSU
tR
tCL
1/fCK
tCH
tCSH
tH
tSU
tODV
tOH
tOD
/Hold Timing
Data Retention (VDD = 4.5V to 5.5V)
Parameter
Min
Max
Units
Notes
Data Retention
17
Years
@ TA = 55°C (average)
9000
Hours
@ TA = 125°C
Note: The device is guaranteed to retain data after both conditions have been applied : (1) 17 yrs at an average
temperature of 55°C and (2) 9000 hrs at 125°C.
Typical Grade 1 Storage Profile
Typical Grade 1 Operating Profile
25000
1400
1200
1000
20000
Hours
Hours
1600
800
600
400
200
10000
5000
0
0
70
75
80
85
90
95 100 105 110 115 120 125
Temperature (°C)
Rev. 3.1
July 2007
15000
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Temperature (°C)
Page 11 of 13
FM25C160 - Automotive Temp.
Mechanical Drawing
8-pin SOIC (JEDEC MS-012, Variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
Pin 1
0.65
1.27
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.10 mm
0°- 8°
0.19
0.25
45 °
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXX-PT
LLLLLLL
RICYYWW
Legend:
XXXX= part number, P= package type, T= temp (A= Automotive, blank=ind.)
LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25C160, “Green” SOIC package, Automotive, Lot 60018,
Year 2006, Work Week 38
FM25C160GA
A60018G
RIC0638
Rev. 3.1
July 2007
Page 12 of 13
FM25C160 - Automotive Temp.
Revision History
Revision
2.0
2.1
2.2
3.0
Date
3/24/06
6/22/06
10/12/06
1/30/07
3.1
7/12/07
Rev. 3.1
July 2007
Summary
Created automotive temperature spec.
Changed VIH/VIL spec limits. Added comment to Note 4 in DC Table.
Updated Data Retention table and added typical operating/storage profiles.
Changed to Production status. Passed AEC Q100 testing. Added ESD
Machine Model rating.
Changed to Production status. Changed Data Retention table.
Page 13 of 13