256MB, 512MB, 1GB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 256Mb E-die with 72-bit ECC Revision 1.4 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM Revision History Revision 0.0 (June, 2003) - First release Revision 1.0 (June, 2003) - Revision 1.0 release. Revision 1.1 (September, 2003) - Corrected typo. Revision 1.2 (February, 2004) - Corrected typo. Revision 1.3 (March. 2004) - Modified DC Characteristics Notes. Revision 1.4 (May, 2004) - Added Note 5. sentense of tRDL parameter Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 168Pin Registered DIMM based on 256Mb E-die (x4, x8) Ordering Information Part Number Density Organization Component Composition Component Package Height M390S3253ET1-C7A 256MB 32Mx72 32Mx8(K4S560832E) * 9EA M390S3253ETU-C7A 256MB 32Mx72 32Mx8(K4S560832E) * 9EA 1,500mil 1,200mil M390S6450ET1-C7A 512MB 64Mx72 64Mx4(K4S560432E) * 18EA 1,700mil M390S6450ETU-C7A 512MB 64Mx72 64Mx4(K4S560432E) * 18EA M390S6453ET1-C7A 512MB 64Mx72 32Mx8(K4S560832E) * 18EA 1,700mil M390S2858ET1-C7A 1GB 128Mx72 st.128Mx4(K4S510632E) * 18EA 1,700mil M390S2858ETU-C7A 1GB 128Mx72 st.128Mx4(K4S510632E) * 18EA 1,200mil 54-TSOP(II) 1,200mil Operating Frequencies 7A @CL3 @CL2 Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns) CL-tRCD-tRP(clock) 3-3-3 2-2-2 Feature • • • • • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD Note : 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. ** About these pins, Refer to the Block Diagram of each. Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DQM0 ~ 7 DQM BA0 ~ BA1 Select bank VDD Power supply (3.3V) DQ0 ~ DQ63 Data input/output VSS Ground CB0 ~ CB7 Check bit (Data-in/data-out) *VREF Power supply for reference CLK0 ~ 3 Clock input REGE Register enable CKE0, CKE1 Clock enable input SDA Serial data I/O CS0 ~ CS3 Chip select input SCL Serial clock RAS Row address strobe SA0 ~ 2 Address in EEPROM CAS Colume address strobe DU Don′t use WE Write enable NC No connection * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x4 : CA0 ~ CA9, CA11), (x8 : CA0 ~ CA9) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) REGE Register enable The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 256MB, 32Mx72 ECC Module (M390S3253ET1) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM • PCLK0 BCS0 BCKE0 B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE BDQM0 DQ0~7 • CLK CS CKE Add,CTL DQM DQ0~7 D0 CLK CS CKE Add,CTL DQM DQ0~7 D1 CLK CS CKE Add,CTL DQM DQ0~7 D2 • CLK CS CKE Add,CTL DQM DQ0~7 D3 • CLK CS CKE Add,CTL DQM DQ0~7 D4 CLK CS CKE Add,CTL DQM DQ0~7 D5 CLK CS CKE Add,CTL DQM DQ0~7 D6 CLK CS CKE Add,CTL DQM DQ0~7 D7 CLK CS CKE Add,CTL DQM DQ0~7 D8 • 10Ω • • • DQ8~15 10Ω • PCLK1 • BDQM1 • • CB0~7 10Ω BCS2 • • BDQM2 DQ16~23 10Ω PCLK3 • • BDQM3 DQ24~31 10Ω • DQ32~39 • BDQM4 10Ω • BDQM5 DQ40~47 10Ω • • • BDQM6 DQ48~55 10Ω BDQM7 DQ56~63 10Ω VSS RAS,CAS,WE DQM0,1,4,5 CS0 REGE 74ALVCF162835 B0A0~B0A9 10Ω CLK1,2,3 BRAS,BCAS,BWE BDQM0,1,4,5 BCS0 12pF CDCF2509 10Ω LE CLK0 OE PCLK2 2G AGND 1G AVCL VDD A0~A9 12pF CLK FIBIN 10kΩ PCLK0 PCLK1 PCLK2 PCLK3 FBOUT Cb*1 VDD A10,A11,A12,BA0~1 CS2 CKE0 DQM2,3,6,7 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 74ALVCF162835 Note 1. The actual values of Cb will depend upon the PLL chosen. B0A10,B0A11,B0A12,BBA0~1 BCS2 BCKE0 BDQM2,3,6,7 Serial PD SCL 47KΩ LE OE WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 256MB, 32Mx72 ECC Module (M390S3253ETU) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM PCLK0 BCS0 BCKE0 B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE BDQM0 DQ0~7 • • CLK CS CKE Add,CTL DQM DQ0~7 D0 CLK CS CKE Add,CTL DQM DQ0~7 D1 CLK CS CKE Add,CTL DQM DQ0~7 D2 • CLK CS CKE Add,CTL DQM DQ0~7 D3 • CLK CS CKE Add,CTL DQM DQ0~7 D4 CLK CS CKE Add,CTL DQM DQ0~7 D5 CLK CS CKE Add,CTL DQM DQ0~7 D6 CLK CS CKE Add,CTL DQM DQ0~7 D7 CLK CS CKE Add,CTL DQM DQ0~7 D8 • 10Ω • PCLK1 • • DQ8~15 10Ω PCLK2 • BDQM1 • • CB0~7 10Ω PCLK3 BCS2 • • BDQM2 DQ16~23 10Ω PCLK4 • • BDQM3 DQ24~31 10Ω • DQ32~39 • BDQM4 10Ω • BDQM5 DQ40~47 10Ω • • BDQM6 DQ48~55 10Ω BDQM7 DQ56~63 10Ω VSS RAS,CAS,WE DQM0,1,4,5 CS0 REGE 74ALVCF162835 B0A0~B0A6 10Ω CLK1,2,3 BRAS,BCAS,BWE BDQM0,1,4,5 BCS0 12pF 10Ω CLK0 OE 12pF 10kΩ CLK FIBIN PCLK4 PCLK5 PCLK0 PCLK1 PCLK2 PCLK3 FBOUT Cb*1 Note 1. The actual values of Cb will depend upon the PLL chosen. VDD A7~A12,BA0~1 CS2 CKE0 DQM2,3,6,7 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 CDCF2509 LE PCLK2 2G AGND 1G AVCL VDD A0~A6,BA0~1 74ALVCF162835 B0A7~B0A12,BBA0~BBA1 BCS2 BCKE0 BDQM2,3,6,7 Serial PD SCL 47KΩ LE OE WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 512MB 64Mx72 ECC Module (M390S6450ET1) (Populated as 1 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE BDQM0 DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D0 CLK CS CKE Add,CTL DQM DQ0~3 D1 CLK CS CKE Add,CTL DQM DQ0~3 D2 CLK CS CKE Add,CTL DQM DQ0~3 D3 CLK CS CKE Add,CTL DQM DQ0~3 D4 CLK CS CKE Add,CTL DQM DQ0~3 D5 CLK CS CKE Add,CTL DQM DQ0~3 D6 CLK CS CKE Add,CTL DQM DQ0~3 D7 CLK CS CKE Add,CTL DQM DQ0~3 D8 CLK CS CKE Add,CTL DQM DQ0~3 D9 D10 DQ36~39 CLK CS CKE Add,CTL DQM DQ0~3 D11 DQ40~43 CLK CS CKE Add,CTL DQM DQ0~3 D12 DQ44~47 CLK CS CKE Add,CTL DQM DQ0~3 D13 CB4~7 CLK CS CKE Add,CTL DQM DQ0~3 D14 DQ48~51 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D15 CLK CS CKE Add,CTL DQM DQ0~3 D16 CLK CS CKE Add,CTL DQM DQ0~3 D17 B1CKE0 BDQM4 DQ32~35 10Ω 10Ω DQ4~7 10Ω PCLK1 BDQM1 DQ8~11 10Ω BDQM5 10Ω 10Ω PCLK2 DQ12~15 10Ω 10Ω CB0~3 10Ω 10Ω PCLK3 BCS2 DQ16~19 10Ω PCLK4 BDQM2 DQ20~23 10Ω BDQM6 DQ52~55 10Ω 10Ω DQ24~27 DQ56~59 10Ω 10Ω PCLK5 B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE BDQM3 DQ28~31 BDQM7 DQ60~63 10Ω 10Ω VSS 74ALVCF162835 VDD B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0 10Ω CLK1,2,3 12pF 2G AGND 1G AVCL VDD A3~A10,BA0 CDCF2510 10kΩ PCLK6 REGE A11,A12,BA1 LE OE CLK0 74ALVCF162835 CS2 CKE0 DQM2,3,6,7 LE A0,A1,A2 OE 74ALVCF162835 RAS,CAS,WE CS0 DQM0,1,4,5 LE 10Ω OE B0A11.B0A12.B0BA1 B1A11.B1A12.B1BA1 BCS2 B0CKE0 B1CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0 BDQM0,1,4,5 12pF CLK FIBIN PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 IY0 IY1 IY2 IY3 IY4 2Y0 2Y1 FBOU Cb*1 Note 1. The actual values of Cb will depend upon the PLL chosen. Serial PD SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 512MB 64Mx72 ECC Module (M390S6450ETU) (Populated as 1 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE BDQM0 DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D0 CLK CS CKE Add,CTL DQM DQ0~3 D1 CLK CS CKE Add,CTL DQM DQ0~3 D2 CLK CS CKE Add,CTL DQM DQ0~3 D3 CLK CS CKE Add,CTL DQM DQ0~3 D4 CLK CS CKE Add,CTL DQM DQ0~3 D9 D10 DQ36~39 CLK CS CKE Add,CTL DQM DQ0~3 D11 DQ40~43 CLK CS CKE Add,CTL DQM DQ0~3 D12 DQ44~47 CLK CS CKE Add,CTL DQM DQ0~3 D13 CB4~7 CLK CS CKE Add,CTL DQM DQ0~3 DQ48~51 CLK CS CKE Add,CTL DQM DQ0~3 DQ32~35 10Ω BDQM4 10Ω PCLK1 DQ4~7 10Ω 10Ω PCLK2 BDQM1 DQ8~11 10Ω PCLK3 DQ12~15 BDQM5 10Ω 10Ω 10Ω PCLK4 CB0~3 10Ω 10Ω PCLK5 BCS2 CLK CS CKE Add,CTL DQM DQ0~3 BDQM2 DQ16~19 D5 BDQM6 10Ω 10Ω PCLK6 DQ20~23 CLK CS CKE Add,CTL DQM DQ0~3 D6 CLK CS CKE Add,CTL DQM DQ0~3 D7 CLK CS CKE Add,CTL DQM DQ0~3 D8 DQ52~55 10Ω 10Ω PCLK7 BDQM3 DQ24~27 BDQM7 DQ56~59 D14 CLK CS CKE Add,CTL DQM DQ0~3 D15 CLK CS CKE Add,CTL DQM DQ0~3 D16 CLK CS CKE Add,CTL DQM DQ0~3 D17 10Ω 10Ω PCLK8 BCS2 B1CKE0 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE DQ28~31 10Ω DQ60~63 10Ω VSS 74ALVCF162835 VDD B0A0~B0A12,B0BA0~1, B0RAS, B0CAS B0CKE0 B1CKE0 CLK1,2,3 12pF 10kΩ PCLK9 REGE VDD 10Ω LE 2G AGND 1G AVCL A0~A12,BA0~1, RAS, CAS CKE0 CDCF2510 OE 10Ω 74ALVCF162835 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS CLK0 12pF CLK FIBIN IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK9 PCLK5 PCLK6 PCLK7 PCLK8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 FBOUT Cb*1 LE Note 1. The actual values of Cb will depend upon the PLL chosen. OE 74ALVCF162835 WE Serial PD B0WE B1WE BDQM0~7, BCS0,BCS2 DQM0~7,CS0,CS2 LE OE SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 512MB, 64Mx72 ECC Module (M390S6453ET1) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE BDQM0 DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D0 CLK CS CKE Add,CTL DQM DQ0~3 D1 CLK CS CKE Add,CTL DQM DQ0~3 D2 CLK CS CKE Add,CTL DQM DQ0~3 D3 CLK CS CKE Add,CTL DQM DQ0~3 D4 CLK CS CKE Add,CTL DQM DQ0~3 D5 CLK CS CKE Add,CTL DQM DQ0~3 D6 CLK CS CKE Add,CTL DQM DQ0~3 D7 CLK CS CKE Add,CTL DQM DQ0~3 D8 CLK CS CKE Add,CTL DQM DQ0~3 D9 D10 DQ36~39 CLK CS CKE Add,CTL DQM DQ0~3 D11 DQ40~43 CLK CS CKE Add,CTL DQM DQ0~3 D12 DQ44~47 CLK CS CKE Add,CTL DQM DQ0~3 D13 CB4~7 CLK CS CKE Add,CTL DQM DQ0~3 D14 DQ48~51 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D15 CLK CS CKE Add,CTL DQM DQ0~3 D16 CLK CS CKE Add,CTL DQM DQ0~3 D17 B1CKE0 BDQM4 DQ32~35 10Ω 10Ω DQ4~7 10Ω PCLK1 BDQM1 DQ8~11 10Ω BDQM5 10Ω 10Ω PCLK2 DQ12~15 10Ω 10Ω CB0~3 10Ω 10Ω PCLK3 BCS2 DQ16~19 10Ω PCLK4 BDQM2 DQ20~23 10Ω BDQM6 DQ52~55 10Ω 10Ω DQ24~27 DQ56~59 10Ω 10Ω PCLK5 B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE BDQM3 DQ28~31 BDQM7 DQ60~63 10Ω 10Ω VSS 74ALVCF162835 VDD B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0 10Ω CLK1,2,3 12pF 2G AGND 1G AVCL VDD A3~A10,BA0 CDCF2510 10kΩ PCLK6 REGE A11,A12,BA1 LE CLK0 74ALVCF162835 CS2 CKE0 DQM2,3,6,7 LE A0,A1,A2 OE 74ALVCF162835 RAS,CAS,WE CS0 DQM0,1,4,5 LE 10Ω OE OE B0A11.B0A12.B0BA1 B1A11.B1A12.B1BA1 BCS2 B0CKE0 B1CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0 BDQM0,1,4,5 12pF CLK FIBIN IY0 PCLK0 IY1 PCLK1 IY2 PCLK2 IY3 PCLK3 IY4 PCLK4 2Y0 PCLK5 2Y1 PCLK6 FBOUT Cb*1 Note 1. The actual values of Cb will depend upon the PLL chosen. Serial PD SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 1GB, 128Mx72 ECC Module (M390S2858ET1) (Populated as 2 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM BCS1,B2CKE0 BCS0,B0CKE0 PCLK0 B0RAS,B0CAS,B0WE,B0BA0,B0BA1 B0A0~B0A12 BDQM0 DQ0~3 10Ω PCLK1 DQ4~7 10Ω PCLK2 BDQM1 DQ8~11 10Ω PCLK3 DQ12~15 10Ω PCLK4 CB0~3 10Ω CLK CS1,CKED0L CTL Add DQM DQ0~3 CLK CS0,CKED0U CTL Add DQM DQ0~3 CLK CS1,CKED1L CTL Add DQM DQ0~3 CLK CS0,CKED1U CTL Add DQM DQ0~3 CLK CS1,CKED2L CTL Add DQM DQ0~3 CLK CS0,CKED2U CTL Add DQM DQ0~3 CLK CS1,CKED3L CTL Add DQM DQ0~3 CLK CS0,CKED3U CTL Add DQM DQ0~3 CLK CS1,CKED4L CTL Add DQM DQ0~3 CLK CS0,CKED4U CTL Add DQM DQ0~3 CLK CS1,CKED5L CTL Add DQM DQ0~3 CLK CS0,CKED5U CTL Add DQM DQ0~3 CLK CS1 CTL Add DQM DQ0~3 CLK CS0,CKED6U CTL Add DQM DQ0~3 BDQM4 DQ32~35 10Ω DQ36~39 10Ω BDQM5 DQ40~43 10Ω DQ44~47 10Ω CB4~7 10Ω CLK CS0,CKE D9L CTL Add DQM DQ0~3 CLK CS1,CKED9U CTL Add DQM DQ0~3 CLK CS0,CKE D10L CTL Add DQM DQ0~3 CLK CS1,CKED10U CTL Add DQM DQ0~3 CLK CS0,CKED11L CTL Add DQM DQ0~3 CLK CS1,CKED11U CTL Add DQM DQ0~3 CLK CS0,CKE D12L CTL Add DQM DQ0~3 CLK CS1,CKED12U CTL Add DQM DQ0~3 CLK CS0,CKE D13L CTL Add DQM DQ0~3 CLK CS1,CKED13U CTL Add DQM DQ0~3 CLK CS0,CKE D14L CTL Add DQM DQ0~3 CLK CS1,CKED14U CTL Add DQM DQ0~3 CLK CS0,CKE D15L CTL Add DQM DQ0~3 CLK CS1,CKED15U CTL Add DQM DQ0~3 CLK D16L CS0,CKE CTL Add DQM DQ0~3 CLK CS1,CKED16U CTL Add DQM DQ0~3 CLK CS0,CKE D17L CTL Add DQM DQ0~3 CLK CS1,CKED17U CTL Add DQM DQ0~3 BCS3,B3CKE0 BCS2,B1CKE0 PCLK5 BDQM2 DQ16~19 10Ω PCLK6 DQ20~23 10Ω PCLK7 BDQM3 DQ24~27 10Ω PCLK8 B1RAS,B1CAS,B1WE,B1BA0,B1BA1 B1A0~B1A12 DQ28~31 10Ω D6L CLK CS1,CKED7L CTL Add DQM DQ0~3 CLK CS0,CKED7U CTL Add DQM DQ0~3 CLK CS1,CKED8L CTL Add DQM DQ0~3 CLK CS0,CKED8U CTL Add DQM DQ0~3 BDQM6 DQ48~51 10Ω DQ52~55 10Ω BDQM7 DQ56~59 10Ω DQ60~63 10Ω VSS 74ALVCF162835 B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0 VDD 10Ω G AGND AVDD A3~A10,BA0 CLK1,2,3 VDD 12pF CDCF2510 10kΩ PCLK9 REGE LE OE A11,A12,BA1 74ALVCF162835 CS2,CS3 CKE0 DQM2,3,6,7 LE OE A0,A1,A2 74ALVCF162835 RAS,CAS,WE CS0,CS1 DQM0,1,4,5 LE 10Ω OE CLK FBIN CLK0 B0A11,B0A12.B0BA1 B1A11,B1A12.B1BA1 BCS2,BCS3 B0CKE0,B1CKE0 B2CKE0,B3CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0,BCS1 BDQM0,1,4,5 12pF IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 FBOU Cb PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 PCLK8 PCLK9 *1 Note 1. The actual values of Cb will depend upon the PLL chosen. Serial PD SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM 1GB, 128Mx72 ECC Module (M390S2858ETU) (Populated as 2 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM BCS1 PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE BDQM0 DQ0~3 10Ω PCLK1 DQ4~7 10Ω PCLK2 BDQM1 DQ8~11 10Ω PCLK3 DQ12~15 10Ω PCLK4 CB0~3 10Ω PCLK5 BCS2 CLK CS CKE Add,CTL DQM DQ0~3 D0L CLK CS CKE Add,CTL DQM DQ0~3 D1L CLK CS CKE Add,CTL DQM DQ0~3 D2L CLK CS CKE Add,CTL DQM DQ0~3 D3L CLK CS CKE Add,CTL DQM DQ0~3 D4L CLK CS CKE Add,CTL DQM DQ0~3 BDQM2 DQ16~19 10Ω CLK CS CKE Add,CTL DQM DQ0~3 PCLK6 DQ20~23 10Ω PCLK7 BDQM3 DQ24~27 10Ω PCLK8 BCS2 B1CKE0 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE BDQM0 DQ28~31 10Ω D5L CLK CS CKE Add,CTL DQM DQ0~3 D0U CLK CS CKE Add,CTL DQM DQ0~3 D1U CLK CS CKE Add,CTL DQM DQ0~3 D2U CLK CS CKE Add,CTL DQM DQ0~3 D3U CLK CS CKE Add,CTL DQM DQ0~3 D4U CLK CS CKE Add,CTL DQM DQ0~3 BDQM4 DQ32~35 10Ω 10Ω DQ36~39 BDQM5 DQ40~43 10Ω 10Ω DQ44~47 10Ω CB4~7 BDQM6 DQ48~51 10Ω CLK CS CKE Add,CTL DQM DQ0~3 D6U CLK CS CKE Add,CTL DQM DQ0~3 D7L CLK CS CKE Add,CTL DQM DQ0~3 D7U CLK CS CKE Add,CTL DQM DQ0~3 D8L CLK CS CKE Add,CTL DQM DQ0~3 D8U D9L CLK CS CKE Add,CTL DQM DQ0~3 D9 CLK CS CKE Add,CTL DQM DQ0~3 D10L CLK CS CKE Add,CTL DQM DQ0~3 D10 CLK CS CKE Add,CTL DQM DQ0~3 D11L CLK CS CKE Add,CTL DQM DQ0~3 D11 CLK CS CKE Add,CTL DQM DQ0~3 D12L CLK CS CKE Add,CTL DQM DQ0~3 D12 CLK CS CKE Add,CTL DQM DQ0~3 D13L CLK CS CKE Add,CTL DQM DQ0~3 D13 D14L CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 D15L CLK CS CKE Add,CTL DQM DQ0~3 D15 CLK CS CKE Add,CTL DQM DQ0~3 D16L CLK CS CKE Add,CTL DQM DQ0~3 D16 CLK CS CKE Add,CTL DQM DQ0~3 D17L CLK CS CKE Add,CTL DQM DQ0~3 D17 CLK CS CKE Add,CTL DQM DQ0~3 D5U D6L CLK CS CKE Add,CTL DQM DQ0~3 DQ52~55 10Ω BDQM7 DQ56~59 10Ω BDQM7 DQ60~63 10Ω D14 BCS3 VSS 74ALVCF162835 VDD B0A0~B0A12,B0BA0~1, B0RAS, B0CAS B0CKE0 B1CKE0 CLK1,2,3 12pF 10kΩ PCLK9 REGE VDD 10Ω LE 2G AGND 1G AVCL A0~A12,BA0~1, RAS, CAS CKE0 CDCF2510 OE 10Ω 74ALVCF162835 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS CLK0 12pF CLK FIBIN IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK9 PCLK5 PCLK6 PCLK7 PCLK8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 FBOUT Cb*1 LE Note 1. The actual values of Cb will depend upon the PLL chosen. OE 74ALVCF162835 WE DQM0~7,CS0~3 Serial PD B0WE,B0CKE1 B1WE,B1CKE1 BDQM0~7, BCS0~3 LE OE SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4) *2 REG *1 *3 D Control Signal(RAS,CAS,WE) OUT *1. Register Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK RAS CAS WE *2. Register Output RAS td tr td tr CAS WE *3. SDRAM CAS latency(refer to *1) =2CLK+1CLK 1CLK tSAC tRAC(refer to *1) DQ Qa0 tRAC(refer to *2) Row Active Read Command Qa1 Qa2 Db0 Qa3 Db1 CAS latency(refer to *2) =2CLK Precharge Command Db2 Db3 tRDL Row Active Write Command Precharge Command td, tr = Delay of register Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal because of the buffering in register. Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module. : Don′t care Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1.0 * # of component W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input low voltage VIL -0.3 0 0.8 V 2 Output high voltage VOH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE(Max.) (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Symbol M390S3253ET1 M390S3253ETU M390S6450ET1 M390S6450ETU M390S6453ET1 M390S2858ET1 M390S2858ETU Unit Input capacitance (A0 ~ A11) CIN1 15 15 19 15 pF Input capacitance (RAS, CAS, WE) CIN2 15 15 19 15 pF Input capacitance (CKE0) CIN3 15 15 33 15 pF Input capacitance (CLK0) CIN4 23 20 12 20 pF Input capacitance (CS0, CS2) CIN5 15 15 12 15 pF Input capacitance (DQM0 ~ DQM7) CIN6 15 15 12 15 pF Input capacitance (BA0 ~ BA1) CIN7 15 15 12 15 pF Data input/output capacitance(DQ0~DQ63) COUT1 16 16 19 22 pF Data input/ouput capacitance (CB0~CB7) COUT2 16 16 19 22 pF Parameter Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM DC CHARACTERISTICS M390S3253ETU(1) (32M x 72, 256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V Version 7A Unit Note 1,220 mA 1 370 20 mA 530 mA 95 405 60 mA 575 mA 230 mA 1,400 mA 1 2,120 380 mA mA 2 Version 7A Unit Note 1,940 mA 1 370 40 mA M390S6450ETU(1) (64M x 72, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V 710 mA 185 460 110 mA 800 mA 455 mA 2,300 mA 1 3,740 405 mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM DC CHARACTERISTICS M390S6453ET1 (64M x 72, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V Version 7A Unit Note 1,445 mA 1 390 40 mA 710 mA 185 460 110 mA 800 mA 455 mA 1,625 mA 1 2,345 405 mA mA 2 Version 7A Unit Note 2,390 mA 1 425 75 mA M390S2858ETU(1) (128M x 72, 1GB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V 1,070 mA 365 570 220 mA 1,250 mA 905 mA 2,750 mA 1 4,190 460 mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note 7A Row active to row active delay tRRD(min) 15 ns 1 RAS to CAS delay tRCD(min) 20 ns 1 tRP(min) 20 ns 1 1 Row precharge time tRAS(min) 45 ns tRAS(max) 100 us Row cycle time tRC(min) 65 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2,5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Row active time Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Number of valid output data CAS latency=3 2 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter 7A Symbol Min CLK cycle time CAS latency=3 CLK to valid output delay CAS latency=3 Output data hold time tCC CAS latency=2 7.5 Note 1000 ns 1 ns 1,2 ns 2 10 5.4 tSAC CAS latency=2 CAS latency=3 Unit Max 6 tOH CAS latency=2 3 3 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 ns 6 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh (V=Valid, X=Don′t care, H=Logic high, L=Logic low) CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh H Bank active & row addr. H X Read & column address H X Auto precharge disable Precharge L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H H L H L L X Entry H L Exit L H Entry H L Precharge power down mode Exit L V Column address L X X All banks Clock suspend or active power down L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address H H Bank selection 3 Row address H H Note 1,2 X Auto precharge enable Burst stop A0 ~ A9, A11, A12 3 Auto precharge enable Auto precharge disable A10/AP L L Write & column address Exit H BA0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 32Mx72 (M390S3253ET1) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) REG B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) PLL C 0.250 (6.350) 0.250 (6.350) .450 (11.430) 0.700 (17.780) REG 0.0984 ±0.008 (2.500 ±0.2) 0.118 (3.000) 1.500 (38.1) 0.157 ± 0.004 (4.000 ± 0.100) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.157 Min (3.99 Min) 0.150 Max (3.81 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 32Mx72 (M390S3253ETU) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.350 (8.890) REG B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) C 0.250 (6.350) 0.250 (6.350) .450 (11.430) 0.700 (17.780) REG 0.0984 ±0.008 (2.500 ±0.2 ) 0.118 (3.000) 1.200 (38.1) PLL 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.157 Min (3.99 Min) 0.150 Max (3.81 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 64Mx72 (M390S6450ET1) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) C 0.250 (6.350) 0.250 (6.350) .450 (11.430) PLL B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) REG 0.700 (17.780) REG 0.0984 ±0.008 (2.500 ±0.2) 0.118 (3.000) 1.700 (43.18) 0.157 ± 0.004 (4.000 ± 0.100) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.150 Max (3.81 Max) 0.165 Min (4.19 Min) REG 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 64Mx4 SDRAM, TSOPII SDRAM Part No. : K4S560432E This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 64Mx72 (M390S6450ETU) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) REG 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.700 (17.780) REG 0.118 (3.000) 1.200 (30.48) PLL 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.157 Min REG (3.99 Min) 0.150 Max (3.81 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 64Mx4 SDRAM, TSOPII SDRAM Part No. : K4S560432E This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 64Mx72 (M390S6453ET1) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) C 0.250 (6.350) 0.250 (6.350) .450 (11.430) PLL B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) REG 0.700 (17.780) REG 0.0984 ±0.008 (2.500 ±0.2) 0.118 (3.000) 1.700 (43.18) 0.157 ± 0.004 (4.000 ± 0.100) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.150 Max (3.81 Max) 0.165 Min (4.19 Min) REG 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances :± 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 128Mx72 (M390S2858ET1) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) C 0.250 (6.350) 0.250 (6.350) .450 (11.430) PLL B A .118DIA ± 0.004 (3.000DIA ± 0.100) 0.350 (8.890) REG 0.700 (17.780) REG 0.100 Min (2.540 Min) 0.118 (3.000) 1.700 (43.18) 0.157 ± 0.004 (4.000 ± 0.100) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.254 Max (6.452 Max) 0.157 Min (3.99 Min) REG 0.100 Min 0.250 (6.350) 0.250 (6.350) Detail A 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified SDRAM Part No. : K4S510632E - The used device is stacked 128Mx4 SDRAM, TSOPII - Staktek’s stacking technology is Samsung’s stacking technology of choice This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004 256MB, 512MB, 1GB Registered DIMM SDRAM PACKAGE DIMENSIONS : 128Mx72 (M390S2858ETU) Units : Inches (Millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) B A C 0.250 (6.350) 0.250 (6.350) .450 (11.430) 0.100 Min (2.540 Min) REG .118DIA ± 0.004 (3.000DIA ± 0.100) 0.350 (8.890) 0.700 (17.780) REG 0.118 (3.000) 1.200 (30.48) PLL 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.254 Max (6.452 Max) 0.157 Min (3.99 Min) REG 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified SDRAM Part No. : K4S510632E - The used device is stacked 128Mx4 SDRAM, TSOPII - Staktek’s stacking technology is Samsung’s stacking technology of choice This module is based on JEDEC PC133 Specification Rev. 1.4 May 2004