Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
0.1
0.2
0.3
0.4
History
1) Initial Draft.
1) Correct Fig.10 Sequential out cycle after read
2) Add the text to Fig.1, Table.1, Table.2
- text : IO15 - IO8 (x16 only)
3) Delete ‘3.2 Page program NOTE 1.
- Note : if possible it is better to remove this constrain
4) Change the text ( page 10,13, 45)
- 2.2 Address Input : 28 Addresses -> 27 Addresses
- 3.7 Reset : Fig.29 -> Fig.30
- 5.1 Automatic page read after power up : Fig.30 -> Fig.29
5) Add 5.3 Addressing for program operation & Fig.34
1) Change TSOP, WSOP, FBGA package dimension & figures.
- Change TSOP, WSOP, FBGA package mechanical data
- Change FBGA thickness (1.2 -> 1.0 mm)
2) Correct TSOP, WSOP Pin configurations.
- 38th NC pin has been changed Lockpre(figure 3,4)
3) Edit figure 15,19 & table 4
4) Add Bad Block Management
5) Change Device Identifier 3rd Byte
- 3rd Byte ID is changed. (reserved -> don't care)
- 3rd Byte ID table is deleted.
1) Add Errata
tCLS
tCLH
tWP
tALS
tALH
tDS
tWC
tR
Specification
0
10
25
0
10
20
50
25
Relaxed value
5
15
40
5
15
25
60
27
2) LOCKPRE is changed to PRE.
- Texts, Table, Figures are changed.
3) Add Note.4 (table.14)
4) Block Lock Mechanism is deleted.
- Texts, Table, figures are deleted.
5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)
- Texts & Figures are added.
6) Edit the figures. (#10~25)
1) Change AC characteristics(tREH)
before: 20ns -> after: 30ns
2) Edit Note.1 (page. 21)
3) Edit the Application note 1,2
4) Edit The Address cycle map (x8, x16)
Rev 0.7 / Apr. 2005
Draft Date
Remark
Aug. 2004
Preliminary
Sep. 2004
Preliminary
Oct. 2004
Preliminary
Nov.29 2004
Preliminary
Jan.19 2005
Preliminary
1
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Revision History
- Continued -
Revision
No.
History
Draft Date
Remark
Jan. 25. 2005
Preliminary
Mar. 09. 2005
Preliminary
Apr. 06. 2005
Preliminary
1) Correct AC characteristics(tREH)
before: 30ns-> after: 20ns
2) Add Errata
Case
0.5
tRC
tRP
tREH
tREA
50
20
20
30
Except for
ID Read
50
20
20
30
ID Read
60
25
30
30
Specification Read(all)
Relaxed
value
1) Change AC characteristics
tDH
0.6
Before
10
After
15
2) Add tADL parameter
- tADL=100ns
3) Correct table.9
1) Correct AC Timing Characteristics Table
- Errata value is eddited.
- tADL(max) is changed to tADL(min).
2) Change Errata
- tREA is deleted from the errata
Before
After
0.7
Case
tRC
tRP
tREH
Except for
ID Read
50
20
20
ID Read
60
25
30
Read (all)
60
25
30
3) Edit pin Description table
4) Delete Multiple Die & Stacked Devices Access
- Texts & tables are deleted.
5) Edit Data Protection texts
6) Add Read ID table
7) Add tOH parameter
- tOH=15ns(min.)
8) Add Marking Information
9) Correct application note.2
- tCS(2us) is changed to 100ns.
Rev 0.7 / Apr. 2005
2
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
STATUS REGISTER
- Pinout compatibility for all densities
ELECTRONIC SIGNATURE
- Manufacturer Code
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
- Device Code
: HY27UFXX1G2M
- 1.8V device: VCC = 1.7 to 1.95V : HY27SFXX1G2M
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 1,024 Blocks
= (1K+32) Words x 64 pages x 1,024 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27(U/S)F081G2M
- x16 device: (1K + 32 spare) Words
: HY27(U/S)F161G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 27us(1) (max.)
- Sequential access: 60ns(1) (min.)
- Page program time: 300us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
NOTE:
1. These parameters are applied to the errata.
Rev 0.7 / Apr. 2005
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27(U/S)F(08/16)1G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)F(08/16)1G2M-T (Lead)
- HY27(U/S)F(08/16)1G2M-TP (Lead Free)
- HY27(U/S)F(08/16)1G2M-V(P)
: 48-Pin WSOP1 (12 x 17 x 0.7 mm)
- HY27(U/S)F(08/16)1G2M-V (Lead)
- HY27(U/S)F(08/16)1G2M-VP (Lead Free)
- HY27(U/S)F(08/16)1G2M-F(P)
: 63-Ball FBGA (9.5 x 12 x 1.0 mm)
- HY27(U/S)F(08/16)1G2M-F (Lead)
- HY27(U/S)F(08/16)1G2M-FP (Lead Free)
3
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V
Vcc Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 60ns(1) cycle time per word. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27(U/S)F(08/16)1G2M extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.
The HYNIX HY27(U/S)F(08/16)1G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - WSOP1 12 x 17 mm,
FBGA 9.5 x 12 mm.
1.1 Product List
PART NUMBER
ORIZATION
HY27SF081G2M
x8
HY27SF161G2M
x16
HY27UF081G2M
x8
HY27UF161G2M
x16
VCC RANGE
PACKAGE
1.70 - 1.95 Volt
63FBGA / 48TSOP1 / 48WSOP1
2.7V - 3.6 Volt
NOTE: 1. This parameters is applied to the errata.
Rev 0.7 / Apr. 2005
4
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
9&&
&(
,2a,2
,2a,2 [2QO\
:(
5%
5(
$/(
&/(
:3
35(
966
Figure1: Logic Diagram
IO15 - IO8
Data Input / Outputs (x16 only)
IO7 - IO0
Data Input / Outputs
CLE
Command latch enable
ALE
Address latch enable
CE#
Chip Enable
RE#
Read Enable
WE#
Write Enable
WP#
Write Protect
RB#
Ready / Busy
Vcc
Power Supply
Vss
Ground
NC
No Connection
PRE
Power-On Read Enable
Table 1: Signal Names
Rev 0.7 / Apr. 2005
5
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
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1$1')ODVK
7623
[
1&
1&
1&
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,2
,2
,2
,2
1&
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35(
9FF
9VV
1&
1&
1&
,2
,2
,2
,2
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
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9VV
1&
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&/(
$/(
:(
:3
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7623
9VV
,2
,2
,2
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,2
,2
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1&
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9FF
1&
1&
1&
,2
,2
,2
,2
,2
,2
,2
,2
9VV
[
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
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1$1')ODVK
:623
[
1&
1&
1&
1&
,2
,2
,2
,2
1&
1&
35(
9FF
9VV
1&
1&
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,2
,2
,2
,2
1&
1&
1&
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&(
1&
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9VV
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:(
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:623
[
9VV
,2
,2
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1&
35(
9FF
1&
1&
1&
,2
,2
,2
,2
,2
,2
,2
,2
9VV
Figure 3. 48WSOP1 Contactions, x8 and x16 Device
Rev 0.7 / Apr. 2005
6
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
$
1&
%
1&
1&
&
:3
'
$/(
9VV
&(
:(
5%
1&
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1&
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(
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1&
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/
1&
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1&
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Figure 4. 63FBGA Contactions, x8 Device (Top view through package)
$
1&
%
1&
1&
&
:3
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9VV
&(
:(
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'
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Figure 5. 63FBGA Contactions, x16 Device (Top view through package)
Rev 0.7 / Apr. 2005
7
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name
Description
IO0-IO7
IO8-IO15(1)
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
CLE
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE#).
ALE
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE#).
CE#
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect
the memory.
WE#
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data
is valid tREA after the falling edge of RE# which also increments the internal column address counter
by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program /
erase) operations.
RB#
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
VSS
GROUND
NC
NOT CONNECTED
To Enable Power On Auto Read. When PRE is a logic high, Power on Auto Read mode is enabled, and
PRE
when PRE is a logic low, Power Auto Read mode is disabled. Power On Auto Read mode is available
only on 3.3V device.
Not using POWER-ON AUTO-READ, connect it Vss or leave it N.C.
Table 2: Pin Description
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev 0.7 / Apr. 2005
8
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
0
0
0
0
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
Table 3: Address Cycle Map(x8)
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
0
0
0
0
0
3rd Cycle
A11
A12
A13
A14
A15
A16
A17
A18
4th Cycle
A19
A20
A21
A22
A23
A24
A25
A26
Table 4: Address Cycle Map(x16)
FUNCTION
1st CYCLE
2nd CYCLE
3rd CYCLE
READ 1
00h
30h
-
READ FOR COPY-BACK
00h
35h
-
READ ID
90h
-
-
RESET
FFh
-
-
PAGE PROGRAM (start)
80h
10h
-
COPY BACK PGM (start)
85h
10h
-
CACHE PROGRAM
80h
15h
-
BLOCK ERASE
60h
D0h
-
READ STATUS REGISTER
70h
-
-
RANDOM DATA INPUT
85h
-
-
RANDOM DATA OUTPUT
05h
E0h
-
CACHE READ START
00h
31h
-
CACHE READ EXIT
34h
-
-
Acceptable command
during busy
Yes
Yes
Table 5: Command Set
Rev 0.7 / Apr. 2005
9
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
CLE
ALE
CE#
WE#
RE#
WP#
H
L
L
Rising
H
X
L
H
L
Rising
H
X
H
L
L
Rising
H
H
L
H
L
Rising
H
H
L
L
L
Rising
H
H
Data Input
L
(1)
H
Falling
X
Sequential Read and Data Output
L
L
MODE
Read Mode
Write Mode
Command Input
Address Input(4 cycles)
Command Input
Address Input(4 cycles)
L
L
L
H
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/Vcc
Stand By
Table 6: Mode Selection
NOTE:
1. With the CE# don’t care option CE# high during latency time does not stop the read operation
Rev 0.7 / Apr. 2005
10
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 7 and table 13 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 27 addresses(x8 device) needed
to access the 1Gbit 4 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable
High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 8 and table 13
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration
(X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
9 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 10,12,13 and table 13 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.7 / Apr. 2005
11
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h
to the command register along with four address cycles. In two consecutive read operations, the second one doesn’t’
need 00h command, which four address cycles and 30h command initiates that operation. Two types of operations are
available : random read, serial page read. The random read mode is enabled when the page address is changed. The
2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data registers in less than 27us(1)(tR). The system controller may detect the completion of this data transfer (tR) by analyzing
the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 60ns(1) cycle
time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consecutive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of
consecutive partial page programming operation within the same page without an intervening erase operation must
not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array
(X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block 1. A page program cycle consists of a serial data
loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data
register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate
cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the program process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the RB# output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 15 details the sequence.
NOTE:
1. These parameters are applied to the errata.
Rev 0.7 / Apr. 2005
12
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid while A12 to A17 (X8) or A11 to A16
(X16) is ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing
process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of the
Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the
erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copying-program with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back
command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is
required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 17.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 17 shows the command sequence for the copy-back operation.
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or
RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when RB# pins are common-wired. RE# or CE# does not need to be toggled for updated
status. Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read
command (00h) should be given before starting read cycles. See figure 11 for details of the Read Status operation.
Rev 0.7 / Apr. 2005
13
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h,
4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 20 shows the operation sequence, while tables 16, 17 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high. If the device
is already in reset state a new reset command will not be accepted by the command register. The RB# pin transitions
to low for tRST after the Reset command is written. Refer to figure 25.
3.8 Cache Program.
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data
input may be executed while data stored in data register are programmed into memory cell. After writing the first set
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period
of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers
become ready by polling the Cache-Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon
the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by
the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The
status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the progress of programming only with RB#, the last page of the target programming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See figure 18 for more details.
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the
last page is initiated only after completion of the previous cycle, which can be expressed as the following
formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page (Program command cycle time + Last page data loading time)
Rev 0.7 / Apr. 2005
14
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.9 Cache Read
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will
be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device (50us for
x16 device).
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- RB# ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device
internally is active on n+1 page
- Status register (SR<6> behave like RB#, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tCBSY before becoming again idle and ready to accept any further commands.
If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.7 / Apr. 2005
15
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection.
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time
of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 26. The
two-step command sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache program and random read completion. The RB# pin is normally high and goes to low when the
device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more RB# outputs to be Or-tied. Because
pull-up resistor value is related to tr(RB#) and current drain during busy (Ibusy), an appropriate value can be obtained
with the following reference chart (Fig.27). Its value can be determined by the following guidance.
4.3 Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is logic high state. Serial
access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device
(HY27UF(08/16)1G2M).
Rev 0.7 / Apr. 2005
16
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
Symbol
Min
Valid Block Number
NVB
1004
Typ
Max
Unit
1024
Blocks
Table 7: Valid Blocks Number
Symbol
Parameter
Value
Unit
1.8V
3.3V
0 to 70
0 to 70
℃
Ambient Operating Temperature (Extended Temperature Range)
-25 to 85
-25 to 85
℃
Ambient Operating Temperature (Industrial Temperature Range)
-40 to 85
-40 to 85
℃
TBIAS
Temperature Under Bias
-50 to 125
-50 to 125
℃
TSTG
Storage Temperature
-65 to 150
-65 to 150
℃
VIO(2)
Input or Output Voltage
-0.6 to 2.7
-0.6 to 4.6
V
Supply Voltage
-0.6 to 2.7
-0.6 to 4.6
V
Ambient Operating Temperature (Commercial Temperature Range)
TA
Vcc
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 0.7 / Apr. 2005
17
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
$a$
$''5(66
5(*,67(5
&2817(5
352*5$0
(5$6(
&21752//(5
+9*(1(5$7,21
35(
$/(
&/(
:(
&(
:3
5(
;
0ELW0ELW
1$1')ODVK
0(025<$55$<
'
(
&
2
'
(
5
&200$1'
,17(5)$&(
/2*,&
3$*(%8))(5
&200$1'
5(*,67(5
<'(&2'(5
'$7$
5(*,67(5
%8))(56
,2
Figure 6: Block Diagram
Rev 0.7 / Apr. 2005
18
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
Symbol
Test Conditions
Sequential
Read
ICC1
Program
Erase
1.8Volt
3.3Volt
Unit
Min
Typ
Max
Min
Typ
Max
tRC=60ns(1),
CE#=VIL, IOUT=0mA
-
8
15
-
10
20
mA
ICC2
-
-
8
15
-
10
20
mA
ICC3
-
-
8
15
-
10
20
mA
Stand-by Current (TTL)
ICC4
CE#=VIH,
PRE=WP#=0V/Vcc
-
-
1
-
1
mA
Stand-by Current (CMOS)
ICC5
CE#=Vcc-0.2,
PRE=WP#=0V/Vcc
-
10
50
-
10
50
uA
Input Leakage Current
ILI
VIN=0 to 3.6V
-
-
± 10
-
-
± 10
uA
Output Leakage Current
ILO
VOUT=0 to 3.6V
-
-
± 10
-
-
± 10
uA
Input High Voltage
VIH
-
Vcc-0.4
-
Vcc+
0.3
2
-
Vcc+
0.3
V
Input Low Voltage
VIL
-
-0.3
-
0.4
-0.3
-
0.8
V
Output High Voltage
Level
VOH
IOH=-100uA
Vcc-0.1
-
-
-
-
-
V
IOH=-400uA
-
-
-
2.4
-
-
V
Output Low Voltage Level
VOL
IOL=100uA
-
-
0.1
-
-
-
V
IOL=2.1mA
-
-
-
-
-
0.4
V
VOL=0.1V
3
4
-
-
-
-
mA
VOL=0.4V
-
-
-
8
10
-
mA
Operating
Current
Output Low Current
(RB#)
IOL
(RB#)
Table 9: DC and Operating Characteristics
Value
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (1.7V - 1.95Volt & 2.7V - 3.6V)
Output Load (3.0V - 3.6V)
1.8Volt
3.3Volt
0V to Vcc
0.4V to 2.4V
5ns
5ns
Vcc / 2
1.5V
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
-
1 TTL GATE and CL=100pF
Table 10: AC Conditions
NOTE:
1. These parameters are applied to the errata.
Rev 0.7 / Apr. 2005
19
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Item
Symbol
Test Condition
Min
Max
Unit
Input / Output Capacitance (1)
CI/O
VIL=0V
-
10
pF
Input Capacitance(1)
CIN
VIN=0V
-
10
pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Note: 1. For the stacked devices version the Input Capacitance is <TBD> and the I/O capacitance is <TBD>
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
300
700
us
Dummy Busy Time for Cache Program
tCBSY
-
3
700
us
Main Array
NOP
-
-
4
Cycles
Spare Array
NOP
-
-
4
Cycles
tBERS
-
2
3
ms
Number of partial Program Cycles in the same page
Block Erase Time
Table 12: Program / Erase Characteristics
Rev 0.7 / Apr. 2005
20
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
Symbol
1.8Volt
Min
Max
3.3Volt
Min
Max
Unit
CLE Setup time
tCLS
5(2)
5(2)
ns
CLE Hold time
tCLH
15(2)
15(2)
ns
CE# setup time
tCS
0
0
ns
CE# hold time
tCH
10
10
ns
WE# pulse width
tWP
40(2)
40(2)
ns
ALE setup time
tALS
5(2)
5(2)
ns
ALE hold time
tALH
15(2)
15(2)
ns
Data setup time
tDS
25(2)
25(2)
ns
Data hold time
tDH
15
15
ns
Write Cycle time
tWC
60(2)
60(2)
ns
WE# High hold time
tWH
20
20
ns
ALE to Data Loading time
tADL
100
100
ns
Data Transfer from Cell to register
tR
27(2)
27(2)
us
ALE to RE# Delay (ID Read)
tAR
10
10
ns
CLE to RE# Delay
tCLR
10
10
ns
Ready to RE# Low
tRR
20
20
ns
RE# Pulse Width
tRP
25(2)
25(2)
ns
WE# High to Busy
tWB
Read Cycle Time
tRC
RE# Access Time
tREA
30
30
ns
RE# High to Output High Z
tRHZ
30
30
ns
CE# High to Output High Z
tCHZ
20
20
ns
RE or CE High to Output hold
tOH
RE# High Hold Time
tREH
Output High Z to RE# low
tIR
CE# Access Time
tCEA
WE# High to RE# low
tWHR
Device Resetting Time
(Read / Program / Erase)
tRST
100
60(2)
100
60(2)
15
ns
15
(2)
ns
ns
(2)
30
30
ns
0
0
ns
45
60
45
60
5/10/500(1)
ns
ns
5/10/500(1)
us
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. These parameters are applied to the errata.
3. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Rev 0.7 / Apr. 2005
21
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
IO
Pagae
Program
Block
Erase
Cache
Program
Read
Cache
Read
0
Pass / Fail
Pass / Fail
Pass / Fail (N)
NA
Pass: ‘0’ Fail: ‘1’
1
NA
NA
Pass / Fail (N-1)
NA
Pass: ‘0’ Fail: ‘1’
(Only for Cache Program,
else Don’t care)
2
NA
NA
NA
NA
-
3
NA
NA
NA
NA
-
4
NA
NA
NA
NA
-
5
Ready/Busy
Ready/Busy
P/E/R
Controller Bit
Ready/Busy
P/E/R
Controller Bit
Active: ‘0’ Idle: ‘1’
6
Ready/Busy
Ready/Busy
Cache Register
Free
Ready/Busy
Ready/Busy
Busy: ‘0’ Ready’: ‘1’
7
Write Protect
Write Protect
Write Protect
Write Protect
CODING
Protected: ‘0’ Not
Protected: ‘1’
Table 14: Status Register Coding
DEVICE IDENTIFIER BYTE
DESCRIPTION
1st
Manufacturer Code
2nd
Device Identifier
3rd
Don't care
4th
Page Size, Block Size, Spare Size, Organization
Table 15: Device Identifier Coding
Rev 0.7 / Apr. 2005
22
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Description
Page Size
(Without Spare Area)
Spare Area Size
(Byte / 512Byte)
Serial Access Time
Block Size
(Without Spare Area)
Organization
IO7
IO6
IO5-4
IO3
IO2
1K
2K
Reserved
Reserved
IO1-0
0
0
1
1
8
16
0
1
0
1
0
1
Standard (50ns)
Fast
(30ns)
0
1
64K
128K
256K
Reserved
0
0
1
1
X8
X16
0
1
0
1
0
1
Not Used
Reserved
Table 16: 4th Byte of Device Identifier Description
Part Number
Voltage
Bus Width
Manufacture
Code
Device
Code
3rd Code
4th Code
HY27UF081G2M
3.3V
x8
ADh
F1h
Don’t care
15h
HY27UF161G2M
3.3V
x16
ADh
C1h
Don’t care
55h
HY27SF081G2M
1.8V
x8
ADh
A1h
Don’t care
15h
HY27SF161G2M
1.8V
x16
ADh
ADh
Don’t care
55h
Table 17: Read ID
Rev 0.7 / Apr. 2005
23
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
&/(
W&/6
W&/+
W&6
W&+
&(
W:3
:(
W$/6
W$/+
$/(
W'6
,2a
W'+
&RPPDQG
Figure 7: Command Latch Cycle
W&/6
&/(
W&6
W:&
W:&
W:&
&(
W:3
W:3
:(
W$/6
W:+
W$/+ W$/+
W:3
W:+
W$/+ W$/+
W:3
W:+
W$/+ W$/+
W$/+
$/(
,2[
W'+
W'6 W'+
W'6
&RO$GG
&RO$GG
W'6 W'+
W'6 W'+
5RZ$GG
5RZ$GG
Figure 8: Address Latch Cycle
Rev 0.7 / Apr. 2005
24
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
W&/+
&/(
W&+
&(
W$/6
W:&
$/(
W:3
W:3
:(
W:3
W:+
W:+
W'6
,2[
W'+
W'6
',1
W'+
W'6
',1
W'+
',1ILQDO
Figure 9. Input Data Latch Cycle
W&($
&(
W5($
W5(+
W53
W&+=
W5($
W5($
W2+
5(
W5+=
W5+=
W2+
,2[
'RXW
W55
'RXW
'RXW
W5&
5%
127(67UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG
Figure 10: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L)
Rev 0.7 / Apr. 2005
25
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
W&/5
&/(
W&/6
W&/+
W&6
&(
W&+
W:3
:(
W&($
W&+=
W:+5
5(
W'6
,2[
W'+
W,5
W5($
W5+=
6WDWXV2XWSXW
K
Figure 11: Status Read Cycle
W&/5
&/(
&(
W:&
:(
W:%
W$5
$/(
W5
W5&
5(
W2+
W55
,2[
K
&RO$GG
&RO$GG 5RZ$GG 5RZ$GG
&ROXPQ$GGUHVV
5'
K
W5+=
'RXW1
'RXW1
'RXW0
5RZ$GGUHVV
%XV\
Figure 12: Read1 Operation (Read One Page)
Rev 0.7 / Apr. 2005
26
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
W&/5
&/(
&(
W:&
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Figure 13: Read1 Operation intercepted by CE#
Rev 0.7 / Apr. 2005
27
Rev 0.7 / Apr. 2005
5%
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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 14 : Random Data output
28
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
&/(
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Figure 15: Page Program Operation
Rev 0.7 / Apr. 2005
29
Rev 0.7 / Apr. 2005
5%
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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 16 : Random Data In
30
Rev 0.7 / Apr. 2005
K
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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 17 : Copy Back Program
31
Rev 0.7 / Apr. 2005
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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 18 : Cache Program
32
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure 19: Block Erase Operation (Erase One Block)
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Figure 20: Read ID Operation
Rev 0.7 / Apr. 2005
33
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure 22: exit from cache read in 5ms when device internally is reading
Rev 0.7 / Apr. 2005
34
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
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Figure 24: Read Operation with CE don’t-care.
Rev 0.7 / Apr. 2005
35
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
9
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Figure 25: Automatic Read at Power On
:(
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Rev 0.7 / Apr. 2005
36
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
9FF
97+
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Figure 27: Power On and Data Protection Timing
* See the Application Note.1
Rev 0.7 / Apr. 2005
37
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure 28: Ready/Busy Pin electrical specifications
Rev 0.7 / Apr. 2005
38
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure 29: page programming within a block
Rev 0.7 / Apr. 2005
39
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of
the 1st or 2nd page(if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 29. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give
errors in the Status Register.
As the failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation
Recommended Procedure
Erase
Block Replacement
Program
Block Replacement or ECC
Read
ECC
Table 18: Block Failure
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Figure 30: Bad Block Management Flowchart
Rev 0.7 / Apr. 2005
40
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Automatic Page0 Read after Power Up
The timing diagram related to this operation is shown in Fig. 24
Due to this functionality the CPU can directly download the boot loader from the first page of the NAND flash, storing
it inside the internal cache and starting the execution after the download completed.
5.2 Addressing for program operation
Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB
(most significant bit) page of the block. Random address programming is prohibited. See Fig. 28.
Rev 0.7 / Apr. 2005
41
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
H
'
$
$
%
$
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/
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(
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Figure 31. 48-pin TSOP1, 12 x 20mm, Package Outline
Symbol
millimeters
Min
Typ
A
Max
1.200
A1
0.050
0.150
A2
0.980
1.030
B
0.170
0.250
C
0.100
0.200
CP
0.050
D
11.910
12.000
12.120
E
19.900
20.000
20.100
E1
18.300
18.400
18.500
e
0.500
L
0.500
0.680
alpha
0
5
Table 19: 48-TSOP1, 12 x 20mm, Package Mechanical Data
Rev 0.7 / Apr. 2005
42
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
$QJOH DOSKD
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Figure 32. 48-pin WSOP1, 12 x 17mm, Package Outline
Symbol
millimeters
Min
Typ
A
Max
0.700
A1
0
0.080
A2
0.540
0.620
B
0.130
0.230
C
0.065
0.175
CP
0.050
D
11.910
12.000
E
16.900
17.000
17.100
E1
15.300
15.400
15.500
e
12.120
0.500
L
0.450
0.750
alpha
0
8
Table 20: 48-WSOP1, 12 x 17mm, Package Mechanical Data
Rev 0.7 / Apr. 2005
43
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure 33. 63-ball FBGA - 9.5 x 12, 6 x 8 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Symbol
A
A1
A2
b
D
D1
D2
E
E1
E2
e
FD
FD1
FE
FE1
SD
SE
Millimeters
Min
0.80
0.25
0.55
0.40
9.40
11.90
Typ
0.90
0.30
0.60
0.45
9.50
4.00
7.20
12.00
5.60
8.80
0.80
2.75
1.15
3.20
1.60
0.40
0.40
Max
1.00
0.35
0.65
0.50
9.60
12.10
Table 21: 63-ball FBGA - 9.5 x 12, 6 x 8 ball array 0.8mm pitch, Pakage Mechanical Data
Rev 0.7 / Apr. 2005
44
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
MARKING INFORMATION
P a ck a g
TSOP1
/
W SO P
M a rk in g E x a m p le
H
Y
2
7
x
x
x
x
x
F
- h y n ix
: H yn ix S ym b o l
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- H Y27xFxx1G 2M xxxx
: P art N u m b er
x
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R
x
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Y
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x
x
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2 7 : N A N D Fla sh
x : P ow er S u pp ly
: U (2 .7V ~ 3 .6 V ), L(2 .7V ), S(1.8V )
F : C la ssifica tion
: S in gle Level C ell+ S in g le D ie+ Larg e B lock
x x : B it O rg an izatio n
: 0 8(x8 ), 1 6(x1 6)
1 G : D en sity
: 1 G b it
2: M ode
: 1 n C E & 1R /n B ; S equ en tia l R o w R ea d D isa b le
M : V ersio n
: 1 st G en era tion
x : P a cka g e T ype
: T (48-T S O P 1 ), V (4 8 -W S O P )
x : P a cka g e M a teria l
: B la n k(N o rm a l), P (L e ad F re e )
x : O p eratin g T em p erature
: C (0℃ ~ 7 0 ℃ ), E (-2 5 ℃ ~ 8 5 ℃ )
M (-3 0℃ ~ 8 5 ℃ ), I(-4 0 ℃ ~ 8 5 ℃ )
x : B ad B lock
: B (In clu ded B a d B lo ck), S (1 ~ 5 B a d B lo ck),
P (A ll G o o d B lo ck)
- Y : Y ear (ex: 5 = yea r 2 0 0 5, 0 6= yea r 2 0 06 )
- w w : W ork W eek (ex: 12 = w o rk w eek 1 2 )
- x x : P ro cess C o d e
N o te
- C a p ita l L e tte r
: Fixed Item
- S m a ll L e tte r
: N o n -fixed Item
Rev 0.7 / Apr. 2005
45
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
MARKING INFORMATION
P a ck a g
FBGA
M a rk in g E x a m p le
H
Y
2
7
x
x
x
x
x
F
- h yn ix
: H ynix Sym bol
- KOR
- H Y27xFxx1G2M xxxx
: O rigin C ountry
: Part N um ber
x
K
O
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x
1
G
2
M
Y
W
W
x
x
H Y : H Y N IX
2 7 : N A N D Flash
x: Pow er Supply
: U (2.7V ~ 3.6V), L(2.7V ), S(1.8V)
F : C lassification
: Single Level C ell+ Single D ie+ Large B lock
x x: B it O rganization
: 08(x8), 16(x16)
1 G : D ensity
: 1G bit
2 : M ode
: 1nC E & 1R /nB ; Sequential R ow R ead D isable)
M : V ersion
: 1st G eneration
x : Package Type
: F(63 FB G A )
x : Package M aterial
: B lank(N orm al), P(Lead Free)
x : O perating T em perature
: C (0℃ ~ 70℃ ), E (-25℃ ~ 85℃ )
M (-30℃ ~ 85℃ ), I(-40℃ ~ 85℃ )
x : B ad B lock
: B (Included B ad B lock), S (1~ 5 B ad B lock),
P(A ll G ood B lock)
- Y : Y ear (ex: 5= year 2005, 06= year 2006)
- w w : W ork W eek (ex: 12= w ork w eek 12)
- x x : Process C ode
N o te
- C a p ita l L e tte r
: Fixed Item
- S m a ll L e tte r
: N on-fixed Item
Rev 0.7 / Apr. 2005
46
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Application Note
1. Power-on/off Sequence
After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific
level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on progress. While
the device is initializing, the device sets internal registeries to default value and generates internal biases to operate
circuits. Typically the initializing time of 20us is required.
Power-off or power failure before write/erase operation is complete will cause a loss of data. The WP# signal helps
user to protect not only the data integrity but also device circuitry from being damaged at power-on/off by keeping
WP# at VIL during power-on/off.
For the device to operate stably, it is highly recommended to operate the device as shown Fig.33.
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9'HYLFH9
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5HDG\
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Figure 34: Power-on/off sequence
Rev 0.7 / Apr. 2005
47
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
2. Automatic sleep mode for low power consumption
The device provides the automatic sleep function for low power consumption.
The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command
input, and exits simply by lowering CE# to VIL level.
Typically, consecutive operation is executable right after deactivating the automatic sleep mode, while tCS of 2us is
required prior to following operation as shown in Fig.34.
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Figure 35: tCS setting when deactivating the auto sleep mode
Rev 0.7 / Apr. 2005
48