19-2285; Rev 0; 1/02 Quad Differential LVECL-to-LVPECL Translators The MAX9420–MAX9423 are specified for operation from -40°C to +85°C, and are offered in space-saving 32-pin 5mm ✕ 5mm TQFP and 32-lead 5mm ✕ 5mm QFN packages. Applications Features ♦ >500mV Differential Output at 3.0GHz Clock ♦ 336ps (typ) Propagation Delay in Asynchronous Mode ♦ 17ps (typ) Channel-to-Channel Skew ♦ Integrated 50Ω Outputs (MAX9421/MAX9423) ♦ Integrated 100Ω Inputs (MAX9422/MAX9423) ♦ Synchronous/Asynchronous Operation Ordering Information TEMP RANGE PART MAX9420EHJ PINDATA OUTPUT PACKAGE INPUT -40°C to +85°C 32 TQFP MAX9420EGJ* -40°C to +85°C 32 QFN MAX9421EHJ -40°C to +85°C 32 TQFP MAX9421EGJ* -40°C to +85°C 32 QFN MAX9422EHJ -40°C to +85°C 32 TQFP MAX9422EGJ* -40°C to +85°C 32 QFN MAX9423EHJ -40°C to +85°C 32 TQFP MAX9423EGJ* -40°C to +85°C 32 QFN Open Open Open Open Open 50Ω Open 50Ω 100Ω Open 100Ω Open 100Ω 50Ω 100Ω 50Ω *Future product—contact factory for availability. Data and Clock Driver and Buffer Central Office Backplane Clock Distribution Pin Configurations OUT0 OUT0 GND IN1 IN1 32 31 30 29 28 27 26 25 VEE 1 24 VCC SEL 2 23 OUT1 SEL 3 22 OUT1 CLK 4 CLK 5 EN 6 EN 7 18 OUT2 VEE 8 17 VCC 21 GND MAX9420 MAX9421 MAX9422 MAX9423 11 12 13 14 15 16 OUT3 GND IN2 IN2 IN3 19 OUT2 VCC 10 9 20 GND OUT3 Functional Diagram appears at end of data sheet. VCC ATE IN0 TOP VIEW IN3 Base Station IN0 DSLAM Backplane TQFP (5mm x 5mm) Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9420–MAX9423 General Description The MAX9420–MAX9423 are extremely fast, low-skew quad LVECL-to-LVPECL translators designed for highspeed signal and clock driver applications. The devices feature ultra-low propagation delay of 336ps and channel-to-channel skew of 17ps. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. These devices operate with a negative supply voltage of -2.0V to -3.6V, compatible with LVECL input signals. The positive supply range is 2.375V to 3.6V for differential LVPECL output signals. A variety of input and output terminations are offered for maximum design flexibility. The MAX9420 has open inputs and open-emitter outputs. The MAX9421 has open inputs and 50Ω series outputs. The MAX9422 has 100Ω differential input impedance and open-emitter outputs. The MAX9423 has 100Ω differential input impedance and 50Ω series outputs. MAX9420–MAX9423 Quad Differential LVECL-to-LVPECL Translators ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.1V VEE to GND............................................................-4.1V to +0.3V Inputs to GND .............................................(VEE - 0.3V) to +0.3V Differential Input Voltage .......................................................±3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70°C) Single-Layer PC Board 32-Pin 5mm ✕ 5mm TQFP (derate 9.5mW/°C above +70°C) ................................761mW 32-Lead 5mm ✕ 5mm QFN (derate 21.3mW/°C above +70°C) .................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm ✕ 5mm TQFP......................................+105°C/W 32-Lead 5mm ✕ 5mm QFN ......................................+47°C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 32-Pin 5mm ✕ 5mm TQFP.........................................+73°C/W Junction-to-Case Thermal Resistance 32-Pin 5mm ✕ 5mm TQFP.........................................+25°C/W 32-Lead 5mm ✕ 5mm QFN .........................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (IN_, IN_) ........................................500V Others.............................................................................1.2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω ±1% to VCC - 2.0V. Typical values are at VEE = -3.3V, VCC = 3.3V, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVECL INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage VIHD Figure 1 VEE + 1.4 0 V Differential Input Low Voltage VILD Figure 1 VEE -0.2 V Differential Input Voltage VID Figure 1 Input Current Differential Input Resistance (IN, IN) IIH, IIL RIN VEE ≤ -3.0V 0.2 3.0 VEE > -3.0V 0.2 VEE MAX9420/ MAX9421 EN, EN, SEL, SEL , IN_, IN_, CLK, or CLK = VIHD or VILD -10 25 MAX9422/ MAX9423 EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD -10 25 V µA MAX9422/MAX9423 86 100 114 Ω 660 mV LVPECL OUTPUTS (OUT_, OUT_) 2 Differential Output Voltage VOH VOL Figure 1 600 Output Common-Mode Voltage VOCM Figure 1 VCC 1.5 VCC 1.25 VCC 1.1 V Internal Current Source ISINK MAX9421/MAX9423, Figure 2 6.5 8.2 10.0 mA Output Impedance ROUT MAX9421/MAX9423, Figure 2 40 50 60 Ω _______________________________________________________________________________________ Quad Differential LVECL-to-LVPECL Translators (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω ±1% to VCC - 2.0V. Typical values are at VEE = -3.3V, VCC = 3.3V, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS mA POWER SUPPLY Negative Supply Current IEE OUT_, OUT_ open MAX9421/MAX9422/ MAX9423 7 10 Positive Supply Current ICC OUT_, OUT_ open MAX9421/MAX9423 153 -180 MAX9420/MAX9422 87 105 mA AC ELECTRICAL CHARACTERISTICS (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, outputs terminated with 50Ω ±1% to VCC - 2.0V. For SEL = high, CLK = high or low, fIN = 2.0GHz. For SEL = low, FIN = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.4V to 0, VILD = VEE to -0.2V, VIHD - VILD = 0.2V to the smaller of 3.0V or |VEE|. Typical values are at VEE = -3.3V, VCC = 3.3V, GND = 0, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Note 4) MIN TYP MAX UNITS IN-to-OUT Differential PARAMETER tPLH1, tPHL1 SEL = high, Figure 3 SYMBOL CONDITIONS 250 336 450 ps CLK-to-OUT Differential tPLH2, tPHL2 SEL = low, Figure 4 350 506 575 ps IN-to-OUT Channel-to-Channel Skew (Note 5) tSKD1 SEL = high 17 60 ps CLK-to-OUT Channel-toChannel Skew (Note 5) tSKD2 SEL = low 17 55 ps Maximum Clock Frequency fCLK(MAX) VOH - VOL ≥ 500mV, SEL = low 3.0 GHz Maximum Data Frequency fIN(MAX) VOH - VOL ≥ 400mV, SEL = high 2 GHz Added Random Jitter (Note 6) Added Deterministic Jitter (Note 6) tRJ SEL = low, fCLK = 3.0GHz, fIN = 1.5GHz 0.65 1.0 ps(RMS) SEL = high, fIN = 2GHz 0.53 1.0 ps(RMS) 28 45 SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps, 223 - 1 PRBS pattern tDJ ps(P-P) SEL = high, IN_ = 3.0Gbps 223 - 1 PRBS pattern 23 IN-to-CLK Setup Time tS Figure 4 80 CLK-to-IN Hold Time tH Figure 4 80 Output Rise Time tR Figure 3 45 ps ps 90 120 ps _______________________________________________________________________________________ 3 MAX9420–MAX9423 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, outputs terminated with 50Ω ±1% to VCC - 2.0V. For SEL = high, CLK = high or low, fIN = 2.0GHz. For SEL = low, FIN = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.4V to 0, VILD = VEE to -0.2V, VIHD - VILD = 0.2V to the smaller of 3.0V or |VEE|. Typical values are at VEE = -3.3V, VCC = 3.3V, GND = 0, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Note 4) PARAMETER SYMBOL Output Fall Time tF CONDITIONS MIN Figure 3 ∆tPD/ ∆T Propagation Delay Temperature Coefficient TYP MAX UNITS 90 120 ps 0.2 1 ps/°C Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 6: Device jitter added to the input signal. Typical Operating Characteristics (VEE = -3.3V, VCC = 3.3V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω ±1% to VCC - 2.0V, SEL = high, fCLK = 3.0GHz, fIN = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = -0.9V, VILD = -1.7V, TA = +25°C, unless otherwise noted.) 80 7 6 70 35 60 85 -40 -15 MAX9420/MAX9422 SEL = HIGH tR 90 tF 85 80 -15 10 35 TEMPERATURE (°C) 4 60 85 1000 1500 2000 2500 3000 3500 CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE 350 340 tPLH1 330 tPHL1 320 310 600 MAX9420/MAX9422 SEL = LOW 575 550 525 tPLH2 500 tPHL2 475 450 290 -40 500 IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE 300 75 0 85 IN_ FREQUENCY (MHz) MAX9420/MAX9422 SEL = HIGH 360 PROPAGATION DELAY (ps) 95 60 370 MAX9420 toc04 100 35 TEMPERATURE (°C) TEMPERATURE (°C) OUTPUT RISE/FALL TIME vs. TEMPERATURE 10 PROPAGATION DELAY (ps) 10 MAX9420 toc05 -15 400 0 4 -40 600 200 5 75 800 MAX9420 toc06 85 MAX9420/MAX9422 SEL = HIGH OUTPUT AMPLITUDE (mV) 90 MAX9420/MAX9422 SEL = HIGH OUTPUTS NOT TERMINATED 8 1000 MAX9420 toc02 MAX9420/MAX9422 SEL = HIGH OUTPUTS NOT TERMINATED OUTPUT AMPLITUDE (mV) SUPPLY CURRENT (mA) 9 MAX9420 toc01 100 95 OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY SUPPLY CURRENT (IEE) vs. TEMPERATURE MAX9420 toc03 SUPPLY CURRENT (ICC) vs. TEMPERATURE OUTPUT RISE/FALL TIME (ps) MAX9420–MAX9423 Quad Differential LVECL-to-LVPECL Translators 425 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Quad Differential LVECL-to-LVPECL Translators PIN NAME FUNCTION 1, 8 VEE Negative Supply Voltage. Bypass VEE to GND with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 SEL Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronous mode. 3 SEL Inverting Differential Select Input 4 CLK Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = differential low. 5 CLK Noninverting Differential Clock Input 6 EN Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) drives the output low. 7 EN Inverting Differential Output Enable Input 9 IN3 Noninverting Differential Input 3 10 IN3 Inverting Differential Input 3 11, 17, 24, 30 VCC Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 12 OUT3 Inverting Differential Output 3 13 OUT3 Noninverting Differential Output 3 14, 20, 21, 27 GND Ground 15 IN2 Noninverting Differential Input 2 16 IN2 Inverting Differential Input 2 18 OUT2 Inverting Differential Output 2 19 OUT2 Noninverting Differential Output 2 22 OUT1 Noninverting Differential Output 1 23 OUT1 Inverting Differential Output 1 25 IN1 Inverting Differential Input 1 26 IN1 Noninverting Differential Input 1 28 OUT0 Noninverting Differential Output 0 29 OUT0 Inverting Differential Output 0 31 IN0 Inverting Differential Input 0 32 IN0 Noninverting Differential Input 0 — EP Exposed Paddle (MAX942_EGJ only). Connected to VEE internally. See package dimensions. _______________________________________________________________________________________ 5 MAX9420–MAX9423 Pin Description MAX9420–MAX9423 Quad Differential LVECL-to-LVPECL Translators Detailed Description The MAX9420–MAX9423 are extremely fast, low-skew quad LVECL-to-LVPECL translators designed for highspeed signal and clock driver applications. The devices feature ultra-low propagation delay of 336ps and channel-to-channel skew of 17ps. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. These devices operate with a negative supply voltage of -2.0V to -3.6V, compatible with LVECL input signals. The positive supply range is 2.375V to 3.6V for differential LVPECL output signals. A variety of input and output terminations are offered for maximum design flexibility. The MAX9420 has open inputs and open-emitter outputs. The MAX9421 has open inputs and 50Ω series outputs. The MAX9422 has 100Ω differential input impedance and open-emitter outputs. The MAX9423 has 100Ω differential input impedance and 50Ω series outputs. Supply Voltages For interfacing to differential LVECL input levels, the VEE range is -2.0V to -3.6V with GND = 0. The VCC range is from 2.375V to 3.6V, compatible with LVPECL logic. Output levels are referenced to VCC. Data Inputs The MAX9420/MAX9421 have open inputs and require external termination. The MAX9422/MAX9423 have integrated 100Ω differential input termination resistors from IN_ to IN_, reducing external component count. GND Outputs The MAX9421/MAX9423 have internal 50Ω series output termination resistors and 8mA internal pulldown current sources. Using integrated resistors reduces external component count. The MAX9420/MAX9422 have open-emitter outputs. An external termination is required. See the Output Termination section. Enable Setting EN = high and EN = low enables the device. Setting EN = low and EN = high forces the outputs to a differential low. All changes on CLK, SEL, and IN_ are ignored. Asynchronous Operation Setting SEL = high and SEL = low enables the four channels to operate independently as LVECL-toLVPECL translators. The CLK signal is ignored in this mode. In asynchronous mode, the CLK signal should be set to either logic low or high state to minimize noise coupling. Synchronous Operation Setting SEL = low and SEL = high enables all four channels to operate in synchronized mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on the rising edge of the differential clock input (CLK and CLK). Differential Signal Input Limit The maximum signal magnitude of all the differential inputs is 3.0V. VIHD (MAX) VID VCC VID = 0 VOH VILD (MAX) VOH - VOL VOCM VIHD (MIN) VID VOL VID = 0 VEE GND VILD (MIN) INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION Figure 1. Input and Output Voltage Definitions 6 _______________________________________________________________________________________ Quad Differential LVECL-to-LVPECL Translators MAX9420–MAX9423 IN_ IN_ 100kΩ IN_ IN_ MAX9420/MAX9421 MAX9422/MAX9423 VCC VCC ROUT OUT_ OUT_ ROUT OUT_ OUT_ ISINK ISINK MAX9420/MAX9422 VEE MAX9421/MAX9423 Figure 2. Input and Output Configurations IN_ VIHD - VILD IN_ tPLH1 tPHL1 OUT_ VOH - VOL OUT_ 80% OUT_ - OUT_ DIFFERENTIAL OUTPUT WAVEFORM VOH - VOL 80% VOH - VOL 20% tR 20% tF SEL = HIGH EN = HIGH Figure 3. IN-to-OUT Propagation Delay Timing Diagram _______________________________________________________________________________________ 7 MAX9420–MAX9423 Quad Differential LVECL-to-LVPECL Translators CLK VIHD - VILD CLK tH tS tH IN_ VIHD - VILD IN_ tPLH2 tPHL2 OUT_ VOH - VOL OUT_ SEL = LOW EN = HIGH Figure 4. CLK-to-OUT Propagation Delay Timing Diagram Applications Information ple parallel vias for ground-plane connection to minimize inductance. Input Bias Unused inputs should be biased or driven as shown in Figure 5. This avoids noise coupling that might cause toggling at the unused outputs. Output Termination Terminate open-emitter outputs (MAX9420/MAX9422) through 50Ω to VCC - 2V or use an equivalent Thevenin termination. Terminate outputs using identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed. Power-Supply Bypassing Circuit Board Traces Input and output trace characteristics affect the performance of the MAX9420–MAX9423. Connect each of the inputs and outputs to a 50Ω characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce the reflections by maintaining 50Ω characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. Chip Information TRANSISTOR COUNT: 927 PROCESS: Bipolar Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to GND and VEE to GND with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device pins. Use multi- 8 _______________________________________________________________________________________ Quad Differential LVECL-to-LVPECL Translators MAX9420–MAX9423 VCC VCC GND IN_ IN_ OUT_ OUT_ 100Ω 100Ω OUT_ IN_ OUT_ IN_ 1kΩ MAX9420 MAX9421 1/4 1kΩ 1/4 MAX9422 MAX9423 VEE VEE Figure 5. Input Bias Circuits for Unused Inputs IN1 GND OUT0 IN1 25 26 27 28 IN0 VCC 29 30 32 * 31 IN0 TOP VIEW OUT0 Pin Configurations (continued) * VEE 1 24 VCC SEL 2 23 OUT1 SEL 3 22 OUT1 CLK 4 21 GND CLK 5 20 GND EN 6 19 OUT2 EN 7 18 OUT2 8 17 VCC 12 13 14 15 16 OUT3 GND IN2 IN2 11 VCC OUT3 9 10 IN3 * IN3 VEE MAX9420 MAX9421 MAX9422 MAX9423 * QFN-EP* *EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE LEAD UNDER PACKAGE. _______________________________________________________________________________________ 9 Quad Differential LVECL-to-LVPECL Translators MAX9420–MAX9423 Functional Diagram IN0 IN0 1 D Q D Q 0 OUT0 OUT0 CK CK IN1 IN1 1 D Q D Q 0 OUT1 OUT1 CK CK IN2 IN2 1 D Q D Q 0 OUT2 OUT2 CK CK IN3 IN3 1 D Q D Q 0 OUT3 OUT3 CK CK CLK CLK SEL SEL EN EN 10 ______________________________________________________________________________________ Quad Differential LVECL-to-LVPECL Translators 32L TQFP, 5x5x01.0.EPS ______________________________________________________________________________________ 11 MAX9420–MAX9423 Package Information Quad Differential LVECL-to-LVPECL Translators MAX9420–MAX9423 Package Information (continued) 12 ______________________________________________________________________________________ Quad Differential LVECL-to-LVPECL Translators Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9420–MAX9423 Package Information (continued)