SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE (TOP VIEW) 2 13 2CLR 3 12 2D 4 11 2CLK 5 6 10 2PRE 9 2Q 7 8 1CLK NC 1PRE NC 1Q 4 3 2 1 20 19 18 5 17 6 16 7 8 15 14 9 10 11 12 13 1Q GND NC 13 VCC 14 2 2Q 1 1CLR 1CLR 1D 1CLK 1PRE 1Q 1Q GND SN74LVC74A . . . RGY PACKAGE (TOP VIEW) 2CLR SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) • GND • Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2D NC 2CLK NC 2PRE 2Q 2Q Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C 1CLR NC VCC FEATURES • • • • NC - No internal connection DESCRIPTION/ORDERING INFORMATION The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. ORDERING INFORMATION PACKAGE (1) TA QFN – RGY Tube of 50 SN74LVC74AD Reel of 2500 SN74LVC74ADR Reel of 250 SN74LVC74ADT SOP – NS Reel of 2000 SN74LVC74ANSR LCV74A SSOP – DB Reel of 2000 SN74LVC74ADBR LC74A Tube of 90 SN74LVC74APW Reel of 2000 SN74LVC74APWR TSSOP – PW –55°C to 125°C (1) TOP-SIDE MARKING SN74LVC74ARGYR SOIC – D –40°C to 85°C ORDERABLE PART NUMBER Reel of 1000 LC74A LVC74A LC74A Reel of 250 SN74LVC74APWT CDIP – J Tube of 25 SNJ54LVC74AJ SNJ54LVC74AJ CFP – W Tube of 150 SNJ54LVC74AW SNJ54LVC74AW LCCC – FK Tube of 55 SNJ54LVC74AFK SNJ54LVC74AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1993–2005, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment. FUNCTION TABLE INPUTS (1) OUTPUTS PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H (1) H (1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance Tstg (1) (2) (3) (4) (5) D package (4) 86 DB package (4) 96 NS package (4) 76 PW package (4) 113 RGY package (5) 47 Storage temperature range –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. Recommended Operating Conditions (1) SN54LVC74A VCC Supply voltage Operating Data retention only MAX MIN MAX 2 3.6 1.65 3.6 1.5 High-level input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V UNIT 1.5 VCC = 1.65 V to 1.95 V VIH SN74LVC74A MIN 1.7 2 V 2 VCC = 1.65 V to 1.95 V 0.35 × VCC VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2.7 V to 3.6 V 0.8 0.8 VCC = 1.65 V IOH High-level output current –4 VCC = 2.3 V –8 VCC = 2.7 V –12 –12 VCC = 3 V –24 –24 VCC = 1.65 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 12 VCC = 3 V 24 24 10 –55 125 –40 mA 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V (1) UNIT VCC – 0.2 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 V 1.65 V to 3.6 V IOL = 100 µA 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 0.4 IOL = 24 mA 3V 0.55 0.55 3.6 V ±5 ±5 µA 3.6 V 10 10 µA 2.7 V to 3.6 V 500 500 µA II VI = 5.5 V or GND ICC VI = VCC or GND, Ci MAX VCC – 0.2 1.65 V IOH = –24 mA ∆ICC SN74LVC74A MIN TYP (1) MAX IOH = –4 mA IOH = –12 mA VOL MIN TYP (1) 1.65 V to 3.6 V IOH = –100 µA VOH SN54LVC74A VCC IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND 3.3 V 5 5 V pF All typical values are at VCC = 3.3 V, TA = 25°C. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC74A fclock VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX Clock frequency tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ 4 VCC = 2.7 V 83 100 PRE or CLR low 3.3 3.3 CLK high or low 3.3 3.3 Data 3.4 3 PRE or CLR inactive 2.2 2 1 1 UNIT MHz ns ns ns SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC74A VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency MAX VCC = 2.5 V ± 0.2 V MIN MAX 83 tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX 83 MIN 83 UNIT MAX 150 PRE or CLR low 4.1 3.3 3.3 3.3 CLK high or low 4.1 3.3 3.3 3.3 Data 3.6 2.3 3.4 3 PRE or CLR inactive 2.7 1.9 2.2 2 1 1 1 0 MHz ns ns ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC74A FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN fmax MAX 83 CLK tpd MAX 100 Q or Q PRE or CLR MIN UNIT MHz 6 1 5.2 6.4 1 5.4 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC74A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax tpd MAX 83 CLK PRE or CLR Q or Q VCC = 2.5 V ± 0.2 V MIN MAX 83 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX 83 MIN UNIT MAX 150 MHz 1 7.1 1 4.4 1 6 1 5.2 1 6.9 1 4.6 1 6.4 1 5.4 tsk(o) 1 ns ns Operating Characteristics TA = 25°C Cpd PARAMETER TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP Power dissipation capacitance per flip-flop f = 10 MHz 24 24 26 UNIT pF 5 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD 5962-9761601QCA ACTIVE CDIP J 14 1 TBD 5962-9761601QDA ACTIVE CFP W 14 1 TBD 5962-9761601V2A ACTIVE LCCC FK 20 1 TBD 5962-9761601VCA ACTIVE CDIP J 14 1 TBD 5962-9761601VDA ACTIVE CFP W 14 1 SN74LVC74AD ACTIVE SOIC D 14 50 SN74LVC74ADBLE OBSOLETE SSOP DB 14 SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWLE OBSOLETE TSSOP PW 14 SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type TBD A42 N / A for Pkg Type Green (RoHS & no Sb/Br) CU NIPDAU TBD TBD Addendum-Page 1 POST-PLATE N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC74ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVC74ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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