Cypress CY62148EV30 4-mbit (512 k ã 8) static ram Datasheet

CY62148EV30 MoBL®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
❐ Wide voltage range: 2.20 V to 3.60 V
■
Temperature range:
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■
Pin compatible with CY62148DV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Industrial)
The CY62148EV30 is a high performance CMOS static RAM
organized as 512 K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 36-ball very fine-pitch ball grid array
(VFBGA), 32-pin thin small outline package (TSOP) II, and
32-pin small outline integrated circuit (SOIC) [1] packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
Logic Block Diagram
I/O0
IO0
INPUT BUFFER
I/O1
IO1
ROW DECODER
I/O2
IO2
SENSE AMPS
512K x 8
ARRAY
I/O3
IO3
I/O4
IO4
I/O5
IO5
I/O6
IO6
CE
I/O7
IO7
POWER
DOWN
A17
A18
A13
A14
OE
A15
COLUMN DECODER
WE
A16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Note
1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation
Document Number: 38-05576 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 4, 2012
CY62148EV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 38-05576 Rev. *O
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
Page 2 of 18
CY62148EV30 MoBL®
Pin Configuration
VFBGA, SOIC and TSOP II pinouts are as follows. [2, 3]
36-ball VFBGA pinout
32-pin SOIC/TSOP II pinout
Top View
Top View
A6
A8
A
A7
I/O0
B
I/O1
C
VSS
Vcc
D
VCC
Vss
E
I/O2
F
A0
A1
NC
A3
I/O4
A2
WE
A4
NC
A5
I/O5
I/O6
A18
A17
I/O7
OE
CE
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
32
31
30
29
2
3
4
5
6
28
27
26
25
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V)
Speed
(ns)
Operating ICC (mA)
f = 1 MHz
VFBGA
CY62148EV30LL TSOP II
SOIC
Min
Typ [4]
Max
Industrial /
Automotive-A
2.2
3.0
3.6
Industrial
2.2
3.0
3.6
f = fmax
Standby ISB2
(µA)
Typ [4]
Max
Typ [4]
Max
Typ [4] Max
45
2
2.5
15
20
1
7
55
2
2.5
15
20
1
7
Industrial
Notes
2. SOIC package is available only in 55 ns speed bin.
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05576 Rev. *O
Page 3 of 18
CY62148EV30 MoBL®
DC input voltage [5, 6] ...................–0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ............................................ 55 °C to +125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage to ground
potential .......................................–0.3 V to VCC(max) + 0.3 V
Product
Range
DC voltage applied to outputs
in High Z State [5, 6] ......................–0.3 V to VCC(max) + 0.3 V
CY62148EV30
Industrial /
Automotive-A
Ambient
VCC[7]
Temperature
–40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
-45 (Industrial /
Automotive-A)
Test Conditions
Min Typ [9]
VOH
VOL
Output high
voltage
VIL
Min Typ [9]
Unit
Max
IOH = –0.1 mA
2.0
–
–
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
2.4
–
–
V
Output low voltage IOL = 0.1 mA
IOL = 2.1 mA, VCC > 2.70 V
VIH
Max
-55 [8]
–
–
0.4
–
–
0.2
V
–
–
0.4
–
–
0.4
V
Input high voltage VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3 V 1.8
–
VCC + 0.3 V
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3 V 2.2
–
VCC + 0.3 V
V
Input low voltage VCC = 2.2 V to 2.7 V For VFBGA and
–0.3
TSOP II packages
–
0.6
–
–
–
V
–
–
–0.3
–
0.4 [10]
V
–
0.8
–
–
–
V
–
–
–
–0.3
–
0.6 [10]
For SOIC package
–
VCC = 2.7 V to 3.6 V For VFBGA and
–0.3
TSOP II packages
For SOIC package
IIX
Input leakage
current
GND < VI < VC
–1
–
+1
–1
–
+1
A
IOZ
Output leakage
current
GND < VO < VCC, Output disabled
–1
–
+1
–1
–
+1
A
ICC
VCC operating
supply current
f = fmax = 1/tRC
–
15
20
–
15
20
mA
–
2
2.5
–
2
2.5
–
1
7
–
1
7
A
–
1
7
–
1
7
A
f = 1 MHz
VCC = VCC(max),
IOUT = 0 mA,
CMOS levels
ISB1 [11]
Automatic CE
power down
current – CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (Address and Data Only),
ISB2 [11]
Automatic CE
power down
current – CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
f = 0 (OE and WE), VCC = 3.60 V
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
8. SOIC package is available only in 55 ns speed bin.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7 V to 3.6 V) and 0.6 V (for VCC range of 2.2 V to 2.7 V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only.
11. Chip Enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05576 Rev. *O
Page 4 of 18
CY62148EV30 MoBL®
Capacitance
Parameter [12]
Description
Input capacitance
CIN
Output capacitance
COUT
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
10
10
Unit
pF
pF
32-pin SOIC
Package
55
Unit
C/W
22
C/W
Thermal Resistance
Parameter [12]
JA
JC
36-ball VFBGA 32-pin TSOP II
Package
Package
Still air, soldered on a 3 × 4.5
72
75.13
inch, two-layer printed circuit
board
8.86
8.95
Description
Test Conditions
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
OUTPUT
VCC
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
OUTPUT
Parameters
R1
R2
RTH
VTH
90%
10%
GND
Rise Time = 1 V/ns
R2
RTH
2.50 V
16667
15385
8000
1.20
V
3.0 V
1103
1554
645
1.75
Unit



V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05576 Rev. *O
Page 5 of 18
CY62148EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR [14]
Description
VCC for data retention
Data retention current
Conditions
Industrial /
Automotive-A
VCC = 1.5 V,
Min
1.5
–
Typ [13]
–
0.8
Max
–
7
Unit
V
A
0
–
–
ns
45
55
–
–
–
–
ns
ns
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
tCDR[15]
tR[16]
Chip deselect to data
retention time
Operation recovery time
CY62148EV30LL-45
CY62148EV30LL-55
Data Retention Waveform
Figure 2. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
14. Chip Enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 38-05576 Rev. *O
Page 6 of 18
CY62148EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [17]
Description
-45 (Industrial /
Automotive-A)
-55 [18]
Unit
Min
Max
Min
Max
45
–
55
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE LOW to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
[19]
tLZOE
OE LOW to Low Z
5
–
5
–
ns
tHZOE
OE HIGH to High Z [19, 20]
–
18
–
20
ns
tLZCE
CE LOW to Low Z [19]
10
–
10
–
ns
–
18
–
20
ns
[19, 20]
tHZCE
CE HIGH to High Z
tPU
CE LOW to power up
0
–
0
–
ns
tPD
CE HIGH to power up
–
45
–
55
ns
tWC
Write cycle time
45
–
55
–
ns
Write Cycle
[21]
tSCE
CE LOW to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to High Z
[19, 20]
WE HIGH to Low Z
[19]
Notes
17. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 1 on page 5.
18. SOIC package is available only in 55 ns speed bin.
19. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
20. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
21. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 38-05576 Rev. *O
Page 7 of 18
CY62148EV30 MoBL®
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
DATA OUT
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
ICC
50%
50%
ISB
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 27
tHD
DATA VALID
tHZOE
Notes
22. Device is continuously selected. OE, CE = VIL.
23. WE is HIGH for read cycles.
24. Address valid before or similar to CE transition LOW.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05576 Rev. *O
Page 8 of 18
CY62148EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled) [28, 29]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [29]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 30
tHD
DATA VALID
tHZWE
tLZWE
Notes
28. Data I/O is high impedance if OE = VIH.
29. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05576 Rev. *O
Page 9 of 18
CY62148EV30 MoBL®
Truth Table
CE [31]
WE
OE
H
X
X
High Z
Deselect/Power down
Standby (ISB)
L
H
L
Data out
Read
Active (ICC)
L
H
H
High Z
Output disabled
Active (ICC)
L
L
X
Data in
Write
Active (ICC)
Inputs/Outputs
Mode
Power
Note
31. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05576 Rev. *O
Page 10 of 18
CY62148EV30 MoBL®
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62148EV30LL-45BVI
51-85149 36-ball VFBGA
CY62148EV30LL-45BVXI
51-85149 36-ball VFBGA (Pb-free)
CY62148EV30LL-45ZSXI
51-85095 32-pin TSOP II (Pb-free)
CY62148EV30LL-45ZSXA
51-85095 32-pin TSOP II (Pb-free)
CY62148EV30LL-55SXI
51-85081 32-pin SOIC (Pb-free)
Operating
Range
Industrial
Automotive-A
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 4
8
E V30 LL - XX
XX X
X
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = BV or ZS or S
BV = 36-ball VFBGA
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05576 Rev. *O
Page 11 of 18
CY62148EV30 MoBL®
Package Diagrams
Figure 8. 36-ball VFBGA (6 × 8 × 1.0 mm) BV36A Package Outline, 51-85149
51-85149 *E
Document Number: 38-05576 Rev. *O
Page 12 of 18
CY62148EV30 MoBL®
Package Diagrams (continued)
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
51-85095 *B
Document Number: 38-05576 Rev. *O
Page 13 of 18
CY62148EV30 MoBL®
Package Diagrams (continued)
Figure 10. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
51-85081 *D
Document Number: 38-05576 Rev. *O
Page 14 of 18
CY62148EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CMOS
complementary metal oxide semiconductor
µA
microampere
CE
chip enable
mA
milliampere
I/O
input/output
ns
nanosecond
OE
output enable
pF
picofarad
SRAM
static random access memory
V
volt
TSOP
thin small outline package
W
watt
VFBGA
very fine-pitch ball grid array
WE
write enable
Document Number: 38-05576 Rev. *O
Symbol
Unit of Measure
Page 15 of 18
CY62148EV30 MoBL®
Document History Page
Document Title: CY62148EV30 MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05576
Region
ECN
Submission
Date
Orig. of
Change
Description of Change
**
223225
See ECN
AJU
New data sheet.
*A
247373
See ECN
SYT
Changed status from Advance Information to Preliminary.
Updated Operating Range (Updated Note 7 (Changed VCC stabilization time
from 100 s to 200 s)).
Updated Data Retention Characteristics (Changed maximum value of ICCDR
parameter from 2.0 A to 2.5 A, changed minimum value of tR parameter from
100 s to tRC ns).
Updated Switching Characteristics (Changed minimum value of tOHA
parameter from 6 ns to 10 ns for both 35 ns and 45 ns speed bin, changed
maximum value of tDOE parameter from 15 ns to 18 ns for 35 ns speed bin,
changed maximum value of tHZOE, tHZWE parameters from 12 ns to 15 ns for
35 ns speed bin and 15 ns to 18 ns for 45 ns speed bin, changed minimum
value of tSCE from 25 ns to 30 ns for 35 ns speed bin and 40 ns to 35 ns for
45 ns speed bin, changed maximum value of tHZCE parameter from 12 ns to
18 ns for 35 ns speed bin and 15 ns to 22 ns for 45 ns speed bin, changed
minimum value of tSD parameter from 15 ns to 18 ns for 35 ns speed bin and
20 ns to 22 ns for 45 ns speed bin).
Updated Ordering Information (Changed to include Pb-free Packages).
*B
414807
See ECN
ZSD
Changed status from Preliminary to Final.
Changed the address of Cypress Semiconductor Corporation on page #1 from
“3901 North First Street” to “198 Champion Court”.
Updated Features (Removed 35 ns speed bin).
Updated Pin Configuration (Changed ball C3 from DNU to NC, removed the
Note “DNU pins have to be left floating or tied to VSS to ensure proper
application.” and its reference, added 32-pin SOIC pinout).
Updated Electrical Characteristics (Removed “L” version of CY62148EV30,
changed maximum value of ICC parameter from 2 mA to 2.5 mA and typical
value of ICC parameter from 1.5 mA to 2 mA at f = 1 MHz, changed typical value
of ICC parameter from 12 mA to 15 mA at f = fmax, changed typical value of ISB1
and ISB2 parameters from 0.7 A to 1 A and maximum value of ISB1 and ISB2
parameters from 2.5 A to 7 A).
Updated AC Test Loads and Waveforms (Changed the AC test load
capacitance value from 50 pF to 30 pF).
Updated Data Retention Characteristics (Changed maximum value of ICCDR
parameter from 2.5 A to 7 A, added typical value of ICCDR parameter).
Updated Switching Characteristics (Changed minimum value of tLZOE
parameter from 3 ns to 5 ns, changed minimum value of tLZCE and tLZWE
parameters from 6 ns to 10 ns, changed maximum value of tHZCE parameter
from 22 ns to 18 ns, changed minimum value of tPWE parameter from 30 ns to
35 ns, changed minimum value of tSD from 22 ns to 25 ns).
Updated Ordering Information (Updated part numbers and replaced the
Package Name column with Package Diagram).
Updated Package Diagrams (Updated 36-pin VFBGA from *B to *C, added
32-pin SOIC package diagram (Figure 10)).
*C
464503
See ECN
NXR
Updated Product Portfolio (Included Automotive Range).
Updated Operating Range (Included Automotive Range).
Updated Electrical Characteristics (Included Automotive Range).
Updated Data Retention Characteristics (Included Automotive Range).
Updated Switching Characteristics (Included Automotive Range).
Updated Ordering Information (Updated part numbers (Included Automotive
parts and their related information)).
Document Number: 38-05576 Rev. *O
Page 16 of 18
CY62148EV30 MoBL®
Document History Page (continued)
Document Title: CY62148EV30 MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05576
Region
ECN
Submission
Date
Orig. of
Change
*D
833080
See ECN
VKN
Updated Electrical Characteristics (Added VIL parameter for SOIC package,
added Note 10 and referred the same note in the maximum value of VIL
parameter for SOIC package).
*E
890962
See ECN
VKN
Updated Features (Added Note 1 and referred the same note in 32-pin SOIC
package).
Updated Product Portfolio (Removed Automotive Range).
Updated Operating Range (Removed Automotive Range).
Updated Electrical Characteristics (Removed Automotive Range, added Note
11 and referred the same note in ISB2 parameter).
Updated Data Retention Characteristics (Removed Automotive Range).
Updated Switching Characteristics (Removed Automotive Range).
Updated Switching Characteristics (Added values for all parameters for 55 ns
Industrial range).
Updated Ordering Information (Updated part numbers).
*F
987940
See ECN
VKN
Updated Electrical Characteristics (Changed maximum value of VOL
parameter from 0.4 V to 0.2 V for Industrial Range at IOL = 0.1 mA, changed
maximum value of VIL parameter from 0.6 V to 0.4 V for Industrial Range, SOIC
package at VCC = 2.2 V to 2.7 V, updated Note 10, updated Note 11 (made the
note applicable for both ISB2 and ICCDR parameters).
*G
2548575
08/05/08
NXR
Updated Features (Included Automotive-A Range).
Updated Product Portfolio (Included Automotive-A Range).
Updated Operating Range (Included Automotive-A Range).
Updated Electrical Characteristics (Included Automotive-A Range).
Updated Data Retention Characteristics (Included Automotive-A Range).
Updated Switching Characteristics (Included Automotive-A Range).
Updated Ordering Information (Updated part numbers (Included Automotive-A
parts and their related information)).
*H
2769239
09/25/09
VKN /
AESA
Updated Ordering Information (Updated part numbers).
*I
2944332
06/04/2010
VKN
Updated Truth Table (Added Note 31 and referred the same note in CE
column).
Updated Package Diagrams.
*J
3007403
08/13/2010
AJU
Added Ordering Code Definitions.
Updated in new template.
*K
3110202
12/14/2010
PRAS
Updated Logic Block Diagram.
Updated Ordering Code Definitions.
*L
3302901
07/06/2011
RAME
Updated Functional Description (Removed the reference of AN1064).
Updated Ordering Code Definitions.
Updated Package Diagrams (51-85095).
Updated all the notes.
Updated in new template.
*M
3363097
09/07/2011
AJU
Updated Data Retention Characteristics (Corrected Note cross-reference for
ICCDR parameter (Added Note 14 and referred the same note in ICCDR
parameter)).
Updated Package Diagrams (Updated 36-ball VFBGA and 32-pin SOIC
package specs).
*N
3546715
03/09/2012
TAVA
Updated Electrical Characteristics (Updated Note 10 (Removed the line “Refer
to AN13470 for details”.)).
*O
3733339
09/04/2012
JISH
Minor text edits.
Sunset review.
Document Number: 38-05576 Rev. *O
Description of Change
Page 17 of 18
CY62148EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05576 Rev. *O
Revised September 4, 2012
Page 18 of 18
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.