19-0611; Rev 6; 11/08 KIT ATION EVALU E L B A AVAIL Direct-Conversion TV Tuner ♦ I and Q Baseband Outputs Eliminate All IF-SAW Filters ♦ Integrated RF Tracking Filters ♦ Tunable Baseband Lowpass Filters ♦ Full-Band VHF-III and UHF Tuning ♦ +38dB Digital ACPR, +47dB Analog ACPR ♦ Low Noise Figure: 4.7dB (typ) ♦ Frac-N Synthesizer for -90dBc/Hz Close-In Phase Noise ♦ +3.1V to +3.5V Supply Voltage Range ♦ Ultra-Small, 5mm x 5mm Thin QFN Package Pin Configuration/ Functional Diagram MUX GND_PLL VCC_SYN GND_CP 31 30 29 28 27 26 25 CHARGE PUMP 24 CP MAX3580 SCL 2 23 LDO SERIAL INTERFACE, CONTROL, AND SYNTHESIZER RFIN2 3 Automotive Televisions USB Peripherals 22 GND_TUNE LO RFIN 4 LO 18 BBI+ LEXT 8 17 BBI- 9 10 11 12 13 14 15 16 BBQ+ VCC_RF 7 BBQ- *EP = Exposed paddle. +Denotes a lead-free/RoHS-compliant package. T = Tape-and-reel package. 90 VCC_BB 32 TQFN-EP* 0 OVLD_DET 32 TQFN-EP* -40°C to +85°C TRACKING FILTER N.C. -40°C to +85°C MAX3580ETJ+T 19 BB_AGC GND_LNA 6 IND2 MAX3580ETJ+ 20 VCC_VCO ADDR2 5 IND1 PIN-PACKAGE 21 VTUNE RF_AGC Ordering Information TEMP RANGE 32 + SDA 1 Digital Televisions Digital Terrestrial Set-Tops Laptop Televisions PART REF_BUFF Applications VCC_XTAL TOP VIEW XB The MAX3580 communicates using a 2-wire serial bus. The device operates from a typical +3.3V power supply and dissipates 650mW. The MAX3580 is available in a small 32-pin thin QFN package (5mm x 5mm) with an exposed paddle. Electrical performance is guaranteed over the extended -40°C to +85°C temperature range. ♦ 650mW Power Dissipation (at VCC = +3.3V) XE The MAX3580 fully integrated, direct-conversion TV tuner is designed for Digital Video Broadcasting-Terrestrial (DVB-T) applications. The integrated tuner covers a 170MHz to 230MHz input frequency range for the VHF-III band and 470MHz to 878MHz for the UHF band. The MAX3580 direct-conversion tuner integrates an RF input switch and a multiband tracking filter, allowing low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. The zero-IF architecture eliminates the need for SAW filters by providing baseband I and Q outputs directly to the demodulator. In addition, DC-offset cancellation is implemented on-chip using a mixed-signal architecture to improve the second-order distortion performance and the dynamic range of the downstream digitizer and demodulator. The MAX3580 features dynamic gain control of more than 76dB and a typical midband noise figure of 4.7dB referred to the LNA input. The VCO architecture optimizes both in-band and wideband phase noise for OFDM applications where sensitivity to both 1kHz phase noise and wideband phase noise related to strong adjacents can be a problem. Features ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3580 General Description MAX3580 Direct-Conversion TV Tuner ABSOLUTE MAXIMUM RATINGS VCC_ _ to GND......................................................-0.3V to +3.6V SDA, SCL, ADDR2, MUX, REF_BUFF, BB_AGC, RF_AGC to GND ................................-0.3V to +3.6V All Other Pins to GND ..............................-0.3V to (+VCC + 0.3V) RF Input Power ...............................................................+10dBm Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Continuous Power Dissipation (TA = +70°C) (derate 21.3mW/°C above +70°C) ..............................1702mW Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX3580 EV kit, VCC = +3.1V to +3.5V, GND = 0V, BB_AGC = RF_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and BBQ_ are open, no input signal, VCO active, registers set according to the specified default register conditions, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = +3.3V, TA =+25°C, unless otherwise specified.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.5 V 197 225 mA SUPPLY VOLTAGE AND CURRENT Supply Voltage Supply Current VCC ICC 3.1 Active Shutdown mode <100 µA RF_AGC AND BB_AGC Input Bias Current IAGC RF and Baseband AGC Control Voltage VAGC VAGC at +0.5V and +2.85V -50 Maximum gain 2.85 +50 Minimum gain 0.5 µA V SERIAL INTERFACE AND MUX OUTPUT (SCL, SDA, MUX) Input Logic-Level Low VIL Input Logic-Level High VIH 0.3 x VCC 0.7 x VCC SDA, SCL Input Current -10 Output Logic-Level Low VOL Sink current = 0.3mA Output Logic-Level High VOH Source current = 0.3mA 2 V 0.05 x VCC Input Hysteresis V VCC 0.5 _______________________________________________________________________________________ V +10 µA 0.4 V V Direct-Conversion TV Tuner (MAX3580 EV kit, VCC = +3.1V to +3.5V, GND = 0V. RF_AGC = BB_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and BBQ_ loaded by RL greater than 2kΩ and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Operating Frequency Range SYMBOL fRF Overall Voltage Gain (Note 2) CONDITIONS Gain specification met across this frequency band 470 878 RF_AGC = BB_AGC = +2.85V 74 RF_AGC = BB_AGC = +0.5V Within each VHF-III and UHF band (Note 10) Worst case across band selected, 75Ω system Input 3rd-Order Intercept Point NF IIP2 IIP3 RF 1dB Desense LO Harmonic Reception -3 5.4 4.7 858MHz 6.5 Broadband (Notes 4, 5) > 26 Broadband (Notes 4, 6) > -4 Broadband, RF_AGC adjusted for 49dB of gain > 12 Narrowband (Notes 4, 7) +16 PDESIRED = -78dBm and converted to 3.75MHz, PTONE 10MHz higher (Note 4) -22 RF_AGC adjusted for 49dB of gain, PDESIRED = -55dBm +1 > -60 RF input range of 960MHz to 1400MHz > -40 I/Q phase error at 1MHz I/Q amplitude error at 1MHz -1 dBm dBc +1 -3 -1.5 +3 Degrees +1.5 dB -50 -20 470MHz to 878MHz -50 -35 < -50 -20 At 1kHz to 10kHz (Note 3) -80 -90 At 100kHz (Note 3) -94 -107 dB dBc 50MHz to 470MHz At 1MHz dB dBm > 60 878MHz to 1732MHz ΦN dB dBm RF input range of 170MHz to 960MHz (Note 8) DC to 30MHz, RF input to baseband output, relative to desired channel MHz dB -6 Narrowband, RF_AGC adjusted for 49dB of gain (Note 7) UNITS dB 15 Broadband, RF_AGC adjusted for 49dB of gain Isolation Phase Noise (Single-Sideband, Closed Loop) +3 7 470MHz 8MHz RF channel at baseband, tested at 169MHz and 469MHz Spurious at the RF Input (Note 3) 26 230MHz RF Channel Flatness Quadrature Accuracy MAX 230 Input Return Loss Input 2nd-Order Intercept Point TYP 170 RF Gain Flatness Noise Figure (DSB) (Notes 3, 4) MIN dBmV dBc/Hz -130 _______________________________________________________________________________________ 3 MAX3580 AC ELECTRICAL CHARACTERISTICS MAX3580 Direct-Conversion TV Tuner AC ELECTRICAL CHARACTERISTICS (continued) (MAX3580 EV kit, VCC = +3.1V to +3.5V, GND = 0V. RF_AGC = BB_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and BBQ_ loaded by RL greater than 2kΩ and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 27 MHz SIGMA-DELTA FRACTIONAL-N SYNTHESIZER REFERENCE OSCILLATOR Frequency fREF Input Impedance ZIN 4 Voltage Gain Output Impedance ZOUT Buffered Output 10kΩ || 10pF load 0.7 RF N Divider Ratio (Notes 12, 13) 12 RF R Divider Ratio VHF band operation requires R divider = 2 1 10 kΩ 30 V/V 15 Ω VP-P DIVIDERS Fractional-N Resolution 251 2 20 — — Bits LO PHASE DETECTOR AND CHARGE PUMP Phase-Detector Frequency Charge-Pump Current 4 ICP 600 Gain = 1 1200 Charge-Pump Tri-State Current Charge-Pump Compliance Range 27 Gain = 0 Charge-pump positive to negative current matching of ≤ ±5% MHz µA -10 +10 µA 0.4 VCC 0.4 V 2160 4400 MHz 4 16 — LOCAL OSCILLATOR Tuning Frequency Range fOSC Tank Frequency VCO Dividers BASEBAND STAGE Nominal Output Voltage 1dB Output Compression Point (Note 2) P1dB Differential voltage at 3MHz Output Impedance Differential Passband AGC Range BB_AGC = 0.5V to 2.85V Passband Cutoff Attenuation At 3.8MHz (UHF Mode); at 3.325MHz (VHF Mode) Passband Differential Gain Error 2MHz to 3.8MHz, I channel vs. Q channel (UHF mode) Passband Group Delay From DC to 3.8MHz over any 1.1kHz band (UHF mode) Group Delay Mismatch From 0.1MHz to 3.8MHz, I channel vs. Q channel (UHF mode) (Note 9) 4 1.6 30 1 VP-P 2 VP-P 60 Ω 50 dB 2 -0.45 5 dB +0.45 dB 5 ns <2 ns _______________________________________________________________________________________ Direct-Conversion TV Tuner (MAX3580 EV kit, VCC = +3.1V to +3.5V, GND = 0V. RF_AGC = BB_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and BBQ_ loaded by RL greater than 2kΩ and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Rejection Ratio CONDITIONS MIN At 5.25MHz (UHF mode) 23 At 4.75MHz (VHF mode) 23 At 13.25MHz (UHF mode) 63 At 11.75MHz (VHF mode) 62 VCM Common mode (Note 11) Output DC Offset BB_AGC = 2.85V Baseband Highpass Cutoff Programmable AGC Gain Slope BB_AGC = 0.5V to 2.85V Ratio of Passband to Stopband Noise BB_AGC = 2.85V, 10kHz to 3.8MHz vs. 16.2MHz to 23.8MHz MAX UNITS dB 84 At > 16.2MHz DC Output Voltage TYP 0.485 x VCC -70 VDC +70 mV 35 dB/V 20 to 200 14 Hz 15 dB 2-WIRE INTERFACE Clock Rate Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: 400 kHz Min and Max limits are guaranteed by test above TA = +25°C and are guaranteed by design and characterization at TA = -40°C. The default register settings are not production tested. Load registers no sooner than 100µs after power-up. The specified overall voltage gain is suitable to amplify -93dBm to -20dBm to 1VP-P at the baseband output. Guaranteed by design characterization over the specified operating conditions. Not production tested. BB_AGC adjusted for gain = 72dB with RF_AGC at 2.85V. Two tones at a) 230MHz and 431MHz with IM measured at 201MHz and b) 230MHz and 701MHz with IM measured at 471MHz. Two tones at 499MHz and 689MHz with IM measured at 879MHz. IM3 measured with two tones within the adjacent channel at a) 205.75MHz and 210.5MHz with IM measured at 201MHz and b) 475.25MHz and 479.5MHz with IM measured at 471MHz. Measured at RF = 171MHz with harmonics at 511MHz (3rd harmonic) and 851MHz (5th harmonic). Delay of 2ns equal 2.74° phase error. UHF rolloff of 4dB in addition to gain flatness specification. Production tested at VCC = +3.5V to limits of 1.7V -0.12/+0.1V. Operation in the VHF band requires the R-divider = 2. Operation of the N-divider at values below 12 is not tested or guaranteed. _______________________________________________________________________________________ 5 MAX3580 AC ELECTRICAL CHARACTERISTICS (continued) MAX3580 Direct-Conversion TV Tuner Performance to Standards The following is selected overall performance data for the MAX3580 + digital demodulator. NorDig refers to standard Unified 1.0.2 available from www.nordig.org. Table 1 shows the typical overall performance as measured using the MAX3580 and one current production DVB-T demodulator. This reference design is available in NIM card form factor upon request. MBRAI refers to standard MBRAI 04-102 IEC 62002-1 available from www.ansi.org. Modulation of wanted and interfering channel(s) is 8k mode, 16 QAM, C/R = 3/4, GI = 1/4, sensitivity or immunity Reference Bit Error Rate is 2 x 10e-4, unless stated otherwise. Table 1. Selected Typical MBRAI and NorDig Performance TEST SCENARIO 6 COMMENTS SPEC MINIMUM MAX3580 TYPICAL MBRAI S2 Immunity/ACPR for N ±1 adjacent ch. 29dB 40dB MBRAI S2 Immunity/ACPR N ±2 alternate ch. 40dB 43dB MBRAI L3 Linearity/crossmod. with N+2 and N+4 ch. 40dB 47dB NorDig 16 QAM 2/3 Sensitivity at channel 21 (470 MHz) -84.1dBm -85.1dBm NorDig QPSK 1/2 Sensitivity at channel 42 (642 MHz) -92.1dBm -94.8dBm NorDig 64 QAM 7/8 Sensitivity at channel 59 (778 MHz) -74.7dBm -76dBm _______________________________________________________________________________________ Direct-Conversion TV Tuner 100 110 MAX3580 toc02 110 MAX3580 toc01 110 80 TA = +55°C TA = +25°C GAIN (dB) GAIN (dB) TA = +85°C 80 TA = -40°C 90 TA = 0°C 90 BB_AGC = 2.85V 100 100 TA = +25°C GAIN (dB) VOLTAGE GAIN vs. RF_AGC CONTROL VOLTAGE UHF BAND VOLTAGE GAIN vs. FREQUENCY MAX3580 toc03 VHF-III BAND VOLTAGE GAIN vs. FREQUENCY TA = 0°C 90 70 60 TA = +25°C, +55°C 50 TA = +85°C 40 80 TA = +85°C 30 TA = +55°C 20 70 10 150 160 170 180 190 200 210 220 230 240 250 450 500 550 600 650 700 750 800 850 900 FREQUENCY (MHz) FREQUENCY (MHz) -90 220MHz -100 2.0 2.5 3.0 15 NOISE FIGURE (dB) NOISE FIGURE (dB) 620MHz -80 1.5 NOISE FIGURE vs. UHF FREQUENCY 15 -70 1.0 20 MAX3580 toc05 MAX3580 toc04 20 TA = +85°C TA = +55°C 10 10 TA = +25°C TA = +85°C TA = +55°C TA = -40°C 5 5 TA = -40°C TA = +25°C -110 1 10 100 OFFSET FREQUENCY (kHz) 1000 175 200 225 FREQUENCY (MHz) 250 450 500 550 600 650 700 750 800 850 900 FREQUENCY (MHz) VHF MODE NOISE FIGURE vs. VOLTAGE GAIN 30 25 MAX3580 toc07 0.1 0 0 150 -120 NOISE FIGURE (dB) PHASE NOISE (dBm/Hz) -60 0.5 RF_AGC CONTROL VOLTAGE (V) NOISE FIGURE vs. VHF FREQUENCY PHASE NOISE vs. OFFSET FREQUENCY -50 0 MAX3580 toc06 70 TA = +85°C 20 15 TA = -40°C 10 TA = +25°C, +55°C 5 fRF = 220MHz BB_AGC = 2.85V 0 60 65 70 75 80 85 90 VOLTAGE GAIN (dB) _______________________________________________________________________________________ 7 MAX3580 Typical Operating Characteristics (MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) UHF MODE NOISE FIGURE vs. VOLTAGE GAIN VOLTAGE GAIN vs. BB_AGC CONTROL VOLTAGE TA = -40°C 70 TA = +25°C, +55°C 60 50 TA = +85°C 40 -20 -30 -40 -50 -70 fRF = 620MHz BB_AGC = 2.85V 0 65 70 75 80 85 -90 10 -100 90 0 0.5 1.0 1.5 2.0 2.5 BB_AGC CONTROL VOLTAGE (V) NORMALIZED BASEBAND FREQUENCY RESPONSE NORMALIZED BASEBAND FREQUENCY RESPONSE -5 TA = +25°C -5 TA = 0°C -10 TA = +85°C GAIN (dB) -15 0 -20 -25 TA = +25°C -15 -5 -10 TA = +85°C -20 -25 -15 -25 -30 -30 -35 -35 -40 -40 -45 1 2 3 4 0 5 TA = +25°C -50 -50 0 TA = 0°C -40 BB_BW<3:0> = "1001" 7MHz CHANNEL MODE -45 -50 TA = +85°C -20 -35 BB_BW<3:0> = "1011" 8MHz CHANNEL MODE 1 2 3 4 0 5 5 10 5 BB_BW <3:0> = "1001" 7MHz CHANNEL MODE -5 MAX3580 toc14 NORMALIZED BASEBAND FREQUENCY RESPONSE 0 GAIN (dB) -10 -15 TA = +25°C -20 TA = +85°C -25 TA = 0°C -30 -35 -40 -45 0 5 10 15 FREQUENCY (MHz) 15 FREQUENCY (Hz) FREQUENCY (MHz) FREQUENCY (MHz) 8 20 BB_BW<3:0> = "1011" 8MHz CHANNEL MODE 0 -30 -45 10 15 FREQUENCY (MHz) 5 GAIN (dB) TA = 0°C 5 NORMALIZED BASEBAND FREQUENCY RESPONSE 5 MAX3580 toc11 0 NOISE LIMITED 0 3.0 VOLTAGE GAIN (dB) 5 -10 20 MAX3580 toc12 60 VHF INPUT -80 30 5 UHF INPUT -60 MAX3580 toc13 TA = +25°C -10 REJECTION RATIO (dB) GAIN (dB) NOISE FIGURE (dB) 80 20 10 TA = -40°C MAX3580 toc10 90 TA = +55°C 15 RF_AGC = 2.85V 100 0 MAX3580 toc09 TA = +85°C 25 BASEBAND FILTER REJECTION RATIO 110 MAX3580 toc08 30 GAIN (dB) MAX3580 Direct-Conversion TV Tuner 20 25 _______________________________________________________________________________________ 20 25 Direct-Conversion TV Tuner BB_BW <3:0> = "1011" 8MHz CHANNEL MODE -65 20 TA = +55°C 15 TA = +85°C 10 5 BB_BW <3:0> = "1001" 7MHz CHANNEL MODE 30 40 TA = -40°C TA = +25°C TA = +25°C 0 0 50 TA = +85°C 10 0.5 1.0 1.5 2.0 2.5 0 3.0 0.5 1.0 0 MAX3580 toc18 35 2.5 3.0 RF INPUT RETURN LOSS vs. UHF FREQUENCY RF PORT-TO-PORT ISOLATION 40 2.0 BB_AGC VOLTAGE (V) BB_AGC VOLTAGE (V) FREQUENCY (MHz) 1.5 MAX3580 toc19 20 Zo = 75Ω 25 RETURN LOSS (dB) 30 GAIN (dB) RFIN2 TO RFIN 20 15 RFIN TO RFIN2 10 -5 -10 5 0 -15 100 200 300 400 500 600 700 800 900 1000 525 600 675 750 UHF FREQUENCY (MHz) RF INPUT RETURN LOSS vs. VHF FREQUENCY SUPPLY CURRENT vs. SUPPLY VOLTAGE Zo = 75Ω 825 200 TA = +25°C TA = 0°C -5 900 MAX3580 toc21 0 450 FREQUENCY (MHz) MAX3580 toc20 195 TA = -40°C ICC (mA) 10 RETURN LOSS (dB) 0 TA = +55°C 15 5 TA = -40°C MAX3580 toc17 20 0 -75 620MHz RF_AGC = 2.85V 25 NOISE FIGURE (dB) NOISE FIGURE (dB) -55 220MHz RF_AGC = 2.85V 25 30 MAX3580 toc16 30 MAX3580 tpc15 -45 STOPBAND NOISE (dBm) UHF MODE NOISE FIGURE vs. BB_AGC VOLTAGE VHF MODE NOISE FIGURE vs. BB_AGC VOLTAGE STOPBAND NOISE vs. FREQUENCY -10 190 TA = +85°C -15 TA = +55°C 185 -20 150 175 200 225 VHF FREQUENCY (MHz) 250 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) _______________________________________________________________________________________ 9 MAX3580 Typical Operating Characteristics (continued) (MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Direct-Conversion TV Tuner MAX3580 Pin Description 10 PIN NAME 1 SDA Serial-Data Input Line. Requires a pullup resistor to VCC. FUNCTION 2 SCL Serial-Clock Input. Requires a pullup resistor to VCC. 3 RFIN2 Second RF Input 4 RFIN First RF Input 5 ADDR2 6 GND_LNA 7 VCC_RF 8 LEXT 9 RF_AGC 10 IND1 11 IND2 VHF Inductor Pin 2. Keep traces to inductor as short as possible. 12 N.C. No Connection 13 OVLD_DET 14 VCC_BB 15 BBQ- 16 BBQ+ 17 BBI- In-Phase, Inverted Baseband Output 18 BBI+ In-Phase, Noninverted Baseband Output Address Line. Sets the 3rd LSB of the device address. Connect to ground to set for “0” or VCC to set for “1.” Not Internally Connected. Connect to ground. DC Supply for RF LNA. Connect as close as possible a 100pF capacitor from this pin to GND. External Bias Inductor. Connect to VCC with a 270nH inductor. Gain Control Input for RF VGA. VHF Inductor Pin 1. Keep traces to inductor as short as possible. Overload Detector Output. No connection required to this pin. DC Supply for Baseband Filter. Connect as close as possible a 10nF capacitor from this pin to ground. Quadrature Inverted Baseband Output Quadrature Noninverted Baseband Output 19 BB_AGC 20 VCC_VCO Gain Control Input for Baseband VGAs 21 VTUNE 22 GND_TUNE 23 LDO 24 CP 25 GND_CP Ground for the Charge Pump 26 VCC_SYN DC Supply for Synthesizer and Serial-Interface Control. Connect as close as possible a 10nF capacitor from this pin to ground. 27 GND_PLL Ground for the PLL 28 MUX 29 REF_BUFF Buffered Output of Reference Oscillator 30 VCC_XTAL DC Supply for Reference Oscillator. Connect as close as possible a 10nF capacitor from this pin to ground. 31 XB Reference Input. Connect to a parallel resonant mode XTAL through a load-matching capacitor, or can also be used as a reference clock input pin. 32 XE Reference Oscillator Feedback. Connect to a capacitive divider when used in self-oscillating mode. — EP Exposed Paddle. Internally connected to ground. Solder EP to the board’s ground plane to achieve the lowest possible impedance path and optimum RF performance. DC Supply for the VCO. Connect as close as possible a 100pF capacitor from this pin to ground. VCO Tuning Voltage Input. Connect the PLL loop filter output directly to this pin. Ground Reference for the Tuning Voltage. Connect to ground of the loop filter. VCO LDO Output. Connect a 0.1µF capacitor to ground. Charge-Pump Output. Connect the charge-pump output to the PLL loop filter input. Multiplex Output Line. Can be used as a PLL lock-detector output. ______________________________________________________________________________________ Direct-Conversion TV Tuner REF_BUFF 32 31 30 28 29 GND_CP VCC_SYN VCC GND_PLL MUX VCC_XTAL XE XB VCC 26 27 CHARGE PUMP 1 SDA 25 24 CP MAX3580 2 SCL RFIN2 RFIN ADDR2 GND_LNA VCC VCC_RF 23 SERIAL INTERFACE, CONTROL, AND SYNTHESIZER 3 22 LO 4 21 5 20 LDO GND_TUNE VTUNE VCC_VCO VCC 19 6 TRACKING FILTER 0 90 BB_AGC LO 7 18 8 17 BBI+ I CHANNEL 14 15 BBI- 16 BBQ+ 13 BBQ- 12 VCC_BB 11 OVLD_DET 10 N.C. RF_AGC 9 IND2 LEXT IND1 VCC VCC Q CHANNEL RF_AGC RF_AGC BB_AGC MAX3580 3.3V 1nF 10kΩ 1kΩ 39kΩ 1kΩ Rohm 2SA1037AK DEMODULATOR PWM 1μF 100nF Figure 1. Single-Loop AGC Schematic ______________________________________________________________________________________ 11 MAX3580 Typical Application Circuit MAX3580 Direct-Conversion TV Tuner Detailed Description Programmable Registers The MAX3580 includes thirteen write/read registers and three read-only registers. See Table 2 for register configuration and the Register Description section. The register configuration of Table 2 shows each bit name and the bit usage information for all registers. “U” labeled under each bit name indicates that the bit value is user defined to meet specific application requirements. A “0” or “1” indicates that the bit must be set to the defined “0” or “1” value for proper operation. Operation is not tested or guaranteed if these bits are programmed to other values and is only for factory/bench evaluation. For field use, always program to the defined operational state. Note that all registers must be written after and no earlier than 100µs after device power-up. Note: To correctly tune the VCO during a channel change, first write to Register 0x05, continuing through Register 0x06 to Register 0x12, and then write to Register 0x00 through Register 0x04. Table 2. Register Configuration 8-BIT DATA REGISTER ADDRESS 12 REGISTER SETTINGS REGISTER NAME D7 D6 D5 D4 D3 D2 D1 D0 OPERATION DEFINED DEFAULT SETTINGS (POR) 0x00 N7 U N6 U N5 U N4 U N3 U N2 U N1 U N0 U — H17 N-Divider Integer 0x01 MP 0 LI1 0 LI0 0 INT U F19 U F18 U F17 U F16 U — h18 N-Divider Frac2 0x02 F15 U F14 U F13 U F12 U F11 U F10 U F9 U F8 U — h00 N-Divider Frac1 0x03 F7 U F6 U F5 U F4 U F3 U F2 U F1 U F0 U — h00 N-Divider Frac0 0x04 TFS<7> U TFS<6> U TFS<5> U TFS<4> U TFS<3> U TFS<2> U TFS<1> U TFS<0> U — hDB Tracking Filter Series Caps 0x05 VCO_DIV1 U VCO_DIV0 U RFS U TF_BS U TFP<3> U TFP<2> U TFP<1> U TFP<0> U — h7C Tracking Filter Parallel Cap 0x06 RDIV U ICP U CPS U ADLY1 0 ADLY0 1 LF_DIV2 U LF_DIV1 U LF_DIV0 U — h0A PLL Configuration 0x07 CP_TST2 0 CP_TST1 0 CP_TST0 0 X 0 TURBO 1 LD_MUX2 U LD_MUX1 U LD_MUX0 U — h08 Test Functions 0x08 X 0 SHDN_BG U SHDN_PD 1 SHDN_REF U SHDN_SYN U SHDN_MX U SHDN_BB U SHDN_RF U — h00 Shutdown Control 0x09 VCO1 U VCO0 U BS2 U BS1 U BS0 U VAS 1 ADL 0 ADE 0 — hC0 VCO Control 0x0A BB_BW3 U BB_BW2 U BB_BW1 U BB_BW0 U X 0 PD_TH2 U PD_TH1 U PD+TH0 U — h87 Baseband Control 0x0B BB_BIA 0 DC_DAC8 0 DC_MO1 1 DC_MO0 1 DC_SP1 1 DC_SP0 0 DC_TH1 0 DC_TH0 0 h38 h40 DC Offset Control 0x0C DC_DAC7 0 DC_DAC6 0 DC_DAC5 0 DC_DAC4 0 DC_DAC3 0 DC_DAC2 0 DC_DAC1 0 DC_DAC0 0 h00 h00 DC Offset DAC 0x0D X 0 FUSE_TH 0 X 0 WR 0 TFA<3> U TFA<2> U TFA<1> U TFA<0> U — h00 ROM Table Address 0x0E TFD<7> 0 TFD<6> 0 TFD<5> 0 TFD<4> 0 TFD<3> 0 TFD<2> 0 TFD<1> 0 TFD<0> 0 h00 h00 ROM Table Fuse Data 0x0F X 0 X 0 X 0 X 0 MX_HR<3> 0 MX_HR<2> 0 MX_HR<1> 0 MX_HR<0> 0 h00 h00 Mixer Harmonic Rejection 0x10 TFR<7> TFR<6> TFR<5> TFR<4> TFR<3> TFR<2> TFR<1> TFR<0> N/A ROM Table Data Read Back 0x11 POR VASA VASE LD DC_LO DC_HI GKT PD_OVLD N/A N/A Chip Status Read Back 0x12 VCO1A VCO0A BS2A BS1A BS0A ADC2 ADC1 ADC0 N/A N/A Autotuner Read Back N/A ______________________________________________________________________________________ Direct-Conversion TV Tuner N-Divider Integer (Register Address 0x00) N<7:0>: VCO Integer-N Divider Ratio N-Divider Frac2 (Register Address 0x01) MP: Minimum CP Pulse Width. Always set to 0 (factory use only). LI1, LI0; CP Linearity Control. Always set to 00 (factory use only). INT: Integer Mode ON/OFF. Set to 0 for normal operation. F<19:16>: MSB of Main Divider Fractional Divide Ratio N-Divider Frac1, Frac0 (Register Address 0x02, 0x03) F<15:0> 16 LSB of Main Divider Fractional Divide Ratio Tracking Filter Series Capacitor (Register Address 0x04) TFS<7:4>: Tracking Filter Parallel Capacitor. TFS<3:0>: Tracking Filter Series Capacitor. See the RF tracking filter description in the Applications Information section. Tracking Filter Parallel Capacitor and VCO Control (Register Address 0x05) VCO_DIV1, VCO_DIV0: VCO Post Divider 00 = Divide by 4 use for RF frequencies of 540 to 868 MHz 01 = Divide by 8 use for RF frequencies of 470 to 550 MHz 10 = Divide by 16 use for RF frequencies of 170 to 230 MHz 11 = Divide by 32 is not used RFS: RF Input Select 0 = RFIN2 selected 1 = RFIN selected TF_BS: Tracking Filter Band Select 1 = VHF band 0 = UHF band TFP<4:0>: Tracking Filter Shunt Capacitor See the RF tracking filter description in the Applications Information section. PLL Configuration (Register Address 0x06) LF_DIV2, LF_DIV1, LF_DIV0: Prescaler for Internal Low Frequency Clocks 000 - 110 = Divided by 8 to 14 for REF crystal frequencies of 15MHz to 28MHz 111 = Divide by 2 for REF crystal frequencies of 4MHz ADLY1, ADLY0: VCO Autotuner Delay Selection CPS: Charge-Pump Current Mode 0 = Controlled by ICP bit 1 = Controlled by VCO autotuner ICP: Charge-Pump Current 0 = 600µA 1 = 1200µA RDIV: PLL Reference Divider Ratio 0 = Divide by 1 1 = Divide by 2 Test Functions (Register Address 0x07) CP_TST<2:0>: Charge-Pump Test Modes 000 = Normal operation 100 = Low impedance* 101 = Source 110 = Sink 111 = High impedance LD_MUX: Lock-Detector Mode 000 = Normal operation: high = PLL locked, low = unlocked 001 = Monitor N-divider output, post-divided by 2 010 = Monitor R-divider output* 011 = Modulator test vector output (factory use only) 1XX = Bias current trim (factory use only) *Not production tested. ______________________________________________________________________________________ 13 MAX3580 Register Descriptions MAX3580 Direct-Conversion TV Tuner Shutdown Control (Register Address 0x08) SHDN_BG: Main Bandgap 0 = Enabled 1 = Disabled The main bandgap can and will be shut down once all other blocks are shut down (i.e., all bits in this shutdown register and bits VCO_ in the VCO Control Register and bits DC_MO_ in the DC Offset Control Register are shut down). SHDN_PD: Baseband Power Detector For factory use only. Set to 1 at all times. SHDN_RF: RF LNA/VGA: 0 = Enabled 1 = Disabled SHDN_MIX: I/Q Mixer and LO Drivers 0 = Enabled 1 = Disabled SHDN_BB: Baseband Filters and VGA 0 = Enabled 1 = Disabled SHDN_SYN: Fractional PLL 0 = Enabled 1 = Disabled VAS: VCO Band Autoselect 0 = VCO band select controlled by bits VCO<1:0> 1 = Controlled by autotuner ADL: VCO ADC Latch Enable Bit 1 = Latches ADC value 0 = Default ADE: Enable VCO Tune Voltage DAC Read 1 = Enables ADC read 0 = Default Baseband Control (Register Address 0x0A) PD_TH<2:0>: Detection Threshold for Baseband Power Detector BB_BW<3:0>: Baseband Filter Bandwidth. Optimum values for 7MHz and 8MHz wide RF channels can be taken from the ROM table. DC Offset Control (Register Address 0x0B) DC_TH<1:0>: DC Offset Correction Thresholds. Keeps output within: 00 = Output within ±0.55V of balanced state 11 = Output within ±0.75V of balanced state DC_SP<1:0>: DC Offset Correction Speed (or Highpass Corner Frequency). 11 = Fast (~500Hz) 01 = Slow (~20Hz) SHDN_REF: Controls the Crystal Oscillator Buffered Output 00 = Off/hold DAC values DC_MO<1:0>: Mode of Operation 0 = Enabled 1 = Disabled The XTAL oscillator activation results from the SHDN_SYN, SHDN_REF bits: If either one is on, the XTAL oscillator runs. The XTAL oscillator is shut down only if both bits are off. 00 = Off 10/01 = Sets I/Q channel DACs direct from register 11 = Normal operation DC_DAC<8>: MSB for DC Offset DAC VCO Control (Register Address 0x09) VCO<1:0>: Selects 1 of 3 VCO Bands. 00 turns off VCO block completely. BS<2:0>: Selects 1 of 8 VCO Sub-Bands BB_BIA: Baseband Filter Op-Amp Bias Settings 0 = Low 1 = High *Not production tested. 14 ______________________________________________________________________________________ Direct-Conversion TV Tuner Tracking Filter ROM Address (Register Address 0x0D) TFA<3:0>: Tracking Filter ROM Address. See Table 3. Tracking Filter Write Data (Register Address 0x0E) TFD<7:0>: Tracking Filter Data for ROM Tracking Filter ROM Read Back (Read Only) (Register Address 0x10) TFR<7:0>: Tracking Filter ROM Data Read Back Status (Read Only, for Factory Use Only) (Register Address 0x11) POR: Power-On Reset* 0 = Power has not been reset since the last read. 1 = Power has been reset since the last read. Gets reset after reading back address 8’h0C. VASA, VASE: VCO Autotuner Status* LD: PLL Lock Detector 0 = PLL unlocked 1 = PLL locked DC_HI: DC Offset Correction Detected Positive Signal Excursion in Either I or Q Channel* DC_LO: DC Offset Correction Detected Negative Signal Excursions in Either I or Q Channel* PD_OVLD: Baseband Power Detector 0 = Baseband signal below threshold 1 = Baseband signal above threshold Autotuner Read Back (Read Only, for Factory Use Only) (Register Address 0x12) VCOA<1:0> VCO Tank Selected by Autotuner* BSA<1:0> Sub-Band VCO Selected by Autotuner* ADC<2:0> VCO Tank Voltage ADC* *Not production tested. Table 3. MAX3580 Fuse Table BYTE 7 00 6 5 4 3 Unused 2 1 0 Bias DESCRIPTION Bias trim 01 VHF (200MHz) parallel cap VHF (200MHz) series cap VHF high series cap 02 Unused VHF (200MHz) shunt cap VHF shunt cap 03 UHF low (470MHz) parallel cap UHF low (470MHz) series cap UHF low series cap low 04 UHF high (860MHz) shunt cap UHF low (470MHz) shunt cap UHFhigh/low parallel cap 05 UHF high (860MHz) parallel cap UHF high (860MHz) series cap 06 Baseband filter UHF (8MHz) coefficient. Baseband filter VHF (7MHz) coefficient. BB filter bandwidth X Read only 07 X X X X X X UHF high series cap RO ______________________________________________________________________________________ 15 MAX3580 DC Offset DAC (Register Address 0x0C) DC_DAC<7:0>: Value to Program to I/Q DC Offset DAC. Note that the MSB is located in the previous register. MAX3580 Direct-Conversion TV Tuner To Read Back Fuses IMPORTANT NOTICE: When reading other addresses than 8’h00 (the system trim bits), it is possible that the data going to the bias cells will be disturbed due to the architecture of the fuse bank. This means the bias current could change while reading back fuse data. 1) Write 8’hXX to TFA. XX is the address of the fuse column you want to read. 2) Read 8’hXX from TFR. TFR is the Tracking Filter Read Register. 3) Repeat steps 1 and 2 for other addresses. 2-Wire Serial Interface The MAX3580 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). The serial interface allows communication between the MAX3580 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX3580 behaves as slave devices that transfer and receive data to and from the master. Pull SDA and SCL high with external pullup resistors (1kΩ or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles are required to transfer a byte in or out of the MAX3580 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3580 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. Slave Address The MAX3580 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is determined by the state of the ADDR2 pin and is equal to 11000[ADDR2]0 (see Table 4). The eighth bit (R/W) following the 7-bit address determines whether a read or write operation will occur. The MAX3580 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 2). Table 4. Address Configuration ADDRESS (WRITE/READ) ADDR2 C0/C1HEX 0 C4/C5 HEX 1 SLAVE ADDRESS S 1 1 0 0 0 ADDR2 0 R/ W ACK 1 2 3 4 5 6 7 8 9 SDA SCL Figure 2. MAX3580 Slave Address Byte 16 ______________________________________________________________________________________ Direct-Conversion TV Tuner START WRITE DEVICE ADDRESS R/ W 1100000 0 ACK WRITE REGISTER ADDRESS ACK Read Cycle When addressed with a read command, the MAX3580 allows the master to read back a single register or multiple successive registers. A read cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit (R/W = 0). The MAX3580 issues an ACK if the slave address byte is successfully received. The bus master must then send the address of the first register it wishes to read. The slave acknowledges the address. Then a START condition is issued by the master, followed by the 7 slave address bits and a read bit (R/W = 1). The MAX3580 issues an ACK if the slave address byte is successfully received. The MAX3580 starts sending data MSB first with each SCL clock cycle. At the 9th clock cycle, the master can issue an ACK, and continue to read successive registers, or the master terminate the transmission by issuing a NACK. The read cycle does not terminate until the master issues a STOP condition. Figure 4 illustrates an example in which Registers 0 through 2 are read back. WRITE DATA TO REGISTER 0x00 ACK WRITE DATA TO REGISTER 0x01 ACK WRITE DATA TO REGISTER 0x02 ACK STOP 0x00 0x0E 0xE1 0xD8 Figure 3. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively. S T A R T DEVICE ADDRESS R/ W 11000000 0 A C K REGISTER ADDRESS 00000000 A C K S T A R T DEVICE ADDRESS R/ W 11000000 1 A C K REG 00 DATA xxxxxxxx A C K REG 01 DATA xxxxxxxx A C K REG 02 DATA xxxxxxxx N A C K S T O P Figure 4. Example: Receive data from read registers. ______________________________________________________________________________________ 17 MAX3580 Write Cycle When addressed with a write command, the MAX3580 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3580 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to. If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX3580 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX3580 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which Registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively. MAX3580 Direct-Conversion TV Tuner Applications Information Band Selection The MAX3580 is designed to be suitable for operation in the 170MHz to 230MHz VHF-III band and in the 470MHz to 878MHz UHF band. RF Inputs A switch selects either RFIN or RFIN2 as the input to the single-ended broadband matched LNA. This switch is programmed through the RFS bit (bit 5) of register 0x05. The LNA provides a continuous gain control range of typically 50dB before the signal is downconverted. For optimal matching above 600MHz, add a 5nH to 6nH inductor in series with a capacitor at either of the RF input. Application Note: Front End Diplexer Filter for MAX3580 is available, detailing the implementation of a UHF and VHF simple diplexer. This simple diplexer improves strong-signal-handling capabilities of the MAX3580. DC-Offset Cancellation The MAX3580 features an on-chip fast-settling, DC-offset cancellation circuitry that requires no off-chip components. Note that the offset correction circuit is not enabled when the device is powered up. To enable the offset correction circuit, program the DC-Offset Control Register to the recommended default setting. When active, the offset correction circuit creates a highpass characteristic in the signal path with a typical corner frequency of 200Hz, and the residual DC offset can be as high as ±70mV. Baseband Power Detector Maxim recommends disabling this feature. See explanation in the Shutdown Control (Register Address 0x08) section and Table 2 (address 0x08, bit D5). For singleloop AGC control, see Figure 1. Synthesizer Loop Filters A second-order lowpass loop filter is used to connect the PLL to the RF local oscillator. A loop filter bandwidth of 30kHz is optimal for fractional PLL spurs and integrated LO phase noise. Refer to the EV kit data sheet for the recommended loop-filter component values. Crystal-Oscillator Interface The MAX3580 reference oscillator circuitry can be used either as a high-impedance reference input driven by an external source, or be configured as a crystal oscillator. In the latter case, the resulting frequency can be used to drive the digital demodulator chip through the buffered reference output of the MAX3580. When using an external reference oscillator, drive the XB input through an AC-coupling capacitor with amplitude of approximately 1.5V P-P , and leave XE unconnected. Note that the phase noise of the external reference needs to exceed -140dBc/Hz at offsets of 1kHz to 100kHz. When connecting directly to a crystal, see the Typical Application Circuit for the required topology. For particular capacitor values, possible changes to accommodate for different crystal frequencies, crystal load-capacitance requirements, and crystal power-dissipation requirements, refer to the EV kit data sheet. Gain Control The MAX3580 features two VGA circuits that can be used to achieve the optimum SNR. The two circuits can be driven independently by the baseband controller, which allows balancing the gain based on SNR measurements in the digital demodulator. If only one gain control voltage can be provided by the digital demodulator, see Figure 1. See the Baseband Power Detector section. In this operation mode, the baseband gain is set by an amplitude detector in the digital demodulator. 18 ______________________________________________________________________________________ Direct-Conversion TV Tuner When tuning the MAX3580 to a given Rx frequency, the correct capacitor value has to be calculated using the following linear formulas and written to the appropriate registers. This is in addition to programming the PLL with the desired frequency. The formulas differ for VHF and UHF bands but are the same for all three capacitor values. Since the factory calibration coefficients stored on the MAX3580 can differ for each capacitor, the calculations have to be executed for all three capacitor values separately. VHF: Capacitor = ROM_value_VHF (RX_frequency_in_MHz - 200MHz ) / 10MHz In other words, the capacitor values to be written to the MAX3580 decrease 1 count per 10MHz above 200MHz and increase accordingly below 200MHz. UHF: Capacitor = ROM_value_UHF_lo (ROM_value_UHF_lo - ROM_value_UHF_hi) x (RX_frequency_in_MHz - 470MHz ) / 390MHz This means the capacitor values stored in the UHF_lo entries of the MAX3580 ROM table are the correct values for 470MHz reception and the UHF_hi values for 860MHz reception. For any frequency in between, the capacitor values are obtained by a simple linear interpolation. Note: When tuning to frequencies above 860MHz channel center frequency, do not use the formula above, but rather keep programming the tracking filter with the coefficients obtained for 860MHz. Examples: Assuming the MAX3580 ROM table entries are CSERIES VHF = 8, CSERIES UHF_lo = 15, CSERIES UHF_hi = 3 208MHz: CSERIES = 8 - round ( ( 208-200 ) / 10 ) = 7 (floating point division, round to nearest integer after division) 8 - floor ( ( 208 - 200 + 5) / 10 ) = 7 (all calculations using signed integer values, truncate result of division) 677MHz: CSERIES = 15 - round ( (15-3) x (677 - 470) / 390 ) = 9 (floating point division, round to nearest integer after division) 15 - floor ( ( ( 15-3) x (677-470) + 195 ) / 390 ) = 9 (all calculations using signed integer values, truncate result of division) Power-Supply Layout To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central VCC node. The VCC traces branch out from this node, with each trace going to separate V CC pins of the MAX3580. Next to each VCC pin is a bypass capacitor with a low impedance to ground at the frequency of interest. Use at least one via per bypass capacitor for a low-inductance ground connection. The three ground pins (GND_PLL, GND_CP, GND_TUNE) must be connected to the ground plane by separate via holes and must not be directly connected to the exposed paddle. Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 19 MAX3580 RF Tracking Filter The MAX3580 utilizes two narrowband RF tracking filters, one for VHF and one for UHF. Each filter is comprised of a fixed inductor and three digitally controlled variable capacitors named series, shunt, and parallel capacitors. The integrated RF tracking filters uses an external inductor between IND1 and IND2 pins to set the filter’s center frequency. The inductor value must be 68nH ±2% in order to achieve the corner frequency response. The variable capacitors are factory calibrated to this particular inductor value. The value of each capacitor is also set to compensate for process variation of each individual part and to receive the desired RF channel. The process variation is factory calibrated by determining the best capacitor values for three discrete frequencies, which are stored in the on-chip ROM table. Upon power-up these values (6 bytes total) have to be read out of the MAX3580 ROM table and stored in the microprocessor local memory. MAX3580 Direct-Conversion TV Tuner Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 20 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T3255-5 21-0140 ______________________________________________________________________________________ Direct-Conversion TV Tuner REVISION NUMBER REVISION DATE 0 8/06 Initial release 1 5/07 Various changes 2 8/07 Various changes 2, 5 3 10/07 Various changes 3, 20, 21 4 3/08 Updated AC Electrical Characteristics, corrected Pin Description, added Figure 1, updated Figure references, various other changes 1, 2, 5, 7–13, 15, 17–19 5 8/08 Restricted PLL N-divider range and widened I/Q output DC common mode range 3, 5, 15 6 11/08 Added note to Programmable Registers section to avoid mistuning the VCO during a channel change DESCRIPTION PAGES CHANGED — 1, 4, 5, 20, 21 12 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX3580 Revision History