Cypress CY7C1484V33-167BZC 2m x 36/4m x 18 pipelined dcd sram Datasheet

CY7C1484V33
CY7C1485V33
PRELIMINARY
2M x 36/4M x 18 Pipelined DCD SRAM
Features
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Fast clock speed: 250, 200, and 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast access time: 2.6, 3.0, and 3.4 ns
Optimal for depth expansion
Single 3.3V –5% and +5% power supply VDD
Separate VDDQ for 3.3V or 2.5V
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down for portable applications
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1484V33 and CY7C1485V33).
165-ball FBGA will be offered on an opportunity basis.
(Please contact Cypress sales or marketing)
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control
inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQx) and the data
parity (DPx) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b
and DPa,b apply to CY7C1485V33. a, b, c, and d each are
eight bits wide in the case of DQ and one bit wide in the case
of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPd. BWd controls DQ and DPd. BWa, BWb,
BWc, BWd can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. Write pass-through
capability allows written data available at the output for the
immediately next Read cycle. This device also incorporates
pipelined enable circuit for easy depth expansion without
penalizing system performance.
The CY7C1484V33 and CY7C1485V33 SRAMs integrate
2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
The CY7C1484V33/CY7C1485V33 are both double-cycle
deselect parts.All inputs and outputs of the CY7C1484V33,
CY7C1485V33 are JEDEC standard JESD8-5-compatible.
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Functional Description
Selection Guide
CY7C1484V33250
CY7C1485V33250
CY7C1484V33200
CY7C1485V33200
CY7C1484V33167
CY7C1485V33167
Unit
2.6
3.0
3.4
ns
Maximum Operating Current
TBD
TBD
TBD
mA
Maximum CMOS Standby Current
TBD
TBD
TBD
mA
3901 North First Street
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Maximum Access Time
Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05285 Rev. *A
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San Jose, CA 95134
•
408-943-2600
Revised January 18, 2003
CY7C1484V33
CY7C1485V33
PRELIMINARY
Logic Block Diagram
CY7C1484V33–2M × 36
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
Q
A[20:0]
21
GW
19
DQd, DPd
BYTEWRITE
REGISTERS
DQc, DPc
BYTEWRITE
REGISTERS
Q
D
DQb, DPb
BYTEWRITE
REGISTERS
Q
D
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
BWE
BW d
D
BWc
BWb
BWa
CE1
CE2
CE3
19
ADDRESS
CE REGISTER
D
D
ENABLE CE
REGISTER
21
2M × 36
MEMORY
ARRAY
Q
36
36
Q
D ENABLE DELAY Q
REGISTER
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b,c,d
DPa,b,c,d
CY7C1485V33–4M × 18
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[21:0]
GW
Q
22
BWE
BW b
20
DQb, DPb
BYTEWRITE
REGISTERS
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
ENABLE CE
CE REGISTER
Q
D
D
BWa
CE1
CE2
CE3
ADDRESS
CE REGISTER
D
20
22
4M × 18
MEMORY
ARRAY
Q
18
D ENABLE DELAY Q
REGISTER
OUTPUT
REGISTERS
CLK
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b
DPa,b
Document #: 38-05285 Rev. *A
Page 2 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1485V33
(4M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05285 Rev. *A
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
VSS
VDD
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPb NC
NC
DQb
NC
DQb
VDDQ VDDQ
VSSQ VSSQ
NC
DQb
NC
DQb
DQb DQb
DQb DQb
VSSQ VSSQ
VDDQ VDDQ
DQb DQb
DQb DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa DQb
VDDQ VDDQ
VSSQ VSSQ
DQa DQb
DQa DQb
DQa DPb
NC
DQa
VSSQ VSSQ
VDDQ VDDQ
NC
DQa
NC
DQa
DQPa NC
MODE
A
A
A
A
A1
A0
CY7C1484V33
(2M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
(Top View)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
Page 3 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Pin Configurations (continued)
119-ball Bump BGA
CY7C1484V33 (2M × 36)
1
2
3
4
5
6
7
A
VDDQ
A
ADSP
ADSC
A
A
A
A
VDDQ
C
NC
NC
A
A
A
B
VDD
DQc
DQc
A
DQPc
DQc
A
D
E
VSS
VSS
NC
A
VSS
A
DQPb
CE1
VSS
F
VDDQ
DQc
VSS
DQc
DQc
VDDQ
DQc
DQc
VDD
BWc
VSS
NC
VSS
BWb
VSS
DQb
DQb
G
H
J
OE
ADV
GW
VDD
K
DQd
L
M
DQd
DQd
DQd
VSS
BWd
CLK
NC
BWa
VDDQ
DQd
DQd
DQd
VSS
VSS
BWE
N
A1
P
DQd
DQPd
VSS
R
NC
T
NC
A
A
U
VDDQ
TMS
NC
NC
DQb
DQb
DQb
VDD
VDDQ
DQb
DQb
VDDQ
DQa
DQa
DQa
DQa
VSS
DQa
VSS
DQa
VDDQ
DQa
A0
VSS
DQPa
DQa
MODE
A
VDD
A
NC
A
A
A
NC
ZZ
TDI
TCK
TDO
NC
VDDQ
NC
VSS
DQb
CY7C1485V33 (4M × 18)
1
2
3
4
5
6
7
A
VDDQ
A
ADSP
ADSC
A
A
A
A
VDDQ
NC
NC
A
A
A
B
C
D
E
NC
A
NC
DQb
F
VDDQ
NC
DQb
A
VDD
VSS
VSS
NC
A
VSS
CE1
VSS
VSS
VSS
VSS
VSS
DQb
NC
VDD
DQb
NC
BWb
VSS
NC
OE
ADV
GW
VDD
VSS
VSS
CLK
NC
BWa
DQb
NC
VSS
VSS
BWE
DQb
A1
G
H
J
VDDQ
K
NC
L
M
DQb
VDDQ
N
NC
DQb
NC
DQa
DQa
VDD
VDDQ
DQa
NC
VDDQ
NC
DQa
DQa
NC
VSS
NC
VSS
DQa
VDDQ
NC
NC
DQa
A
A
NC
ZZ
NC
VDDQ
NC
VSS
P
NC
DQPb
VSS
A0
R
NC
A
A
A
MODE
A
VDD
T
A
VSS
NC
A
U
VDDQ
TMS
TDI
TCK
TDO
Document #: 38-05285 Rev. *A
A
DQPa
NC
DQa
NC
NC
NC
Page 4 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Pin Configurations (continued)
165-ball Bump FBGA (This package is offered on an opportunity basis)
CY7C1484V33 (2M × 36)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWc
BWb
CE3
BWE
ADSC
ADV
A
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
DPc
A
NC
CE2
VDDQ
BWd
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
DQd
VSS
DQd
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
DQa
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DPd
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
DPa
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
11
R
CY7C1485V33 (4M × 18)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
A
NC
A
CE1
BWb
NC
CE3
BWE
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
A
NC
CE2
VDDQ
NC
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VSS
NC
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
NC
DQb
DQb
NC
NC
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
NC
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DPb
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
NC
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Pin Definitions
Pin Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
I/O
InputSynchronous
InputSynchronous
InputSynchronous
Document #: 38-05285 Rev. *A
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and
BWE).
Page 5 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Pin Definitions (continued)
Pin Name
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
I/O
InputSynchronous
InputClock
InputSynchronous
InputSynchronous
InputSynchronous
InputAsynchronous
InputSynchronous
InputSynchronous
ADSC
InputSynchronous
MODE
InputStatic
ZZ
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
DQe, DPe
DQf, DPf
DQg, DPg
DQh, DPh
TDO
TDI
TMS
TCK
VDD
VSS
VDDQ
VSSQ
144M
NC
InputAsynchronous
I/OSynchronous
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Test Mode Select
Synchronous
JTAG serial clock
Power Supply
Pin Description
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. (TQFP Only)
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW,
A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW,
A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx
and DPx are placed in a three-state condition.DQ a,b,c,d and h are eight bits wide. DP a,b,c,d
are one bit wide.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only)
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only)
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA Only)
Serial clock to the JTAG circuit. (BGA Only)
Power supply inputs to the core of the device. Should be connected to
3.3 –5%/+5% power supply.
Ground
Ground for the core of the device. Should be connected to ground of the system.
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to VDD(max.)
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
–
NC. This pin is reserved for expansion to 144 Mb.
–
No Connects.
Document #: 38-05285 Rev. *A
Page 6 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Introduction
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
Functional Overview
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1484V33/CY7C1485V33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1484V33 and BWa,b
for CY7C1485V33) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
The CY7C1484V33/CY7C1485V33 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium® and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1484V33
and BWa,b for CY7C1485V33) inputs. A Global Write Enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP/CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
The CY7C1484V33/CY7C1485V33 are double-cycle deselect
parts. Once the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output will
three-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Document #: 38-05285 Rev. *A
Because the CY7C1484V33/CY7C1485V33 is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[x:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1484V33/CY7C1485V33 is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1484V33/CY7C1485V33 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported. Asserting
ADV LOW at clock rise will automatically increment the burst
counter to the next address in the burst sequence. Both read
and write burst operations are supported.
Page 7 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Sleep Mode
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
TBD
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
Cycle Descriptions
[1, 2, 3, 4]
Next Cycle
Add. Used
2tCYC
ns
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
0
Unselected
None
0
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
0
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
0
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
0
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
0
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
0
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
0
1
0
1
0
X
X
Hi-Z
Write
Notes:
1. X = “Don’t Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
Document #: 38-05285 Rev. *A
Page 8 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Cycle Descriptions (continued)[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
0
X
X
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Write Cycle Descriptions[1, 2]
Function (CY7C1484V33)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
0
Write Byte 1 – DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (CY7C1485V33)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0–DQ[7:0] and DP0
1
0
1
0
Write Byte 1–DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Document #: 38-05285 Rev. *A
Page 9 of 29
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1484V33/CY7C1485V33 incorporates a serial
boundary scan Test Access Port (TAP) in the FBGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1–1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-in (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data-out (TDO)
CY7C1484V33
CY7C1485V33
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 70-bit-long
register, and the ×18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
Document #: 38-05285 Rev. *A
Page 10 of 29
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
CY7C1484V33
CY7C1485V33
When the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
Reserved
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05285 Rev. *A
Bypass
Page 11 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
TAP Controller State Diagram
1[5]
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
5. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05285 Rev. *A
Page 12 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
.
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[6, 7]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −4.0 mA
2.4
VOH2
Output HIGH Voltage
IOH = −100 µA
3.0
VOL1
Output LOW Voltage
IOL = 8.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
GND ≤ VI ≤ VDDQ
TAP AC Switching Characteristics Over the Operating Range
Parameters
Description
Max.
Unit
V
V
0.4
V
0.2
V
1.8
VDD + 0.3
V
–0.5
0.8
V
–5
5
µA
[8, 9]
Min.
Max.
100
Unit
tTCYC
TCK Clock Cycle Time
ns
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
10
MHz
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
TMS Hold after TCK Clock Rise
10
ns
Hold Times
tTMSH
Notes:
6. All voltage referenced to ground.
7. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms.
8. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05285 Rev. *A
Page 13 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[8, 9]
Parameters
Description
Min.
Max.
Unit
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
ns
ns
TAP Timing and Test Conditions
1.25V
ALL INPUT PULSES
VIH
50Ω
0V
TDO
Z0 = 50Ω
CL = 20 pF
tTH
(a)
tTL
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
×18
×36
Revision Number (31:29)
Instruction Field
000
000
Reserved for version number
Department Number (27:25)
101
101
Department number
Voltage (28&24)
00
00
Architecture (23:21)
000
000
Architecture type
Memory type (20:18)
110
110
Defines type of memory
Device Width (17:15)
010
100
Defines width of the SRAM. ×36 or ×18
Device Density (14:12)
100
100
Defines the density of the SRAM
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Document #: 38-05285 Rev. *A
Description
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Page 14 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bit Size (×18)
Bit Size (×36)
3
3
Bypass
1
1
ID
32
32
TBD
TBD
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1
preload function and is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 38-05285 Rev. *A
Page 15 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Boundary Scan Order (4M × 18)
Boundary Scan Order (2M × 36)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
TBD
TBD
TBD
TBD
TBD
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TBD
Page 16 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–55°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[10] ............................... –0.5V to VDDQ + 0.5V
DC Input Voltage[10] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temp.[11]
VDD
VDDQ
Com’l
0°C−70°C
3.3V +5% /–5%
2.375V(min.)
VDD(max.)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.465
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
VDD = Min., IOH = –4.0 mA
3.3V
2.4
V
VDD = Min., IOH = –1.0 mA
2.5V
2.0
V
VDD = Min., IOL = 8.0 mA
3.3V
0.4
V
VDD = Min., IOL = 1.0 mA
2.5V
0.4
V
Input HIGH Voltage
Input LOW
Voltage[10]
Input Load Current
3.3V
2.0
V
2.5V
1.7
V
3.3V
–0.3
0.8
V
2.5V
–0.3
0.7
V
GND < VI < VDDQ
Input Current of MODE
5
µA
30
µA
Input Current of ZZ
Input = VSS
30
µA
IOZ
Output Leakage
Current
GND < VI < VDDQ, Output Disabled
5
µA
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
250 MHz
TBD
mA
200 MHz
TBD
mA
167 MHz
TBD
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device
Deselected,
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
250 MHz
TBD
mA
200 MHz
TBD
mA
167 MHz
TBD
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device
Deselected, VIN < 0.3V or VIN
> VDDQ − 0.3V, f = 0
All speed grades
TBD
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device
Deselected, or VIN < 0.3V or
VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
250 MHz
TBD
mA
200 MHz
TBD
mA
167 MHz
TBD
mA
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device
Deselected, VIN > VIH or VIN <
VIL, f = 0
All speed grades
TBD
mA
ISB4
Shaded areas contain advance information.
Notes:
10. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
11. TA is the temperature.
Document #: 38-05285 Rev. *A
Page 17 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Capacitance[12]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 2.5V
Max.
Unit
TBD
pF
TBD
pF
TBD
pF
Thermal Resistance[12]
Parameter
Description
Test Conditions
QJA
Thermal Resistance (Junction to
Ambient)
QJC
Thermal Resistance (Junction to
Case)
BGA Typ.
Still Air, soldered on a 4.25 ×
1.125 inch, four-layer printed
circuit board
TBD
TBD
AC Test Loads and Waveforms[13]
VDDQ
OUTPUT
R = 317Ω
ALL INPUT PULSES
OUTPUT
Z0 = 50Ω
RL = 50Ω
VTH = 1.5V for 3.3V VDDQ
= 1.25V for 2.5V VDDQ
(a)
Vdd
5 pF
INCLUDING
JIG AND
SCOPE
R = 351Ω
90%
10%
90%
10%
[10]
GND
2 V/ns
2 V/ns
(c)
(b)
Switching Characteristics Over the Operating Range
-250
Parameter
Description
Min.
-200
Max.
Min.
-167
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
4.0
5
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.7
2.0
2.4
ns
tCL
Clock LOW
1.7
2.0
2.4
ns
250
6
200
ns
167
MHz
Output Times
tCO
Data Output Valid After CLK Rise
2.6
3.0
3.4
ns
tEOV
OE LOW to Output Valid[ 15, 17]
2.6
3.0
3.4
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High-Z[14, 15, 16, 17]
tCLZ
Clock to
Low-Z[14, 15, 16, 17]
tEOHZ
OE HIGH to Output High-Z[14, 15, 17]
tEOLZ
OE LOW to Output
Low-Z[14, 15, 17]
1.0
1.3
2.6
1.0
1.5
3.0
1.3
2.6
ns
3.4
1.5
3.0
ns
ns
3.4
ns
0
0
0
ns
1.2
1.4
1.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
Shaded areas contain advance information.
Notes:
12. Tested initially and after any design or process changes that may affect these parameters.
13. Input waveform should have a slew rate of 2 V/ns.
14. Unless otherwise noted, test conditions assume signal transition time of 1.5 ns, timing reference levels of 1.5V, input pulse levels of 0 to 3.3V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
15. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05285 Rev. *A
Page 18 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
-250
Parameter
Description
Min.
-200
Max.
Min.
Max.
-167
Min.
Max.
Unit
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.2
1.4
1.5
ns
tWES
BWE, GW, BWx Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Select Set-up
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
BWE, GW, BWx Hold After CLK Rise
0.3
0.4
0.5
ns
tADVH
ADV Hold after CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
Document #: 38-05285 Rev. *A
Page 19 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Switching Waveforms
Write Cycle Timing[4, 18, 19]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
Document #: 38-05285 Rev. *A
Page 20 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[4, 18, 20]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tEOV
tCEH
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
Double-Cycle
Deselect
2b
2c 2c
tCLZ
= DON’T CARE
2d
3a
tCHZ
= UNDEFINED
Note:
20. RDx stands for Read Data from Address X.
Document #: 38-05285 Rev. *A
Page 21 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 18, 19, 20, 21, 22]
Single Read
tCYC
Single Write
Single Write
Burst Read
tCH
Pipelined Read
CLK
tADS
tADH
tCL
ADSP
ADSC
tADVS
ADV
tAS
ADD
tADVH
RD1
WD2
WD3
RD4
RD5
tAH
GW
tWS
tWS
tWH
WE
tCES
tWH
tCEH
Deselect cycle
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tEOV
OE
Data In/Out
tEOHZ
tEOLZ
tCO
1a
1a
Out
2a
In
tDS
4a
Out
3a
In
= DON’T CARE
= UNDEFINED
tDH
tDOH
4b
Out
4c
Out
4d
Out
5a
Out
tCHZ
Notes:
21. Device originally deselected.
22. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05285 Rev. *A
Page 22 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read/Write Timing[4, 18, 19, 20]
ADSP read
ADSC read
Unselected
ADSC write
ADSP write
CLK
ADSP
ADSC
ADV
ADD
RD1
RD2
RD3
RD4
WD5
WD6
5a
In
6a
In
WD8
WD7
GW
WE
CE1
Deselect cycle
CE2
CE3
OE
Data In/Out
1a
1a
Out
2a
Out
3a
Out
= DON’T CARE
Document #: 38-05285 Rev. *A
4a
Out
7a
In
= UNDEFINED
Page 23 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-State
I/Os
tEOLZ
ZZ Mode Timing
[4, 23, 24]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Notes:
23. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
24. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05285 Rev. *A
Page 24 of 29
CY7C1484V33
CY7C1485V33
PRELIMINARY
Ordering Information
Speed
(MHz)
250
200
167
Ordering Code
CY7C1484V33-250AC
CY7C1485V33-250AC
Package
Name
Package Type
Operating
Range
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1484V33-250BGC
CY7C1485V33-250BGC
BG119
CY7C1484V33-250BZC
CY7C1485V33-250BZC
BB165C
CY7C1484V33-200AC
CY7C1485V33-200AC
A101
CY7C1484V33-200BGC
CY7C1485V33-200BGC
BG119
CY7C1484V33-200BZC
CY7C1485V33-200BZC
BB165C
CY7C1484V33-167AC
CY7C1485V33-167AC
A101
CY7C1484V33-167BGC
CY7C1485V33-167BGC
BG119
CY7C1484V33-167BZC
CY7C1485V33-167BZC
BB165C
119-ball BGA (14 × 22 × 2.4 mm)
165-ball BGA (15 × 17 mm)
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 × 22 × 2.4 mm)
165-ball BGA (15 × 17 mm)
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 × 22 × 2.4 mm)
165-ball BGA (15 × 17 mm)
Shaded areas contain advance information.
Document #: 38-05285 Rev. *A
Page 25 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Package Diagrams
100-lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Document #: 38-05285 Rev. *A
Page 26 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Package Diagrams (continued)
165-ball FBGA (15 × 17 × 1.20 mm) BB165C
51-85165-**
Document #: 38-05285 Rev. *A
Page 27 of 29
PRELIMINARY
CY7C1484V33
CY7C1485V33
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in
this document are the trademarks of their respective holders.
Document #: 38-05285 Rev. *A
Page 28 of 29
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1484V33
CY7C1485V33
PRELIMINARY
Document History Page
Document Title: CY7C1484V33/CY7C1485V33 2M x 36/4M x 18 Pipelined DCD SRAM
Document Number: 38-05285
Orig. of
Change
REV.
ECN NO.
Issue Date
**
114672
08/21/02
PKS
New Data Sheet
*A
118285
01/20/03
HGK
Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated Features on package offering
Updated Ordering Information
Changed Advanced Information to Preliminary
Document #: 38-05285 Rev. *A
Description of Change
Page 29 of 29
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