Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
D A T A
S H E E T
EA-224 – 4-Port Fast Ethernet Access Controller
TM
(XpressFlow 2001 Series 10/100 Ethernet Switch Chipset)
1. DISTINCTIVE
CHARACTERISTICS
4 independent 10/100Mbps Ethernet Access Ports
9
Direct interface with 10BaseT transceiver
9
IEEE 802.3u compliant MII (Media Independent Interface) and Serial Management interface
9
Direct interface with 100BaseTX, -T2, -T4, or -TF
physical transceivers
Management BUS
16
LOCAL
BUFFER
MEMORY
State of the art 0.5 micron 3.3Volt CMOS process
32
EA-224
4-Port Ethernet
Access Controller
32
Port
0
352-PIN BGA package
Port
1
Port
2
Port
3
Operating frequency
9
-33
33 MHz maximum
9
-40
40 MHz maximum
9
-50
50 MHz maximum
10/100M BaseTx Xceiver
10/100M BaseTx Ports
32-bit Local Buffer Memory Interface
9
Supports 128k to 1M bytes
9
Utilize high performance 32-bit Synchronous
Burst SRAM
Hardware assisted Buffer and Queue Management
to minimized CPU overhead
16-bit Processor Bus I/O Interface
9
Allows host to access Control Registers & Local
Buffer Memory
9
Supports Big and Little Endian CPUs
9
Direct interface with various different standard
microprocessors including 386, 486 families and
Motorola MPC series embedded processors.
32-bit XpressFlow Bus Interface
9
XpressFlow BUS
Uses Granule for frame transferring between
Access Controllers
Also detects IEEE 802.3X MAC Control frames
9
Store-&-Forward
9
Safe Cut-Thru (Runt Free)
9
Turbo Cut-Thru (10Mbps Mode only)
9
Automatically selects the optimized mode for
forwarding
9
Allows manual frame forwarding mode selection
override
Multi-Media ready with QoS supports
Complies with IEEE 802.1 Bridge Standard
VLAN ID Tagging & Stripping
Automatic retry frame transmission
Supports unicast, multicast, and broadcast frames
9
Three frame forwarding modes
9
9
9
Four frame transmission priority queues
Assigns one unique MAC Address for each port
Auto padding if necessary after stripping
Works together with SC-201 XpressFlow Engine
9
Transmit collision
9
Capable to forward frames at full line-rate
9
Transmit buffer under-run
9
Distributed Flow Caching™ to reduce frame forwarding latency
Automatic receive filtering for bad frames for Store
& Forward Mode
Supports both Half & Full Duplex operation
9
Bad FCS
Programmable Flow Control Enable
9
Short events or frames under 64 bytes
9
Jam Fake Collision for Half Duplex Mode
9 Long events or frames over 1518 bytes
9
Transmit Flow Control Frame for IEEE 802.3x
Full Duplex Mode
© 1997 Zarlink Semiconductor Inc.
Page: 1
Automatic statistic collection for RMON
Rev. 4.0 –December, 1997
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XpressFlow-2001 Series –
Ethernet Switch Chip-set
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EA-224
4-Port 10/100M Ethernet Access Controller
2. GENERAL DESCRIPTION:
The
EA-224
provides
four
10/100Mbps Ethernet network access interface ports. MII interface
is used to connect external PHY
devices for 100 Mbps Ethernet.
They also can direct connect with
standard 10Mbps serial interface.
The EA-224 provides the Ethernet
MAC protocols, handles the local
buffer memory interface and
management, arbitrates among
multiple priority queues, and interfaces with the XpressFlow Engine and other Access Controllers
through the XpressFlow message
passing protocol.
SWITCH BUS
Management BUS
32
EA-224
Local
Buffer
Memory
32
Switch Bus
Interafce
32
Automatic
Buffer
Manager
MAC Interface
32
MAC Port #0 to #3
Port 0
1
2
3
4-Port 100Base-Tx PHY
SC-201 – XpressFlow Engine
EA-208E – 8-port 10Mbps
Ethernet Access Controller
1
Port 0
EA-208 – 6-port 10 + 2-port
10/100 Ethernet Access Controller
EA-222 – 2-port 10/100 Fast
Ethernet Access Controller
2.2 Typical Application:
A 16-port Ethernet Switch with
4 Fast Ethernet Up-Links
2
3
Block Diagram –
EA-224 4-Port Ethernet Access Controller
Address
Mapping
Table
Managem
Bus Interafce
Local
Buffer
Memory
Interface
2.1 Related Components:
16
Buffer
RAM
RS232 Local
Control Console
SC201
XpressFlow
Engine
Switch
Manager
CPU
Flash
ROM
DRAM
Management Bus
XpressFlow Bus
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA224
4-Port
Ethernet
Access
Controller
Four 100M
Fast Ethernet ports
System Block Diagram -16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
© 1997 Zarlink Semiconductor Inc.
Page: 2
Rev. 4.0 –December, 1997
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EA-224
4-Port 10/100M Ethernet Access Controller
XpressFlow-2001 Series –
Ethernet Switch Chip-set
3. PIN ASSIGNMENT
3.1 Logic Symbol
L_D[31:0]
L_A[18:2]
L_BWE[3:0]#
L_WE[3:0]#
L_OE[3:0]#
L_ADSC#
L_CLK
4
4
4
Control Buffer
Memory Interface
EA-224
Test Pin
T_MODE
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
S_HPREQ#
S_REQ#
S_GNT#
S_CLK
© 1997 Zarlink Semiconductor Inc.
4
Port [3:0]
10/100 MII Interface
P_CS#
P_ADS#
P_RWC
P_BS16#
P_RDY#
P_INT
P_RST#
P_CLK
XpressFlow Bus Interface
P_A[11:1]
Management Bus
Interface
P_D[15:0]
MII Mode
Mm_RXD[3:0] Tm_RXD
Mm_RXDV
Mm_RXC
Tm_RXC
Mm_RXER
Mm_TXER
Mm_TXC
Mm_TXEN
Mm_TXD[0]
Mm_TXD[1]
Mm_TXD[2]
Mm_TXD[3]
Mm_COL
Mm_CRS
Mm_LNK
MII Serial
Managem't
Page: 3
10BaseT
Serial Xface
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
M_MDC
M_MDIO
Rev. 4.0 –December, 1997
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XpressFlow-2001 Series –
Ethernet Switch Chip-set
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EA-224
4-Port 10/100M Ethernet Access Controller
3.2 Pin Assignment (Preliminary)
Note:
#
Input
I-ST
Output
Out-OD
I/O-TS
I/O-OD
5VT
?
@
A
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Pin No(s).
Symbol
Management Bus Interface
P_D[15:0]
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26,
P25
C26,D24,C25,E24,D26, P_A[11:1]
D25,F24,E26,E25,G24,
F26
F25
P_ADS#
H25
P_RWC
J24
P_RDY#
G25
P_BS16#
G26
P_CS#
H26
P_INT
J26
P_RST#
K24
P_CLK
XpressFlow Bus Interface
C23,A23,B22,C22,A22 S_D[31:27] /
P_C[0:4]
Type
TTL I/O-TS
(5VT)
?
Max
IOL / IOH Name & Functions
16mA
Management Bus – Data Bit [15:0]
TTL In (5VT)
Management Bus – Address Bit [11:1]
TTL In (5VT)
TTL In (5VT)
TTL Out-OD
TTL Out-OD
TTL In (5VT)
CMOS Output
Management Bus – Address Strobe
Management Bus – Read/Write Control
Management Bus – Data Ready
Management Bus – 16 bit Data Bus
Management Bus – Chip Select
Management Bus – Interrupt Request
16mA
16mA
4mA
TTL In-ST
(5VT)
TTL In (5VT)
Management Bus – Master Reset
CMOS I/O-TS
Management Bus – Bus Clock
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
B12
A12
C14
C13
B23
A24
S_D[26:0]
CMOS I/O-TS
12 mA XpressFlow Bus – Data Bit [31:27] or
Management Bus Interface Configuration
bit [0:4]
12mA XpressFlow Bus – Data Bit [26:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Output
12 mA
12mA
12 mA
12 mA
12mA
4mA
B24
A13
D13
S_GNT#
S_OVLD#
S_CLK
CMOS Input
CMOS Input
CMOS Input
© 1997 Zarlink Semiconductor Inc.
Page: 4
XpressFlow Bus – Message Envelope
XpressFlow Bus – End of Frame
XpressFlow Bus – Initiator Ready
XpressFlow Bus – Target Abort
XpressFlow Bus – High Priority Request
XpressFlow Bus – Bus Request to
SC201
XpressFlow Bus – Bus Grant from SC201
XpressFlow Bus – Bus Overload
XpressFlow Bus – Clock
Rev. 4.0 –December, 1997
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XpressFlow-2001 Series –
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Pin No(s).
A
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D A
Symbol
L_ADSC#
L_CLK
Fast Ethernet Access Port [3:0]
T24
M_MDC
AB2,U25,AE26,AF5
AB1,V24,AD25,AE6
AA3,U26,AD26,AD6
AC2,T25
AC25,AF6
Y3,V26,AF24,AD5
AC1,U24
E
T
Local Memory Bus – Data Bit [31:0]
8mA
Local Memory Bus – Address Bit [17:2]
8mA
Local Memory Bus – Address Bit [19] or
Memory Read Chip Select [3]
Local Memory Read Chip Select [2:0]
Local Memory Write Chip Select [3:0]
Local Memory Byte Write Enable, Byte
[3:0]
Local Memory Controller Address Status
Local Memory Clock input
2mA
2mA
8mA
8mA
8mA
CMOS Output
4mA
TTL IO-TS
(5VT)
M[3:0]_RXD[3] TTL In (5VT)
M[3:0]_RXD[2] TTL In (5VT)
4mA
@
@
M[3:0]_RXD[1] TTL In (5VT) @
M[3:2]_RXD[0] TTL In (5VT) @
M[1:0]_RXD[0] TTL In (5VT)
M[3:0]_RXDV TTL In (5VT) @
M[3:2]_RXC
TTL In (5VT) @
AC24,AE7
AA1,V25,AD23,AE5
AA2,W24,AE24,AF4
W2,AA25,AE22,AD1
W1,AA24,AF22,AF2
V3,AA26,AD21,AE3
Y2,Y26,AE23,AF3
W3,W26,AD22,AD4
Y1,W25,AF23,AE4
V1,AB26
M[1:0]_RXC
M[3:0]_RXER
M[3:0]_TXER
M[3:0]_TXC
M[3:0]_TXEN
M[3:0]_TXD[3]
M[3:0]_TXD[2]
M[3:0]_TXD[1]
M[3:0]_TXD[0]
M[3:2]_COL
AD20,AC3
U3,AB24
M[1:0]_COL
M[3:2]_CRS
AF21,AD2
V2,AB25
M[1:0]_CRS
M[3:2]_LNK
AE21,AB3
M[1:0]_LNK
Test Facility
A25
T_MODE
© 1997 Zarlink Semiconductor Inc.
H E
8mA
CMOS Output
CMOS Output
M_MDIO
N1,M3,P2,P1,N3,R2,P3, T_D[15:10]
R1,T2,R3,T1,R4,U2,T3,
U1,U4
S
Max
IOL / IOH Name & Functions
Type
@
R26
A
EA-224
4-Port 10/100M Ethernet Access Controller
Control Buffer Memory Interface
M4,N2,L3,M1,M2,L1,K3, L_D[31:0]
TTL I/O-TS
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,
F3,F2,E1,E3,E2,D1,D3,
D2,C1,C2,B1
CMOS Output
A6,B6,C8,A7,D8,D7,C9, L_A[18:2]
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11
C7
L_A[19] /
CMOS Output
L_OE[3]#
D5,A5,A3
L_OE[2:0]#
CMOS Output
D7,E4,B5,C4
L_WE[3:0]#
CMOS Output
C6,B4,A4,C5
L_BWE[3:0]# CMOS Output
B3
G4
T
?
?
MII Management Data Clock – (common
for all MII Ports – Port [1:0])
MII Management Data I/O – (common for
all MII Ports – Port [1:0]))
Port [3:0] – MII Receive Data Bit [3]
Port [3:0] -- Receive Data Bit [2]
Port [3:0] -- Receive Data Bit [1]
Port [3:0] -- Receive Data Bit [0]
Port [3:0] -- Receive Data Valid
Port [3:0] -- Receive Clock
TTL In (5VT)
CMOS Output
TTL In (5VT)
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
@
@
@
4mA
4mA
4mA
4mA
4mA
4mA
Port [3:0] -- Carrier Sense
Port [3:0] -- Link Status
CMOS I/O-TS
2mA
A CMOS Output
4mA
@
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Port [3:0] -- Receive Error
Port [3:0] -- Transmit Error
Port [3:0] -- Transmit Clock
Port [3:0] -- Transmit Enable
Port [3:0] -- Transmit Data Bit [3]
Port [3:0] -- Transmit Data Bit [2]
Port [3:0] -- Transmit Data Bit [1]
Port [3:0] -- Transmit Data Bit [0]
Port [3:0] -- Collision Detected
Test Pin – Set Test Mode upon Reset,
and provides test status output during
test mode
Test Pins – Reserved for internal use
only
Rev. 4.0 –December, 1997
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XpressFlow-2001 Series –
Ethernet Switch Chip-set
Pin No(s).
Symbol
Power Pins
VDD
D6,D11,D16,D21,F4,
F23,L4,L23,T4,T23,AA4,
AA23,AC6,AC11,AC16,
AC21
A1,A2,A26,B2,B25,B26, VSS
C3,C24,D4,D9,D14,D19,
D23,H4,J23,N4,P23,V4,
W23,AC4,AC8,AC13,
AC18,AC23,AD3,AD24,
AE1,AE2,AE25,AF1,
AF25
© 1997 Zarlink Semiconductor Inc.
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EA-224
4-Port 10/100M Ethernet Access Controller
Type
Name & Functions
Power
+3.3 Volt DC Supply
Power
Ground
Page: 6
Rev. 4.0 –December, 1997
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EA-224
4-Port 10/100M Ethernet Access Controller
XpressFlow-2001 Series –
Ethernet Switch Chip-set
3.3 Pin Reference Table: (352 pin BGA)
Pin #
F26
G24
E25
E26
F24
D25
D26
E24
C25
D24
C26
F25
G26
H25
G25
J24
J26
H26
K24
P25
P26
R24
N25
N26
P24
M25
N24
M26
L25
M24
L26
K25
L24
K26
J25
D13
A13
B23
A24
B24
B12
A12
C14
C13
B13
C15
A14
D15
B14
C16
A15
B15
A16
C17
B16
Signal Name Pin #
P_A[1]
D17
P_A[2]
A17
P_A[3]
C18
P_A[4]
B17
P_A[5]
A18
P_A[6]
B18
P_A[7]
C19
P_A[8]
A19
P_A[9]
B19
P_A[10]
C20
P_A[11]
A20
P_ADS#
B20
P_CS#
A21
P_RWC
C21
P_BS16#
D20
P_RDY#
B21
P_RST#
A22
C22
P_INT
P_CLK
B22
P_D[0]
A23
P_D[1]
C23
P_D[2]
P_D[3]
A11
P_D[4]
B10
P_D[5]
C11
P_D[6]
A10
P_D[7]
D10
P_D[8]
B9
P_D[9]
C10
P_D[10]
A9
P_D[11]
B8
P_D[12]
A8
P_D[13]
C9
P_D[14]
B7
P_D[15]
D8
A7
S_CLK
C8
S_OVLD#
B6
S_HPREQ#
A6
S_REQ#
C7
S_GNT#
D5
S_MSGEN#
A5
S_EOF#
A3
S_IRDY
D7
S_TABT#
E4
S_D[0]
B5
S_D[1]
C4
S_D[2]
C6
S_D[3]
B4
S_D[4]
A4
S_D[5]
C5
S_D[6]
B3
S_D[7]
G4
S_D[8]
B1
S_D[9]
C2
S_D[10]
C1
?
Note:
Signal Name
S_D[11]
S_D[12]
S_D[13]
S_D[14]
S_D[15]
S_D[16]
S_D[17]
S_D[18]
S_D[19]
S_D[20]
S_D[21]
S_D[22]
S_D[23]
S_D[24]
S_D[25]
S_D[26]
S_D[27] / P_C[4]
S_D[28] / P_C[3]
S_D[29] / P_C[2]
S_D[30] / P_C[1]
S_D[31] / P_C[0]
L_A[2]
L_A[3]
L_A[4]
L_A[5]
L_A[6]
L_A[7]
L_A[8]
L_A[9]
L_A[10]
L_A[11]
L_A[12]
L_A[13]
L_A[14]
L_A[15]
L_A[16]
L_A[17]
L_A[18]
L_A[19] / OE[3]#
L_OE[2]#
L_OE[1]#
L_OE[0]
L_WE[3]#
L_WE[2]#
L_WE[1]#
L_WE[0]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
L_CLK
L_D[0]
L_D[1]
L_D[2]
@
@
@
Pin #
D2
D3
D1
E2
E3
E1
F2
F3
F1
G2
G1
G3
H2
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
L1
M2
M1
L3
N2
M4
Signal Name
L_D[3]
L_D[4]
L_D[5]
L_D[6]
L_D[7]
L_D[8]
L_D[9]
L_D[10]
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
L_D[16]
L_D[17]
L_D[18]
L_D[19]
L_D[20]
L_D[21]
L_D[22]
L_D[23]
L_D[24]
L_D[25]
L_D[26]
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
T24
R26
M_MDC
M_MDIO
AB3
AD2
AC3
AE3
AF3
AD4
AE4
AF2
AD1
AF4
AE5
AE7
AD5
AF6
AD6
AE6
AF5
AE21
AF21
AD20
AD21
AE23
AD22
M0_LNK / T0_LNK
M0_CRS / T0_CRS
M0_COL / T0_COL
M0_TXD[3] / T0_FD
M0_TXD[2] / T0_LPBK
M0_TXD[1]
M0_TXD[0] / T0_TXD
M0_TXEN / T0_TXEN
M0_TXC / T0_TXC
M0_TXER
M0_RXER
M0_RXC / T0_RXC
M0_RXDV
M0_RXD[0] / T0_RXD
M0_RXD[1]
M0_RXD[2]
M0_RXD[3]
M1_LNK / T1_LNK
M1_CRS / T1_CRS
M1_COL / T1_COL
M1_TXD[3] / T1_FD
M1_TXD[2] / T1_LPBK
M1_TXD[1]
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
?
?
?
@
@
@
@
@
?
?
?
Pin #
AF23
AF22
AE22
AE24
AD23
AC24
AF24
AC25
AD26
AD25
AE26
AB25
AB24
AB26
AA26
Y26
W26
W25
AA24
AA25
W24
V25
U24
V26
T25
U26
V24
U25
V2
U3
V1
V3
Y2
W3
Y1
W1
W2
AA2
AA1
AC1
Y3
AC2
AA3
AB1
AB2
Signal Name
M1_TXD[0] / T1_TXD
M1_TXEN / T1_TXEN
M1_TXC / T1_TXC
M1_TXER
M1_RXER
M1_RXC / T1_RXC
M1_RXDV
M1_RXD[0] / T1_RXD
M1_RXD[1]
M1_RXD[2]
M1_RXD[3]
M2_LNK / T2_LNK
M2_CRS / T2_CRS
M2_COL / T2_COL
M2_TXD[3] / T2_FD
M2_TXD[2] / T2_LPBK
M2_TXD[1]
M2_TXD[0] / T2_TXD
M2_TXEN / T2_TXEN
M2_TXC / T2_TXC
M2_TXER
M2_RXER
M2_RXC / T2_RXC
M2_RXDV
M2_RXD[0] / T2_RXD
M2_RXD[1]
M2_RXD[2]
M2_RXD[3]
M3_LNK / T3_LNK
M3_CRS / T3_CRS
M3_COL / T3_COL
M3_TXD[3] / T3_FD
M3_TXD[2] / T3_LPBK
M3_TXD[1]
M3_TXD[0] / T3_TXD
M3_TXEN / T3_TXEN
M3_TXC / T3_TXC
M3_TXER
M3_RXER
M3_RXC / T3_RXC
M3_RXDV
M3_RXD[0] / T3_RXD
M3_RXD[1]
M3_RXD[2]
M3_RXD[3]
A25
T_MODE
U4
U1
T3
U2
R4
T1
R3
T2
T_D[0]
T_D[1]
T_D[2]
T_D[3]
T_D[4]
T_D[5]
T_D[6]
T_D[7]
@
@
@
@
@
?@
@
@
?@
?@
@
@
@
@
?@
@
@
?@
?@
@
@
@
@
@
A
A
A
A
A
A
A
A
Signal Name
Pin #
R1
P3
R2
N3
P1
P2
M3
N1
T_D[8]
T_D[9]
T_D[10]
T_D[11]
T_D[12]
T_D[13]
T_D[14]
T_D[15]
D6
D11
D16
D21
F4
F23
L4
L23
T4
T23
AA4
AA23
AC6
AC11
AC16
AC21
A1
A2
A26
B2
B25
B26
C3
C24
D4
D9
D14
D19
D23
H4
J23
N4
P23
V4
W23
AC4
AC8
AC13
AC18
AC23
AD3
AD24
AE1
AE2
AE25
AF1
AF25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
? Output signals with programmable polarity.
@ Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
A These pins are reserved for internal use only. They should be left unconnected.
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4-Port 10/100M Ethernet Access Controller
4. FUNCTIONAL DESCRIPTION
4.1 Local Memory (Local Buffer Memory) Interface
Use industry standard Synchronous Burst Mode SRAM up to 1M bytes
9 32k x 32, 64k x 32, 128k x 32, or 256k x 32
Provides 4 individual Byte Write Enable controls ( L_BWE[3:0]# )
Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip
Supports back to back Read or Write operations across memory chips
4.1.1 Pin Description
Symbol
L_D[31:0]
L_A[19] /
L_OE[3]#
L_OE[2:0]#
L_WE[3:0]#
L_BWE[3:0]#
L_CLK
Note:
Name & Functions
TTL
Local Memory Data Bus Bit [31:0] – a 32-bit synchronous data bus.
@ I/O-TS
L_A[18:2]
L_ADSC#
Type
CMOS Local Memory Address Bus Bit [18:2] – Bit [18:2] of a synchronous
Output address bus. The memory address is sampled when L_CS# is enabled
and L_ADSC# is asserted.
CMOS Local Memory Address Bus Bit [19] or Local Memory Read Chip
Output Select [3] – Depends on memory configuration, this pin can be used as
the Local Memory Address Bit [19] or as the Local Memory Read Chip
Select [3].
CMOS Local Memory Read Chip Select [2:0] – allows up to read one of the 4
Output banks of memory.
CMOS Local Memory Write Chip Select [3:0] – allows up to write one of the 4
Output banks of memory.
CMOS Local Memory Byte Write Enable [3:0] – use to write individual bytes.
Output
CMOS Local Memory Controller Address Status – to load a new address.
Output
CMOS Local Memory Clock – a synchronous clock to memory devices.
Output
@ These pins have weak internal pull up resistors (50k to 100k Ohms each).
© 1997 Zarlink Semiconductor Inc.
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4-Port 10/100M Ethernet Access Controller
XpressFlow-2001 Series –
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4.1.2 Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3
Chip #2
Chip #1
Chip #0
L_A[19] /
RAM Chip # of RAM Total Buffer
L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]#
L_OE[3]#
Size
Chips Memory Size
32k x 32
64k x 32
128k x32
256k x32
1
128k bytes
----
----
----
----
2
256k bytes
----
----
----
----
4
512k bytes
1
256k bytes
2
512k bytes
4
1M bytes
1
512k bytes
----
----
----
----
2
1M bytes
----
----
----
----
1
1M bytes
----
L_A[19]
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
4.1.3 Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
L_D[31:0] (Wr)
D1
D3
L_D[31:0] (Rd)
D3+1
D3+2
D3+3
D2
D6
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
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4.2 Management Bus Interface
Supports various industry standard microprocessors including:
S
H E
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T
9 Motorola MPC series embedded processors
Easily adapts to other industry standard CPUs
Provides separate Address and Data bus
Supports Big & Little Endian byte ordering
Supports 16-bit Data Bus
Supports early RDY cycle
9 Meets timing requirement for Intel/AMD
186 family processors
9 Intel 186, 386, and 486 family or equivalent
A
EA-224
4-Port 10/100M Ethernet Access Controller
XpressFlow-2001 Series –
Ethernet Switch Chip-set
T
Supports 1X or 2X CPU Clock
9 2X CPU Clock for 386 family processors
Provides a single interrupt signal to Switch
Manager CPU
4.2.1 Pin Description
Symbol
P_C[4:0]
Type
Name & Functions
CMOS Input Processor Configuration bit [4:0]: – During the Reset Cycle, the
P_C[4:0] pins provides the processor configuration. By using external
weak pull-up or -down resistors, they define the External Management
Bus Interface Configuration. These inputs are sampled at the trailing
edge of the Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU
Bus interface, and the setting of this bit is ignored.
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid.
If C[4] is High, the P_D[15:0] are valid along in the same clock period
as P_RDY is asserted. If C[4] is Low, the P_RDY is asserted one
clock period early ahead of the P_D[15:0] are valid.
Lo
Hi
C[0]
CPU Clock
C[1]
Byte Order
C[2]
RWC
C[3]
Bus Size
C[4]
RDY Timing
1X Clock
2x Clock
Little Endian
Big Endian
P_R/W#
P_W/R#
n/a
n/a
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
P_A[11:1] TTL In (5VT) Address Bus Bit [11:1] – I/O port address
P_D[15:0] TTL I/O-TS Data Bus Bit [15:0] – a 16-bit synchronous data bus.
(5VT)
P_ADS# TTL In (5VT) Address Strobe – indicates valid address is on the bus
P_RWC TTL Input
Read/Write Control – indicates the current bus cycle is a read or write
(5VT)
cycle. C[1] defines the polarity of this signal during the Reset cycle.
C[1]=0
C[1]=1
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
P_RDY# TTL Out-OD Data Ready – timing indicates for bus data valid
P_BS16# TTL Out-OD Bus Size 16 – response to bus master that the EA208 only supports 16bit data bus width.
P_CS#
TTL Input
Chip Select – indicates the XpressFlow Engine is the target for the cur(5VT)
rent bus operation.
P_INT ? CMOS Out- Interrupt Request to Switch Manager CPU The polarity of this signal
put
output is programmable via chip configuration register.
P_RST# TTL In-ST
CPU Reset – Synchronous reset Input from Switch Manager CPU
(5VT)
P_CLK
TTL In (5VT) CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
© 1997 Zarlink Semiconductor Inc.
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4.2.2 Motorola MPC801 Processor Interface
P_CLK
{CLKOUT}
P_ADS#
{TS#}
P_A[11:1]
{A[20:30]}
P_CS#
P_RWC
{RD/WR#}
P_RDY#
{TA#}
P_D[15:0]
{D[0:15]} (in)
P_D[15:0]
{D[0:15]} (out)
Note: Mnemonics with in {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations
4.2.3 Intel 486 Processor Interface
P_CLK
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D[15:0] (out)
Typical 486 CPU I/O Access Operations
© 1997 Zarlink Semiconductor Inc.
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4.2.4 Intel 386 Processor Interface
P_CLK
PH2 (internal)
PH2
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal)
PH2
PH1
PH2
PH2 or PH1
P_RST#
Internal PH2 Clock Synchronization **
Note: ** See Intel 386 Processor Data Book for more details
© 1997 Zarlink Semiconductor Inc.
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4-Port 10/100M Ethernet Access Controller
4.2.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
? This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation.
@ These registers are reserved for system diagnostic usage only.
I/O Offset
Register Description
Device Configuration Registers (DCR)
GCR
Global Control Register
DCR0
DCR1
DCR2
DCR3
DCR4
DTSR
Device Status Register
Signature & Revision Register
ID Register
Device Configuration Register
Interfaces Status Register
Test Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
ISRM
Interrupt Status Register – Masked
IMSK
Interrupt Mask Register
IAR
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR Memory Write Address Reg. – Single Cycle
MRAR
Memory Read Address Reg. – Single Cycle
MBAR
Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
MRBS
Memory Read Burst Size (in D-words)
MWDR Memory Write Data Register
MWDX Memory Write Data Reg. – Byte Swapping
MRDR Memory Read Data Register
MRDX
Memory Read Data Reg. – Byte Swapping
FCB Buffer & Stack Management
FCBBA Frame Control Buffer – Base Address
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSL
FCBST
FCBSS
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
© 1997 Zarlink Semiconductor Inc.
Page: 13
Reg.
Little
Big
Endian Endian
Size
hF00
hF02
hF00
hF10
hF20
hF30
hF40
hF70
W/R
Note:
16-bit
W/--
?
hF02
hF12
hF22
hF32
hF42
hF72
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/R
--/R
W/R
hF80
hF90
hFA0
hFB0
hF82
hF92
hFA2
hFB2
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/--
hE08
hE18
hE28
hE40
hE50
hE68
hE6C
hE68
hE6C
hE08
hE18
hE28
hE42
hE52
hE68
hE6C
hE68
hE6C
32-bit
32-bit
32-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
W/R
W/R
W/R
W/R
W/R
W/-W/---/R
--/R
hD00
hD30
hD02
hD32
16-bit
16-bit
W/R
--/R
hD90
hDA0
hDB0
hD92
hDA2
hDB2
16-bit
16-bit
16-bit
W/R
W/R
--/R
@
@
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I/O Offset
Register Description
Access Control Function (Chip Level controls)
AVXR
VLAN Control Table (VCT) Index Register
AVDR
VCT Data Register
AVTC
VLAN Type Code
AXSC
Transmission Scheduling Control Register
AMIIC
MII Command Register
AMIIS
MII Status Register
AFCR
Flow Control Register
AMAR0 Multicast Address. for MAC Control Frames
Byte [1,0]
AMAR1
Byte [3,2]
AMAR2
Byte [5,4]
AMCT
MAC Control FrameType Code Register
ADAR0 Base MAC Address Register – Byte [1,0]
ADAR1 Base MAC Address Register – Byte [3,2]
ADAR2 Base MAC Address Register – Byte [5,4]
Reg.
Little
Big
Endian Endian
Size
hC00
hC10
hC20
hC30
hC40
hC40
hC70
hC80
hC02
hC12
hC22
hC32
hC40
hC40
hC72
hC82
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
16-bit
16-bit
W/-W/R
W/R
W/R
W/---/R
W/R
W/R
hC90
hCA0
hCB0
hCC0
hCD0
hCE0
hC92
hCA2
hCB2
hCC2
hCD2
hCE2
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Ethernet MAC Port Control Registers – (substitute [n] with Port Number, n = {0..3] )
ECR0
MAC Port Control Register
hn00 hn02 16-bit W/R
ECR1
MAC Port Configuration Register
hn10 hn12 16-bit W/R
ECR2
MAC Port Interrupt Mask Register
hn20 hn22 16-bit W/R
ECR3
MAC Port Interrupt Status Register
hn30 hn32 16-bit
--/R
EXSR
MAC Tx Status Register
hn40 hn42 16-bit
--/R
EXEC
MAC Tx Error Counters
hn50 hn52 16-bit
--/R
ERSR
MAC Rx Status Register
hn68 hn68 32-bit
--/R
EREC
MAC Rx Error Counters
hn78 hn78 32-bit
--/R
© 1997 Zarlink Semiconductor Inc.
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Note:
@
@
@
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4.3 XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architecture
9 High priority for Data Messages
Provides up to 1.6G bps switching bandwidth
9 -33
1.07G bps
9 -40
1.28G bps
9 -50
1.60G bps
Two level bus request priorities
z
for forwarding an Ethernet frame from
receiving port to transmission port
9 Low priority for Command Messages
z
Full multi bus master structure
for passing control information between
devices
Allows Access Controllers to communicate
with XpressFlow Engine and other Access
Controllers via a message passing protocol
4.3.1 Pin Description
Symbol
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
Type
Name & Functions
CMOS Data Bus Bit [31:0] – a 32-bit synchronous data bus.
I/O-TS
Note: During the system RESET period, Data Bit [31:27] are used
as Processor Interface Configuration bit [0:3]
CMOS Message Envelope – encompasses the entire period of a message
I/O-TS transfer. Targets use the leading edge of this signal to detect the beginning of a message transfer, and to decode the message header for
the intended target(s).
CMOS End of Frame – only used by frame data transfer messages to identify
I/O-TS the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
CMOS Initiator Ready – a normal true signal. When negated, it indicates the
I/O-TS initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
CMOS Target Abort – when asserted, the target had aborted the reception of
I/O-OD current message on the bus.
CMOS High Priority Request – indicates one or more Bus Requester is reI/O-OD questing for high priority message transfer.
CMOS Bus Request – Bus Request signal from Access Controller to Bus AcOutput cess Arbitrator in XpressFlow Engine
CMOS Bus Grant – Bus Grant signal from Bus Arbitrator to Bus Requester
Input
CMOS Bus Over-load – when asserted, all data forwarding bus bandwidth has
Input been allocated. Cannot support additional load for data forwarding traffic.
CMOS XpressFlow Bus Clock – up to 50MHz system clock
Input
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4.3.2 Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1
EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]#
S_HPREQ#
High Priority Request pre-empts the low priority request.
© 1997 Zarlink Semiconductor Inc.
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XpressFlow-2001 Series –
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S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Bus Overload pre-empts the data transfer request
© 1997 Zarlink Semiconductor Inc.
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4-Port 10/100M Ethernet Access Controller
4.4 MII Interface
Fully compliant with IEEE 802.3u Media Independent Interface for connecting with external
10/100M Ethernet Physical Layer Transceiver
All ports can also support 10Mbps Serial Interface
9 If 10Mbps Serial Interface is used, the MII
port pin assignment are re-mapped for
10Mbps Serial Interface.
Supports both 10Mbps 10BaseT interface and
100Mbps 100BaseTx interface
Supports both half and full duplex operation
Shared Station Management interface (one for
all MII channels with in the Access Controller)
4.4.1 Pin Description
Symbol
Type
Name & Functions
M_MDC
CMOS MII Management Data Clock – (common for all MII Ports) used to synOutput chronize the MII data stream (MDIO) for transferring between the Access Controller and the MII Tranceivers.
M_MDIO
TTL MII Management Data I/O – (common for all MII Ports) a serial manIO-TS agement data stream synchronous with MDC.
(5VT)
TTL
In Receive Data [3:0] – (one set for each MII Port) a four-bit transmit data
Mm_RXD[3:0]
(5VT) nibble. Bit 0 is the least significant bit, and bit 3 is the most significant
bit.
Mm_RXDV
TTL In Receive Data Valid – (one for each MII Port) instructs the MAC to be(5VT) gin moving data nibbles from the receive data lines.
Mm_RXC
TTL In Receive Clock – (one for each MII Port) a 25MHz clock input with 35%
(5VT) to 65% duty cycles.
Mm_RXER
TTL In Receive Error – (one for each MII Port)
(5VT)
Mm_TXER
CMOS Transmit Error – (one for each MII Port)
Output
Mm_TXC
TTL In Transmit Clock – (one for each MII Port) a continuous clock input with
(5VT) 35% to 65% duty cycles.
Mm_TXEN
CMOS Transmit Enable – (one for each MII Port) instructs the transceiver to
Output begin moving data nibbles on the transmit data lines.
Mm_TXD[3:0] CMOS Transmit Data [3:0] – (one set for each MII Port) a four-bit transmit
Output data nibble. Bit 0 is the least significant bit, and bit 3 is the most significant bit.
Mm_COL
TTL In Collision Detected – (one for each MII Port)
(5VT)
Mm_CRS
TTL In Carrier Sense – (one for each MII Port)
(5VT)
Mm_LNK
TTL In Link Status – (one for each MII Port)
? (5VT) The polarity of this signal is programmable via Port Configuration Register
Note:
“m” is the port number [3:0].
? These signals have programmable output polarity.
© 1997 Zarlink Semiconductor Inc.
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XpressFlow-2001 Series –
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TXC
A
40 nsec
TXEN
TXD[3:0]
100M MII Transmit Timing
40 nsec
RXC
RXDV
RXD[3:0]
SFD
SFD
Data
100M MII Receive Timing
© 1997 Zarlink Semiconductor Inc.
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4.4.2 PIN Mapping between MII Interface and 10Mbps Serial Interface
MII Interface
Symbol
Type
10Mbps Serial Interface
Symbol
Mm_RXD[3:1] TTL In
(5VT)
Mm_RXD[0]
TTL In Tm_RXD
(5VT)
Mm_RXDV
TTL In
(5VT)
Mm_RXC
TTL In Tm_RXC
(5VT)
Mm_RXER
TTL In
(5VT)
Mm_TXER
CMOS
Output
Mm_TXC
TTL In Tm_TXC
(5VT)
Mm_TXEN
Mm_TXD[0]
Mm_TXD[1]
Mm_TXD[2]
Mm_TXD[3]
Mm_COL
Mm_CRS
Mm_LNK
Note:
?
Type
Name & Functions
Not used by Serial Interface Ports. Has a weak
internal pull-up resistor.
TTL In Receive Data – (one for each Serial Interface
(5VT) Port) a receive data stream.
Not used by Serial Interface Ports. Has a weak
internal pull-up resistor.
TTL In Receive Clock – (one for each Serial Interface
(5VT) Port)
Not used by Serial Interface Ports. Has a weak
internal pull-up resistor.
Not used by Serial Interface Ports.
TTL In Transmit Clock – (one for each Serial Inter(5VT) face Port) a continuous clock input with 35% to
65% duty cycles.
CMOS Transmit Enable – (one for each Serial InterOutput face Port)
CMOS Transmit Data – (one for each Serial Interface
Output Port) a transmit data stream.
Not used by Serial Interface Ports
CMOS Tm_TXEN
Output
CMOS Tm_TXD
Output
CMOS
Output
CMOS Tm_LPBK ? CMOS Loop Back Enable – (one for each Serial InOutput
Output terface Port) The polarity of this signal is programmable via Port Configuration Register
CMOS Tm_FD
? CMOS Full Duplex Mode – (one for each Serial InOutput
Output terface Port) The polarity of this signal is programmable via Port Configuration Register
TTL In Tm_COL
TTL In Collision Detected – (one for each Serial In(5VT)
(5VT) terface Port)
TTL In Tm_CRS
TTL In Carrier Sense – (one for each Serial Interface
(5VT)
(5VT) Port)
TTL In Tm_LNK ? TTL In Link Status – (one for each Port) The polarity
(5VT)
(5VT) of this signal is programmable via Port Configuration Register
“m” is the port number [3:0].
? These signals have programmable output polarity.
4.5 Test Facility
Symbol
T_MODE
Type
Name & Functions
CMOS Test Mode Selection & Test Output – Set Test Mode upon Reset, and
I/O TS provides test status output during test mode
© 1997 Zarlink Semiconductor Inc.
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5. DC SPECIFICATION
5.1 ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
-65°C to +150°C
0°C to +70°C
Supply Voltage VDD with Respect to VSS
Voltage on 5V Tolerant Input Pins
Voltage on Other Pins
+3.0 V to +3.6 V
-0.5 V to (VDD + 2.5 V)
-0.5 V to (VDD + 0.5 V)
Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
5.2 DC CHARACTERISTICS
VDD = +3.0 V to +3.6 V
TAMBIENT = 0°C to +70°C
Preliminary
Symbol
fosc
IDD
VOH-CMOS
VOL-CMOS
VOH-TTL
VOL-TTL
VIH-CMOS
VIL-CMOS
VIH-TTL
VIL-TTL
VIH-5VT
VIL-5VT
ILI
ILO
IIH
IIL
CIN
COUT
CI/O
Parameter Description
Min
Frequency of Operation ( -33)
Frequency of Operation ( -40)
Frequency of Operation (-50)
Supply Power – @ 33.3333 MHz (VDD =3.3 V)
Supply Power – @ 40 MHz (VDD =3.3 V)
Supply Power – @ 50 MHz (VDD =3.3 V)
Output High Voltage (CMOS) IOH = maximum
Output Low Voltage (CMOS) IOL = maximum
Output High Voltage (TTL) IOH = maximum
Output Low Voltage (TTL) IOL = maximum
Input High Voltage (CMOS)
Input Low Voltage (CMOS)
Input High Voltage (TTL)
Input Low Voltage (TTL)
Input High Voltage (TTL 5V tolerant)
Input Low Voltage (TTL 5V tolerant)
Input Leakage Current (0.1 V ) VIN ) VDD)
(all pins except those with internal pullup/pull-down resistors)
Output Leakage Current (0.1 V ) VOUT ) VDD)
Input Leakage Current VIH = VDD - 0.1 V
(pins with internal pull-down resistors)
Input Leakage Current VIL = 0.1 V
(pins with internal pull-up resistors)
Input Capacitance
Output Capacitance
I/O Capacitance
20
20
20
Typ
Max
Unit
33.3333
40.0000
50.0000
TBD
TBD
TBD
0.45
VDD + 10%
VDD x 30%
VDD + 10%
+0.8
VDD + 1.8
+0.8
±10
MHz
MHz
MHz
mA
mA
mA
V
V
V
V
V
V
V
V
V
V
µA
±15
60
µA
µA
-60
µA
VDD - 0.5
0.45
2.4
VDD x 70%
-0.5
2.0
-0.3
2.0
-0.3
8
8
10
pF
pF
pF
Notes:
© 1997 Zarlink Semiconductor Inc.
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6. AC SPECIFICATION
6.1 XpressFlow Bus Interface:
S_CLK
S12
S1-min
S_CLK
S_D[31:0]
S17
S18
S13
S2-min
S_D[31:0]
S_MSGEN#
S19
S20
S14
S3-min
S_MSGEN#
S_EOF#
S21
S22
S15
S4-min
S_EOF#
S_IRDY
S23
S24
S_IRDY
XpressFlow Bus Interface –
Output float delay timing
S27
S28
S_TABT#
S29
S_CLK
S30
S_HPREQ#
S1-max
S1-min
S31
S_D[31:0]
S32
S_GNT#
S2-max
S2-min
S33
S_MSGEN#
S34
S_OVLD#
S3-max
S3-min
S_EOF#
XpressFlow Bus Interface –
Input setup and hold timing
S4-max
S4-min
S_IRDY
S6-max
S6-min
S_TABT#
S7-max
S7-min
S_HPREQ#
S8-max
S8-min
S_REQ#
XpressFlow Bus Interface –
Output valid delay timing
© 1997 Zarlink Semiconductor Inc.
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4-Port 10/100M Ethernet Access Controller
-33
Symbol
A
-40
-50
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Note:
S1
S_D[31:0] output valid delay
6
20
5
18
4
15
CL = 50pf
S2
S_MSGEN# output valid delay
6
20
5
18
4
15
CL = 50pf
S3
S_EOF# output valid delay
6
20
5
18
4
15
CL = 50pf
S4
S_IRDY output valid delay
6
20
5
18
4
15
CL = 50pf
S6
S_TABT# output valid delay
6
20
5
18
4
15
CL = 50pf
S7
S_HPREQ# output valid delay
6
20
5
18
4
15
CL = 50pf
S8
S_REQ# output valid delay
6
20
5
18
4
15
CL = 20pf
S12
S_D[31:0] output float delay
15
13
10
S13
S_MSGEN# output float delay
15
13
10
S14
S_EOF# output float delay
15
13
10
S15
S_IRDY output float delay
15
13
10
S17
S_D[31:0] input set-up time
5
4.5
4
S18
S_D[31:0] input hold time
2
1.5
1.5
S19
S_MSGEN# input set-up time
5
4.5
4
S20
S_MSGEN# input hold time
2
1.5
1.5
S21
S_EOF# input set-up time
5
4.5
4
S22
S_EOF# input hold time
2
1.5
1.5
S23
S_IRDY input set-up time
5
4.5
4
S24
S_IRDY input hold time
2
1.5
1.5
S27
S_TABT# input set-up time
5
4.5
4
S28
S_TABT# input hold time
2
1.5
1.5
S29
S_HPREQ# input set-up time
5
4.5
4
S30
S_HPREQ# input hold time
2
1.5
1.5
S31
S_GNT# input set-up time
5
4.5
4
S32
S_GNT# input hold time
2
1.5
1.5
S33
S_OVLD# input set-up time
5
4.5
4
S34
S_OVLD# input hold time
2
1.5
1.5
AC Characteristics – XpressFlow Bus Interface
© 1997 Zarlink Semiconductor Inc.
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6.2 CPU Bus Interface:
P_CLK
P_CLK
P15
P16-min
P1
P2
P_RST#
P_D[31:0]
P3
P4
CPU Bus Interface –
Output float delay timing
P_ADS#
P5
P6
P_W/R#
P_CLK
P7
P8
P16-max
P16-min
P_CS#
P_D[15:0]
P9
P10
P17-max
P17-min
P_A[11:1]
P_RDY#
P11
P12
P18-max
P18-min
P_D[15:0]
P_INT
CPU Bus Interface –
Input setup and hold timing
CPU Bus Interface –
Output valid delay timing
-33
Symbol
Parameter
-40
-50
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Note:
P1
P_RST# input setup time
5
4.5
4
P2
P_RST# input hold time
2
1.5
1.5
P3
P_ADS# input set-up time
5
4.5
4
P4
P_ADS# input hold time
2
1.5
1.5
P5
P_W/R# input set-up time
5
4.5
4
P6
P_W/R# input hold time
2
1.5
1.5
P7
P_CS# input set-up time
5
4.5
4
P8
P_CS# input hold time
2
1.5
1.5
P9
P_A[11:1] input set-up time
5
4.5
4
P10
P_A[11:1] input hold time
2
1.5
1.5
P11
P_D[31:0]# input set-up time
5
4.5
4
P12
P_D[31:0]# input hold time
2
1.5
1.5
P15
P_D[31:0]# output float delay
P16
P_D[31:0]# # output valid delay
6
20
5
18
4
15
CL = 60pf
P17
P_RDY# output valid delay
6
20
5
18
4
15
CL = 60pf
P18
P_INT# output valid delay
6
20
5
18
4
15
CL = 20pf
15
13
10
AC Characteristics -- CPU Bus Interface
© 1997 Zarlink Semiconductor Inc.
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XpressFlow-2001 Series –
Ethernet Switch Chip-set
6.3 Local Memory Interface:
L_CLK
L_CLK
L1
L3-max
L3-min
L2
L_D[31:0]
L_D[31:0]
L4-max
L4-min
Local Memory Interface –
Input setup and hold timing
L_A[19:2]
L5-max
L5-min
L_CS[3:0]#
L_CLK
L6-max
L6-min
L10
L3-min
L_ADSC#
L_D[31:0]
L7-max
L7-min
L_BWE[3:0]#
Local Memory Interface –
Output float delay timing
L8-max
L8-min
L_WE#]
L9-max
L9-min
L_OE#
Local Memory Interface –
Output valid delay timing
-33
Symbol
Parameter
-40
-50
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Note:
L1
L_D[31:0]# input set-up time
5
4.5
4
L2
L_D[31:0]# input hold time
2
1.5
1.5
L3
L_D[31:0]# output valid delay
6
20
5
18
4
15
CL = 30pf
L4
L_A[19:2] output valid delay
6
20
5
18
4
15
CL = 30pf
L5
L_CS[3:0]# output valid delay
6
20
5
18
4
15
L6
L_ADSC# output valid delay
6
20
5
18
4
15
CL = 30pf
L7
L_BWE[3:0]# output valid delay
6
20
5
18
4
15
CL = 30pf
L8
L_WE# output valid delay
6
20
5
18
4
15
CL = 10pf
L9
L_OE# output valid delay
6
20
5
18
4
15
CL = 10pf
L10
L_D[31:0]# output float delay
15
13
10
AC Characteristics – Local Memory Interface
© 1997 Zarlink Semiconductor Inc.
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XpressFlow-2001 Series –
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7. PACKAGING INFORMATION
352-PIN BGA
(35x35x2.33mm)
Pin 1 I.D.
B
24
26
25
20
22
23
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
0.75 DIA
+/- 0.15
(352X)
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
24.00 Ref
1.27
32.00 Ref
31.75
35.00 +/- 0.20
1.17
Ref
C
0.56 2.33
Ref +/-0.13
0.60 +/-0.10
This Document contains advance information on a product under development. Zarlink Semiconductor Inc. reserves the right to make any changes without notice.
400 March Road
Ottawa, Ontario, Canada K2K 3H4
Tel. 613 592 0200, FAX: 613 592 1010
Web Site: www.zarlink.com
Rev. 4.0 December 1997
¶1997 Zarlink Semiconductor Inc.
E1
DIMENSION
A
A1
A2
D
D1
E
E1
b
e
MIN
MAX
2.20
2.46
0.50
0.70
1.17 REF
35.20
34.80
30.00 REF
35.20
34.80
30.00 REF
0.60
0.90
1.27
352
Conforms to JEDEC MS - 034
E
e
D1
A2
D
A1
A
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
c Zarlink Semiconductor 2002 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes:
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TECHNICAL DOCUMENTATION - NOT FOR RESALE