[AKD7780] AKD7780 AK7780 Evaluation Board Rev.0 GENERAL DESCRIPTION The AKD7780 is an evaluation board for AK7780, which is a highly integrated audio processor including two 24-bit stereo ADC’s, a mono ADC and a stereo SRC. This board is composed of a main board and a sub board. AKD7780 has SPDIF input/output port, 2 pairs of stereo analog input ports, 1 mono analog input port, 4 pairs of stereo analog output ports and this helps to the evaluation of AK7780. Ordering guide AKD7780 --- Evaluation board for AK7780 Cable for connecting with printer port of IBM-AT compatible PC and control software and driver for Windows 2000/XP are packed with this. This control software does not operate on Window NT. Windows 2000/XP needs an installation of driver. In case of Windows 95/98/ME, the installation is not needed. FUNCTION Register setting / Download / Read back function to/from PC Digital interface by SPDIF I/O Digital interface by general audio data header(x2) Analog interface of ADC 5ch / DAC 8ch (Note: There is no DAC within AK7780. 8ch DAC AK4359 is equipped.) AKD7780 main board Digital port Digital port PC AK7780 Path Controller (FPGA) AK4359 AK4114 ( 8ch DAC ) Analog out Printer port ( DIR / DIT ) Analog in Digital in / out (Note) AK4114 has DIR, DIT and X’tal oscillator. Figure 1. AKD7780 Block Diagram <KM090600> 2007/09 -1- [AKD7780] Evaluation Board Diagram Board Diagram +12V AK7780 sub-board SMUX2 SMUX1 JTAG PC I/F GND Path Controller (FPGA) AK 7780 -12V Clock (JP5) Optical Out Clock (JP1) Power Supply (JP2-3, JP5-6, JP9-10, JP22) AK 4114 AK4359 Optical In AIN selector (JP12-JP18) ADCM AIN1 AIN2 DAC4 DAC3 DAC2 DAC1 Figure 2. AK7780 Board Diagram Description (1) AIN/DAC/ADCM RCA Jack. White is for Lch and Red is for Rch. Yellow one is for mono input. (2) Optical In Optical input connector. It supports sampling frequencies from 32Hz to 48Hz. It is used as digital data source for AK7780. When AK7780 is operated in slave mode, this input signal is always necessary. (3) Optical Out Optical output connector. It can be selected from SDOUT1-6 or ADOUTA1. (4) Power Supply Supply +12V, GND, -12V for each terminal. Current consumption is about 500mA in operation. (5) Clock (jumper) Clock source jumper. Select clock source between “EXT” and “XTL” for AK4114 or AK7780. (6) Other jumper pins’ setting According to Table 1. / Table 2. (7) PC/IF Connect to PC printer port (Parallel port) with attached cable. Input signals are pull-upped with 10k-ohm resistance. Output signals are 0-5V swing. <KM090600> 2007/09 -2- [AKD7780] Pin 2 3 4 5 6 7 8 9 I/O I I I I I I I I Function nCS3 for AK4114 INIT_RESET (not used) I2CSEL SCLK SI nCS for AK7780 nCS2 for FPGA Pin 10 11 12 13 15 I/O O O O O O Function (not used) (not used) RDY SO (not used) (8) Audio digital data port Two of digital ports (SMUX1/SMUX2) are available. Pin I/O Function pin I/O Function 1 I MCLK 2 P GND 3 I BITCLK 4 P GND 5 I LRCLK 6 (NC) 7 I DI 8 (NC) 9 P VDD 10 O DO ■ Path Controller The Path Controller manages I/O control for audio signal, selector, and AK7780 pin configuration. This controller has 3 words register and each register has 16bit. Access is done by 18bit length as bellow format. nCS2 SCLK SI A1 A0 D15 ADDRESS=0 D[15] (test) D[14:12] SDOUT D[11:10] SRC D[9:8] SDIN5 D[7:6] SDIN4 D[5:4] SDIN3 D[3:2] SDIN2 D[1:0] SDIN1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Set 0. Output signal select. 000: SDOUT1 001: SDOUT2 -- 101: SDOUT6 110: SDOUTA1 111:Low Select SRC master device. 00: AK4114 01: SMUX1 10: SMUX2 11: Low SDIN5 pin input select 00: AK4114 01: SMUX1 10: SMUX2 11: Low SDIN4 pin input select 00: AK4114 01: SMUX1 10: SMUX2 11: Low SDIN3 pin input select 00: AK4114 01: SMUX1 10: SMUX2 11: Low SDIN2 pin input select 00: AK4114 01: SMUX1 10: SMUX2 11: Low SDIN1 pin input select 00: AK4114 01: SMUX1 10: SMUX2 11: Low <KM090600> 2007/09 -3- [AKD7780] ADDRESS=1 D[6:4] CKM[2:0] D[3:2] SELSRC[1:0] D[1:0] CAD[1:0] ADDRESS=2 D[15] TRXPDN D[14] DACPDN D[13] SRCRST D[12] ADRST D[11] DSPRST D[10] CKRST D[9:8] MASTER D[6] D[5] D[4] D[3] D[2] D[1] D[0] (not used) TEST2 TEST1 SRCMUTE JX2 JX1 JX0 AK7780 CKM pin setting AK7780 SELSRC pin setting 00: LRCK 01:BICK 10:TEST 11:TEST AK7780 CAD pin setting AK4114 PDN pin setting AK4359 reset pin setting AK7780 SRCRST pin setting AK7780 ADRST pin setting AK7780 DSPRST pin setting AK7780 CKRST pin setting Select master device for AK7780 00: AK4114 01: SMUX1 10: SMUX2 11: AK7780 AK7780 TEST2I pin setting (Normally 0) AK7780 TEST1I pin setting (Normally 0) AK7780 SRCMUTE pin setting AK7780 JX2 pin setting AK7780 JX1 pin setting AK7780 JX0 pin setting <KM090600> 2007/09 -4- [AKD7780] Evaluation Board Manual Operation sequence 1. Set up the power supply lines. [+12V] (red) = +12V [-12V] (blue) = -12V [GND] (black) = 0V Each supply line should be distributed from the power supply unit. 2. Set up the jumper pins (according to the follows). 3. Connect the needed connector (according to the follows). 4. Power on. 5. Set up the register via PC (according to the follows). Evaluation Mode (1) ADC with external DIT 1. Connection of connector For analog input, RCA1(AIN1L)/RCA2(AIN1R) or RCA3(AIN2L)/RCA4(AIN2R) or RCA5(AIN MONO) is available. For digital output, optical connector PORT2 (TOTX141) is available. 2. Setting of jumper pins for analog output (JP12 – JP18) According to Table 3. / Table 4. / Table 5. 3. Set up the FPGA and AK7780 control register via PC. (2) SRC with external DIR, DIT 1. Connection of connector For digital input, optical connector PORT1 (TORX141) is available. For digital output optical connector PORT2 (TOTX141) is available. 2. Set up the FPGA and AK7780 control register via PC. Register Control It is possible to control AKD7780 via printer port (parallel port) of IBM-AT compatible PC. Connect the P1 port on board to PC with the packed cable. Control software is packed with this board. The software operation sequence is included in the evaluation board manual. Indication for LED [LED] : U17 When power is supplied , LED is lighted to red. Monitor the PC_RQ_N signal and change the color when the board is communicating with PC. <KM090600> 2007/09 -5- [AKD7780] Setting of Jumper Pins (main board) Jumper JP01 (AK4114 Clock) JP02 (AVDD) JP03 (AVDD_SRC) JP05 (AVSS) JP06 (DVDD18) JP09 (DVSS) JP10 (DVDD) JP12 (AIN1-Lch) JP13 (AIN1-Rch) JP18 (AIN-Mono) JP22 (P DVDD) Setting (Default) Note “XTL”: XTL “EXT”: External Clock Short AK7780 AVDD Short AK7780 AVDD_SRC Short AK7780 AVSS Short AK7780 DVDD18 Short AK7780 DVSS Short AK7780 DVDD Short AINLN Short AINRN Short AINM Short Peripheral DVDD Table 1. Setting of jumper pins on main board “XTL” (sub board) Jumper Setting (Default) JP4 (CLKO2) Short JP5 (AK7780 Clock) JP6 (CLKO1) Note Short: CLKO1 output “XTL”: XTL “XTL” “EXT”: External Clock Short Short: CLKO1 output Table 2. Setting of jumper pins on sub board <KM090600> 2007/09 -6- [AKD7780] Analog Input Circuit Figure 3. AIN1 Analog Input Circuit Figure 4. AIN MONO Analog Input Circuit <KM090600> 2007/09 -7- [AKD7780] Figure 5. AIN2 Analog Input Circuit For analog input, RCA1(AIN1L)/ RCA2(AIN1R), RCA3(AIN2L)/RCA4(AIN2R), RCA5(AIN MONO) are available. The AK7780 supports single-ended input mode, monaural single-ended input mode and differential input mode. The input range of AIN is [email protected]. ・Setting of jumper pins of analog input circuit JP12 JP13 Input Pin AINLN/ AINLP AINRN/AINRP AINL2/ AINR2 JP14 JP15 Short Short 1-2 pin Short 1-2 pin Short Open Open 7-8 pin Short 7-8 pin Short AINL3/ AINR3 Open Open 5-6 pin Short 5-6 pin Short AINL4/ AINR4 Open Open 3-4 pin Short 3-4 pin Short AINL5/ AINR5 Open Open 9-10 pin Short 9-10 pin Short AINL6/ AINR6 Open Open 11-12 pin Short 11-12 pin Short AINL7/ AINR7 Open Open 13-14 pin Short 13-14 pin Short AINL8/ AINR8 Open Open 15-16 pin Short 15-16 pin Short Default Table 3. Setting of input when using AIN1L/AIN1R <KM090600> 2007/09 -8- [AKD7780] Input Pin JP16 AINL2/ AINR2 7-8 pin Short 7-8 pin Short AINL3/ AINR3 5-6 pin Short 5-6 pin Short JP17 AINL4/ AINR4 3-4 pin Short 3-4 pin Short AINL5/ AINR5 9-10 pin Short 9-10 pin Short AINL6/ AINR6 11-12 pin Short 11-12 pin Short AINL7/ AINR7 13-14 pin Short 13-14 pin Short AINL8/ AINR8 15-16 pin Short 15-16 pin Short Default Table 4. Setting of input when using AIN2L/AIN2R Input Pin JP18 AIN MONO Short Default Table 5. Setting of input when using AIN MONO <KM090600> 2007/09 -9- [AKD7780] Analog Output Circuit Figure 6. DAC1, DAC2 Analog Output Circuit <KM090600> 2007/09 - 10 - [AKD7780] Figure 7. DAC3, DAC4 Analog Output Circuit There is no DAC within AK7780. So 8ch DAC AK4359 is equipped on board. For analog output, connector RCA6(DAC1L), RCA7(DAC1R), RCA8(DAC2L), RCA9(DAC2R), RCA10(DAC3L), RCA11(DAC3R), RCA13(DAC4L), RCA12(DAC4R) are available. <KM090600> 2007/09 - 11 - [AKD7780] Digital Input Circuit (External DIR:PORT1) Figure 8. Digital Input Circuit (AK4114) For digital input, optical connector PORT1 is available. Digital output circuit (External DIT:PORT2) Figure 9. Digital Output Circuit (AK4114) For digital output, optical connector PORT2 is available. <KM090600> 2007/09 - 12 - [AKD7780] Control Software Manual Set-up of the evaluation board and control software 1. Set up the AKD7780 according to previous term. 2. Connect IBM-AT compatible PC with AKD7780 by 25 pin printer cable (packed with AKD7780). (Please install the driver in the CD-ROM when software is used on Window 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT. And the operation on Windows Vista has not been confirmed.) 3. Insert the CD-ROM labeled “AK7780 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AK7780.exe” to set up the program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow 1. Set up the control program according to the explanation above. 2. Click “Board Init” button to initialize the board. 3. Select the needed dialogue to evaluate by changing the setting. Figure 10. The image of control software <KM090600> 2007/09 - 13 - [AKD7780] Control software supports program download, register setting, peripheral logic setting and running script. These menus are changing at upper tab. Frequent used function are placed outside of main menu. (1) Download Figure 11. 「Download」 Dialogue Push “Refer” button at source item and select source file. And then, push “Assemble” button, Assembler runs and outputs result. Automatically assembled file is selected as a PRAM file. Push “Write” button, download process is done. “Assemble Write” button do all of this process. In this menu, read back of download data, SO-read function, JX setting, CRAM/OFRAM writing under operation are supported. <KM090600> 2007/09 - 14 - [AKD7780] (2) Register Setting Figure 12. 「REG1」 Dialogue REG1/REG2/REG3/TEST tabs are register setting window. (Test items are inactivated.) Check each button and control software will write to each AK7780 register. When accessing to CONT0 register, DSR_RESET will automatically to L. The reference page of registers in datasheet is as follow: Register CONT00 CONT01 CONT02 CONT03 CONT04 CONT05 CONT06 Reference Page Register Reference page 31 CONT07 38 32 CONT08 39 33 CONT09 40 34 CONT0A 41 35 CONT0B 42 36 CONT0C 43 37 CONT0D 44 Table 6. Reference page of registers <KM090600> 2007/09 - 15 - [AKD7780] (3) Peripheral logic setting Figure 13. 「XILINX」 Dialogue In this menu, Path Controller and AK4114 setting are supported. AK7780 is set to master mode and other devices are set to slave mode after start up. <KM090600> 2007/09 - 16 - [AKD7780] (4) Script Figure 14. 「Script」 Dialogue Select script file and runs. “Repeat” button runs current selected script once again. Command [SCRIPT] ;comment W,<address>,<data> W,0xC0,0x00 WL,<command>,<address>,<data>,… WL,0x82,0x0022,0x4000,0x4000,0x4000 D,<address>,<data> X,<address>,<data> P,<message> RI:H / RI:L RS:H / RS:L RA:H / RA:L RD:H / RD:L RC:H / RC:L T,<wait> T,50mS LP:<filename> LC:<filename> LO:<filename> Description Script file header. If this header is missing, Header error will occur. After semi-colon sentence will be ignored as comment. AK7780 register access. AK7780 continuous data access. This is possible to use CRAM access in operating. Command data is byte, following data are word length. AK4114 register access. FPGA register access. Display any message, and suspend script process. AK7780 reset control. INIT_RESET, SRC_RESET, ADC_RESET, DSP_RESET and CK_RESET. Wait script process. Unit is mS only. Download PRAM data Download CRAM data Download OFFSET RAM data Table 7. Script command <KM090600> 2007/09 - 17 - [AKD7780] ■ How to use (1) D-to-D Digital to Digital loop back. The AK4114 is master device, and the AK7780 operates in slave mode. Please confirm that JP1 of main board is XTL side and JP5 of daughter board is EXT side. (a) (b) (c) (d) After starting up, Push “Board Initialize” button. Select SCRIPT tab, and runs scriptMASTER.txt. Push “refer” button and select DtoAD.txt file. Push “Assemble Write” button. Figure 15. 「D-to-D」 <KM090600> 2007/09 - 18 - [AKD7780] (2) SRC operation confirmation The AK4114 is the master device of SRC, and the AK7780 operates as master device with crystal oscillation. Input data from optical terminal goes via SRC, and DSP output will go to DAC at fs=96kHz. Please confirm that JP1 of main board is XTL side and JP5 of daughter board is XTL side. (a) After starting up, Push “Board Initialize” button. (b) Select SCRIPT tab, and runs scriptSRC.txt. Figure 16. 「SRC operation confirmation」 This script file will set each register setting, and download SRC.obj automatically (SRC.obj is SRC-to-DSP output through program). <KM090600> 2007/09 - 19 - [AKD7780] REVISION HISTORY Date (yy/mm/dd) 07/09/10 Manual Revision KM090600 Board Revision 0 Reason Page Contents First edition IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM090600> 2007/09 - 20 - 5 4 3 2 1 AK7780 DAC D DAC_PDN DAC_PDN XILINX TRX_BICK TRX_LRCK TX_CLK RX_CLK RX_CLK2 RX_DAT TX_DAT C BITCLK_O LRCLK_O BITCLK_I LRCLK_I BITCLK_O LRCLK_O BITCLK_I LRCLK_I CLKO1 CLKO2 MCLK SDIN1 SDIN2 SDIN3 SDIN4 SDIN5 CLKO1 CLKO2 MCLK SDIN1 SDIN2 SDIN3 SDIN4 SDIN5 SRC_BICK SRC_LRCK SRCSET0 SRCSET1 SRC_BICK SRC_LRCK SRCSET0 SRCSET1 AK4114 JX0 JX1 JX2 JX0 JX1 JX2 CKM0 CKM1 CKM2 CKM0 CKM1 CKM2 TEST1 TEST2 TESTI1 TESTI2 P_DSP_RESET P_AD_RESET P_CK_RESET P_SRC_RESET P_SRC_SMUTE P_DSP_RESET P_AD_RESET P_CK_RESET P_SRC_RESET P_SRC_SMUTE X_SCLK X_SI X_RQ_N X_SO X_SDA X_SCLK X_SI X_RQ_N X_SO X_SDA POW ER XILINX AINRP AINRN AINR2 AINR3 AINR4 AINR5 AINR6 AINR7 AINR8 AINM ANALOG CLKO1 CLKO2 MCLK SDIN1 SDIN2 SDIN3 SDIN4 SDIN5 C SRC_BICK SRC_LRCK SRCSET0 SRCSET1 JX0 JX1 JX2 CKM0 CKM1 CKM2 TEST1 TEST2 P_DSP_RESET P_AD_RESET P_CK_RESET P_SRC_RESET P_SRC_SMUTE X_SCLK X_SI X_RQ_N X_SO X_SDA B I2CSEL PC_SCLK PC_SI PC_RQ_N CS2 CS3 I2CSEL POW ER AINM AINM D BITCLK_O LRCLK_O BITCLK_I LRCLK_I PC_SO LED_IND B SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 SDOUT6 SDOUTA1 AINLP AINLN AINL2 AINL3 AINL4 AINL5 AINL6 AINL7 AINL8 RDY STO TRX_BICK TRX_LRCK TX_CLK RX_CLK RX_CLK2 RX_DAT TX_DAT PC_SCLK PC_SI CS3 TRX_BICK TRX_LRCK TXCLK RX_CLK RX_CLK2 RX_DAT TX_DAT SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 SDOUT6 SDOUTA1 SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 SDOUT6 SDOUTA1 DAC_PDN TRX_PDN TRX_PDN IRESET AK4114 AINRP AINRN AINR2 AINR3 AINR4 AINR5 AINR6 AINR7 AINR8 AINRP AINRN AINR2 AINR3 AINR4 AINR5 AINR6 AINR7 AINR8 DAC TRX_PDN AINLP AINLN AINL2 AINL3 AINL4 AINL5 AINL6 AINL7 AINL8 AINLP AINLN AINL2 AINL3 AINL4 AINL5 AINL6 AINL7 AINL8 SDOUT1 SDOUT2 SDOUT3 SDOUT4 BITCLK_O LRCLK_O CLKO1 AK7780 PCIF PC_SCLK PC_SI PC_RQ_N CS2_N CS3_N I2CSEL IRESET PC_SO LED_IND RDY STO A PC_SCLK PC_SI PC_RQ_N CS2_N CS3_N I2CSEL IRESET PC_SO LED_IND RDY STO A Title PCIF TOP Size A3 Date: 5 4 3 2 Document Number <Doc> Friday, July 07, 2006 Rev A Sheet 1 1 of 8 5 4 3 2 1 D D AVDD C1 DVDD_3.3V + C2 10uF SPDIF-IN L1 0.1uF 10uH PORT1 VCC GND OUT 3 2 1 R2 470 C3 R1 0.1uF 18k DIF_RX TORX141 default 1-2short + C5 U1 1 2 3 4 5 6 7 8 9 10 11 12 C DVDD_3.3V RX4 NC1 RX5 TEST2 RX6 NC3 RX7 IIC P/SN XTL0 XTL1 VIN L2 AK4114 13 14 15 16 17 18 19 20 21 22 23 24 SPDIF-OUT XTL INT0 CSN CCLK CDTI CDTO PDN XTI XTO DAUX MCKO2 BICK SDTO 36 35 34 33 32 31 30 29 28 27 26 25 TRX_PDN TXCLK R3 R6 R5 X'TAL1 C6 22pF DIF_TX C8 TX_DAT RX_CLK2 TRX_BICK RX_DAT AK4114 PORT2 C10 100 100 100 12.288MHz R7 R8 3 2 1 C CS3 PC_SCLK PC_SI 10uH 100 100 C7 22pF TRX_LRCK RX_CLK C11 + C9 0.1uF TOTX141 0.1uF 10uF SPDI/F Optical out C13 0.1uF C12 + IN VCC GND EXT JP1 HEADER 3 1 2 3 10uF 48 47 46 45 44 43 42 41 40 39 38 37 0.1uF RX3 NC6 RX2 TEST1 RX1 NC5 RX0 AVSS VCOM R AVDD INT1 C4 TVDD NC4 TX0 TX1 BOUT COUT UOUT VOUT DVDD DVSS MCKO1 LRCK SPDI/F Optical in 10uF + B B 10uF DVDD_3.3V DVDD_3.3V DVDD_3.3V 1 TP(BLACK) TP1 + C14 100uF/16V(A) A A Title <Title> Size A3 Date: 5 4 3 2 Document Number <Doc> Friday, July 07, 2006 Rev <RevCode> Sheet 1 2 of 8 5 4 3 2 1 AVDD HEADER 2 HEADER 2 1 2 1 2 default short JP2 default short JP3 JP4 + C15 10uF(A) AVDD_SRC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 D + JP5 AVDD_AD C16 10uF(A) D AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 AINRN AINRP AINLN AINLP AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8 HEADER 25X2 AVSS_CHIP 2 1 default short 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 HEADER 2 DVDD18 C C HEADER 2 default short 1 2 DVDD18_CHIP JP6 JP8 JP7 + B C17 10uF(A) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TEST2 P_SRC_SMUTE P_SRC_RESET X_SDA SRC_LRCK SRC_BICK SDIN1 JX0 JX1 JX2 CLKO2 SDOUT6 SDOUTA1 STO RDY TEST1 I2CSEL SRCSET1 SRCSET0 MCLK CKM1 CKM0 CKM2 LRCLK_O BITCLK_O SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C18 10uF(A) + HEADER 15X2 HEADER 15X2 B DVSS_CHIP JP9 DVDD HEADER 2 HEADER 2 default short 1 2 JP10 + A default short 2 1 C19 10uF(A) JP11 DVDD_CHIP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 CLKO1 SDIN2 SDIN3 SDIN4 SDIN5 BITCLK_I LRCLK_I IRESET P_CK_RESET P_AD_RESET P_DSP_RESET X_RQ_N X_SI X_SCLK X_SO 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 A HEADER 15X2 Title AK7780 HEADER Size A3 Date: 5 4 3 2 Document Number <Doc> Friday, July 07, 2006 Rev A Sheet 1 3 of 8 5 4 AMP_PW - 1 22uF(A) 1 3 5 7 9 11 13 15 4 R15 10k NJM5532D 1 6 NJM5532D C30 7 + + 8 + 5 2 default short 1-2 JP15 U3B R16 10k NJM5532D 1 6 NJM5532D C35 7 + 8 + C34 8 22uF(A) AMP_PW+ 10uF AMP_PW + AMP_PW - D C32 68pF(C/DIP) 5 C33 0.1uF AINRN 22uF(A) U3A 3 AMP_PW+ R14 10k C31 68pF(C/DIP) HEADER 8X2 22uF(A) 8 AINLP AINL4 AINL3 AINL2 AINL5 AINL6 AINL7 AINL8 2 4 6 8 10 12 14 16 C26 10uF + 3 U2B - 4 U2A 2 R13 10k JP14 C25 0.1uF 4 C29 68pF(C/DIP) 4 C28 68pF(C/DIP) R11 10k default short C27 + MR-552LS(R) D AMP_PW- 1 2 + 1 2 AMP_PW- T B S AINLN 22uF(A) + R10 10k AMP_PW - C24 RCA2 - R12 10k JP13 HEADER 2 default short C23 C22 10uF + MR-552LS(W ) C21 0.1uF - R9 10k + 22uF(A) + T B S 2 + C20 RCA1 3 HEADER 2 JP12 C36 0.1uF 1 3 5 7 9 11 13 15 AINRP AINR4 AINR3 AINR2 AINR5 AINR6 AINR7 AINR8 2 4 6 8 10 12 14 16 HEADER 8X2 default short 1-2 + C37 10uF AMP_PW + MR-552LS(R) 3 4 4 - 1 6 NJM5532D - 2 U4B R23 10k C48 7 + + 8 + 5 AINL4 AINL3 AINL2 AINL5 AINL6 AINL7 AINL8 R22 10k C47 68pF(C/DIP) JP17 U5A 2 default short 7-8 NJM5532D U5B R24 10k 1 3 6 + C50 8 C51 22uF(A) 8 C49 0.1uF NJM5532D 7 5 + AMP_PW+ C43 10uF C46 68pF(C/DIP) HEADER 8X2 22uF(A) 8 2 4 6 8 10 12 14 16 4 1 3 5 7 9 11 13 15 U4A NJM5532D R21 10k JP16 C42 0.1uF 4 C45 68pF(C/DIP) R20 10k + C44 68pF(C/DIP) 22uF(A) AMP_PW- T B S R19 10k + R18 10k + RCA4 - + C AMP_PW - C41 - R17 10k MR-552LS(W ) C40 10uF + 22uF(A) C39 0.1uF + T B S AMP_PW- C38 RCA3 C 10uF AMP_PW+ B AMP_PW + C52 0.1uF 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 AINR4 AINR3 AINR2 AINR5 AINR6 AINR7 AINR8 HEADER 8X2 default short 7-8 B + C53 10uF AMP_PW AMP_PW + + R25 10k MR-552LS(Y) C55 0.1uF C56 10uF AMP_PW + R26 10k + C57 100uF/16V(A) R27 10k C58 68pF(C/DIP) C59 68pF(C/DIP) 1 A 6 NJM5532D AMP_PW - 1 2 A + + 8 5 default short C61 7 + 3 U6B R28 10k 4 NJM5532D + C60 100uF/16V(A) - 4 U6A 2 TP(BLACK) TP2 JP18 HEADER 2 1 22uF(A) + T B S AMP_PW- C54 RCA5 AINM AMP_PW+ 8 22uF(A) C62 0.1uF Title + C63 Analog input 10uF Size A3 AMP_PW + Date: 5 4 3 2 Document Number <Doc> Friday, July 07, 2006 Rev A Sheet 1 4 of 8 5 4 3 2 1 AMP_PW + AMP_PW AMP_PW - ROUT1 T B S + 22uF(A) 4 RCA7 + C65 10uF C66 0.1uF MR-552LS(R) + C74 10uF C75 0.1uF C73 7 22uF(A) T B S 22uF(A) R33 22k MR-552LS(W ) R34 22k NJM5532D 5 C72 220pF(F/DIP) DAC1 8 22uF(A) 6 8 4 1 3 C67 220pF(F/DIP) U7B R32 4.7k + C71 - + RCA6 + D 2 C70 R31 4.7k + C69 LOUT1 R30 4.7k NJM5532D + R29 4.7k C68 220pF(F/DIP) U7A - C64 220pF(F/DIP) D AMP_PW + AMP_PW + AMP_PW AMP_PW + AMP_PW AMP_PW - RCA8 22uF(A) 4 RCA9 + C78 10uF C82 0.1uF MR-552LS(R) + C86 10uF C87 0.1uF C80 7 5 C85 220pF(F/DIP) 22uF(A) T B S 22uF(A) R40 22k MR-552LS(W ) R38 22k 6 DAC2 8 22uF(A) R39 4.7k 8 + C81 220pF(F/DIP) ROUT2 T B S + + 1 3 R37 4.7k C84 + 4 2 C83 + R36 4.7k NJM5532D U8B NJM5532D + R35 4.7k C79 LOUT2 C77 220pF(F/DIP) U8A - C76 220pF(F/DIP) AMP_PW + AMP_PW + AMP_PW AMP_PW - AMP_PW + AMP_PW C89 220pF(F/DIP) C96 RCA10 + C97 220pF(F/DIP) 22uF(A) 7 5 C95 220pF(F/DIP) 22uF(A) + C90 10uF C94 0.1uF + C98 10uF C99 0.1uF T B S 22uF(A) MR-552LS(R) R42 22k MR-552LS(W ) R46 22k 6 DAC3 8 22uF(A) R45 4.7k RCA11 8 + 3 ROUT3 T B S R44 4.7k C92 1 + 4 NJM5532D C93 + 2 + LOUT3 R43 4.7k C U9B NJM5532D + R41 4.7k C91 U9A 4 C88 220pF(F/DIP) - C AMP_PW + AMP_PW + AMP_PW AMP_PW - AMP_PW + AMP_PW - ROUT4 T B S + 22uF(A) 4 6 C108 RCA12 7 + C104 10uF C105 0.1uF + C110 10uF C111 0.1uF T B S 22uF(A) MR-552LS(R) R52 22k MR-552LS(W ) R51 22k R50 4.7k 5 C109 220pF(F/DIP) DAC4 8 22uF(A) R49 4.7k C107 8 4 1 3 C101 220pF(F/DIP) 22uF(A) B RCA13 + C103 - + NJM5532D + 2 + LOUT4 R48 4.7k U10B NJM5532D + R47 4.7k C106 C102 220pF(F/DIP) U10A - C100 220pF(F/DIP) B AMP_PW + AMP_PW + AMP_PW - VDD_DAC DAC 5V C120 0.1uF U12 VCC A1 A2 A3 A4 A5 A6 A7 A8 1 19 10 G1 G2 GND 74HCT541 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 A R53 R59 R55 R56 100 100 100 100 R57 R58 R60 100 100 100 DAC_MCLK DAC_BICK DAC_SDTI1 DAC_LRCK DAC_PDW N DAC_SDTI2 DAC_SDTI3 DAC_SDTI4 DVDD_DAC TP(BLACK) TP3 DAC_GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MCLK BICK SDTI1 LRCK PDN CSN CCLK CDTI SDTI2 SDTI3 SDTI4 DIF1 DEM0 DVDD DVSS DZF1 DZF2 AVDD AVSS VCOM LOUT1 ROUT1 PS LOUT2 ROUT2 LOUT3 ROUT3 LOUT4 ROUT4 I2C 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C112 0.1uF + C113 10uF R54 2 DAC_VCOM LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 LOUT4 ROUT4 C119 10uF C114 10uF OUT C115 0.1uF W IRE1 DAC_GND AMP_PW + REG1 10 + C118 0.1uF TAB is VOUT VDD_DAC LM1117-5V GND 20 2 3 4 5 6 7 8 9 DVDD_DAC + CLKO1 BITCLK_O SDOUT1 LRCLK_O DAC_PDN SDOUT2 SDOUT3 SDOUT4 U13 IN 1 3 DVDD_DAC C116 0.1uF + C117 10uF W IRE wired short DAC_GND A AK4359 1 + C121 10uF C122 0.1uF DAC_GND Title DAC Size A3 DAC_GND DAC_GND Date: 5 4 3 2 Document Number <Doc> Thursday, July 06, 2006 Rev A Sheet 1 5 of 8 5 4 3 2 1 18 17 16 15 14 13 12 11 CS3_N IRESET I2CSEL PC_SCLK PC_SI PC_RQ_N CS2_N PC_RQ_N Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 U14 VCC A1 A2 A3 A4 A5 A6 A7 A8 C STO TP(BLUE) TP4 TP(BLUE) TP5 10k 10k 10k 10k 10k 10k R64 R65 R66 R67 R68 P1 R72 100 R73 100 R74 100 R75 100 R69 100 R70 100 R71 100 R76 100 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 C 1 TP(BLACK) TP6 D-SUB25-FEMALE + C124 STO 1 100uF/16V(A) R63 C123 0.1uF D DVDD_5V 1 DVDD_3.3V 10k PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 1 19 10 G1 G2 74LVC541 GND RDY 20 2 3 4 5 6 7 8 9 10k DVDD_3.3V R62 D R61 DVDD_5V RDY PC_SO LED_IND C125 0.1uF 20 2 3 4 5 6 7 8 9 U15 VCC A1 A2 A3 A4 A5 A6 A7 A8 1 19 10 G1 G2 GND 74HCT541 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 DVDD_5V LED(RED) RUN/RESET R77 B 470 B D1 DVDD_5V DVDD_5V 16 6 + R78 C127 0.1uF U16B VCC CEXT C126 33uF(A) 10k 7 PC_RQ_N 9 10 11 8 REXT/CEXT A B CLR GND 74HC221 U17 Q Q 5 12 R79 R80 100 100 1 3 GREEN COM RED 2 16 14 U16A VCC CEXT 15 REXT/CEXT 1 2 3 8 A B CLR GND 74HC221 Q 13 Q 4 BICOLOR LED A A Title <Title> Size A3 Date: 5 4 3 2 Document Number <Doc> Friday, July 07, 2006 Rev <RevCode> Sheet 1 6 of 8 5 4 AK7780 3.3V DVDD 3 2 1 HEAT SINK necessary TAB is VOUT AK7780 3.3V AVDD AMP_PW + AVDD DVDD REG2 LM1084-3.3V 2 D OUT GND L3 IN TM1 1 1 10uH + + C129 0.1uF C130 10uF 3 C128 10uF + C132 0.1uF C131 0.1uF + C133 10uF RED(+12V) D TM2 1 W IRE2 i TJ-563 C134 100uF/16V(A) W IRE i BLACK(GND) TJ-563 wired short + C135 100uF/16V(A) TM3 1 i BLUE(-12V) TJ-563 AK7780 1.8V DVDD TAB is VOUT DVDD18 REG3 + C136 10uF C LM1117-1.8V GND OUT IN 1 3 2 C137 0.1uF AMP_PW - C138 0.1uF + C142 0.1uF + C139 10uF C default short JP22 HEADER 2 TAB is VOUT 2 1 Peripheral 3.3V DVDD DVDD_3.3V REG4 C140 10uF GND LM1117-3.3V C141 0.1uF B IN 1 DVDD_5V REG5 C144 10uF B OUT LM1084-5V 3 2 + C143 10uF HEAT SINK necessary TAB is VOUT Peripheral 5V DVDD GND + OUT 3 2 C145 0.1uF IN 1 C146 0.1uF + C147 10uF A A Title <Title> Size A3 Date: 5 4 3 2 Document Number <Doc> W ednesday, July 12, 2006 Rev <RevCode> Sheet 1 7 of 8 5 4 3 2 1 DVDD_5V wired short W IRE3 W IRE SMUX_DVDD SMUX PORT C148 0.1uF D + C149 10uF D JP19 SMUX_MCLK SMUX_BICK SMUX_LRCK SMUX_DAT1 1 3 5 7 9 2 4 6 8 10 HEADER 5X2 SMUX_DAT2 SMUX PORT2 JP20 R81 MCLK SRCSET0 SRCSET1 I2CSEL TESTI1 LED_IND DAC_PDN TRX_PDN TX_CLK RX_CLK RX_CLK2 TX_DAT TRX_LRCK TRX_BICK R82 100 100 R96 100 R97 100 CS3 CS2 PC_RQ_N PC_SI B R100 PC_SCLK 100 JTAG PORT2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 99 4 3 27 23 22 GSR GTS2 GTS1 GCK3 GCK2 GCK1 48 45 83 47 TCK TDI TDO TMS 2 7 19 24 34 43 46 73 80 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 59 60 61 63 64 66 65 67 68 70 71 72 74 76 77 78 79 81 82 85 86 87 89 90 91 92 93 94 95 96 97 VINT0 VINT1 VINT2 5 57 98 VIO0 VIO1 VIO2 VIO3 26 38 51 88 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 21 31 44 62 69 75 84 100 1 3 5 7 9 2 4 6 8 10 SDA SCL TP(BLUE) TP(BLUE) TP7 TP8 HEADER 5X2 1 C SRC_LRCK P_SRC_RESET P_SRC_SMUTE TESTI2 CLKO1 SDOUT5 SDOUT4 SDOUT3 SDOUT2 SDOUT1 BITCLK_O LRCLK_O CKM1 1 6 8 9 10 11 12 13 14 15 16 17 18 20 25 28 29 30 32 33 35 36 37 39 40 41 42 49 50 52 53 54 55 56 58 C 1 SMUX2_MCLK SMUX2_BICK SMUX2_LRCK SMUX2_DAT1 U18 DVDD_3.3V SMUX2_DAT2 R84 R85 R87 100 100 100 R89 R88 R90 R91 R93 R95 R94 100 100 100 100 100 100 100 X_SO X_SI X_RQ_N SDIN1 SDIN2 SDIN3 SDIN4 SDIN5 BITCLK_I LRCLK_I P_CK_RESET P_AD_RESET P_DSP_RESET SDOUTA1 SDOUT6 CLKO2 JX2 JX1 JX0 R83 4.7k R86 100 X_SDA X_SCLK R92 10k DVDD_5V B DVDD_3.3V C150 0.1uF C151 0.1uF C152 0.1uF C153 0.1uF + C154 10uF C155 0.1uF C156 0.1uF C157 0.1uF + C158 10uF JP21 2 4 6 8 10 TCK TDI TDO TMS VDD_JTAG HEADER 5X2 CKM0 CKM2 PC_SO RX_DAT DVDD_5V C159 R101 SRC_BICK (open) W IRE4 W IRE wired short 0.1uF 100 TP(BLACK) TP9 1 1 3 5 7 9 XC95108 A A Title <Title> Size A3 Date: 5 4 3 2 Document Number <Doc> W ednesday, July 12, 2006 Rev <RevCode> Sheet 1 8 of 8 5 4 + C1 100uF(A) AVDD_SRC D + AVDD_AD 2 1 JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 AINRN AINRP AINLN AINLP AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8 AVDD_AD C2 0.1uF AVDD_SRC + C3 10uF C4 0.1uF + C5 10uF C6 0.1uF + C7 10uF D C9 + C8 100uF(A) 3 HEADER 25X2 AVSS_CHIP TP(BLUE) TP1 10uF 1.5k(DIP) 0.1uF R2 TESTO R1 VCOM C11 AVDD_AD AVDD_AD AVSS_CHIP 1 C10 1.5k(DIP) 76 74 AVSS_CHIP 73 AVDD_SRC JP2 TEST2 P_SRC_SMUTE P_SRC_RST SDA SRC_LRCK SRC_BICK SDIN1 JX0 JX1 JX2 R3 72 71 70 AVSS_CHIP 69 DVDD_CHIP 68 DVSS_CHIP 67 DVDD18_CHIP 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 100 66 65 64 DVDD18_CHIP 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C + C14 100uF(A) DVSS_CHIP HEADER 15X2 63 62 61 60 59 58 DVDD18_CHIP 57 DVSS_CHIP 56 DVDD_CHIP JP4 HEADER 2 1 2 77 AINM DVDD_6 75 CLKO2 55 54 R5 100 SDOUT6 53 R7 100 SDOUTA1 52 STO 51 RDY SO 50 49 DVDD_CHIP DVSS_6 DVDD18_6 48 DVSS_CHIP SCLK/SCL 46 RQ_N/CAD1 P_DSPRST SI/CAD0 45 47 100 100 RDY DVDD18_CHIP 12.288MHz P_ADRST SDOUT3 C13 8.2nF(DIP) TESTO 78 79 AINL4 AINR4 81 82 80 AINR3 AINL3 AINR2 83 AINL2 AVDD3 84 85 87 86 VCOM VREFH AVSS3 VREFL 90 88 91 89 AINRN AINLP AINLN AINRP 93 92 94 AINL5 AINR5 95 96 AINL6 STO X'TAL1 R11 R12 AINR6 SDOUT2 44 C17 22pF(DIP) 98 SDOUTA1 43 R10 0(DIP) SDOUT6 SDOUT1 26 C16 97 BITCLK_O B 22pF(DIP) AINL7 CLKO2 P_CKRST 25 DVDD_7 LRCLK_O INIT_RESET 100 DVSS_7 DVDD3 42 R9 JP5 DVSS3 41 24 DVDD18_7 40 100 DVDD18_3 DVSS_5 R8 JX2 DVDD18_5 23 CKM2 39 100 JX1 SDOUT4 default 1-2short 22 R6 CKM0 DVSS_CHIP 1 2 3 100 JX0 LRCLK_I HEADER 3 R4 CKM1 38 21 SDIN1 37 20 SRC_BICK DVDD18_2 DVDD18_CHIP DVDD_CHIP DVSS2 BITCLK_I 19 SRC_LRCK SDIN5 DVSS_CHIP SDA XTO SDIN4 17 DVDD18_CHIP 18 AK7780 XTI 36 16 HEADER 15X2 P_SRCRST 35 15 DVDD18_8 DVSS1 SDIN3 13 DVDD18_CHIP 14 DVDD1 SDIN2 DVSS_CHIP DVSS_8 34 12 DVDD_8 BVSS1 33 XTO BVSS2 SRCSET0 32 11 SRCSET1 DVDD18_4 10 XTI P_SRCSMUTE DVSS_4 9 DVSS_CHIP I2CSEL 31 DVSS_CHIP DVDD_CHIP TEST2 DVDD18_CHIP C15 100uF(A) TEST1 I2CSEL SRCSET1 SRCSET0 MCLK CKM1 CKM0 CKM2 LRCLK_O BITCLK_O SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TEST1 DVDD_4 + 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 AVDD2 CLKO1 DVDD18_CHIP 8 AVDD1 30 AVSS_CHIP JP3 AVSS2 29 7 C SRC_LFLT 28 6 C12 1.5uF(DIP) AVSS1 DVSS_CHIP 5 LFLT DVDD_CHIP 4 AINR7 100 AINL8 3 SDOUT5 2 AVDD_AD 27 1 AVSS_CHIP AINR8 U1 99 47nF(DIP) B AK7780 HEADER 2 1 2 DVDD_CHIP JP6 TP(BLACK) TP2 C18 0.1uF JP7 1 DVDD_CHIP + C27 100uF(A) DVSS_CHIP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R13 100 SDIN2 SDIN3 SDIN4 SDIN5 BITCLK_I LRCLK_I INIT_RESET P_CKRST P_ADRST P_DSPRST RQ_N SI SCLK SO CLKO1 (9,10) + C20 10uF (9,10) C21 0.1uF (19,20) + C19 10uF (19,20) C22 0.1uF (29,30) + C23 10uF (29,30) C24 0.1uF (48,49) + C25 10uF (56,57) C26 0.1uF C28 0.1uF (68,69) (56,57) DVDD18_CHIP C29 0.1uF + C30 10uF C31 0.1uF + C32 10uF C33 0.1uF C34 0.1uF + C35 10uF C36 0.1uF + C37 10uF C38 0.1uF C39 0.1uF + C40 10uF HEADER 15X2 (13,14) (13,14) (18,19) (18,19) (30,31) (38,39) (38,39) (47,48) (57,58) (47,48) (67,68) (67,68) A A Title chip Size A2 Date: 5 4 3 2 Document Number <Doc> Rev NC Wednesday, July 12, 2006 1 Sheet 1 of 1 5 4 3 2 1 JP1 + C1 100uF(A) AVDD_SRC D + AVDD_AD C8 100uF(A) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 AINRN AINRP AINLN AINLP AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8 AVDD_AD C2 0.1uF AVDD_SRC + C3 10uF C4 0.1uF + C5 10uF C6 0.1uF + C7 10uF D C9 + 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 HEADER 25X2 AVSS_CHIP TP(BLUE) TP1 10uF 1.5k(DIP) 0.1uF R1 TESTO R2 VCOM C11 AVDD_AD AVDD_AD AVSS_CHIP 1 C10 1.5k(DIP) 76 AVSS_CHIP AVDD_SRC default short JP2 TEST2 P_SRC_SMUTE P_SRC_RST SDA SRC_LRCK SRC_BICK SDIN1 JX0 JX1 JX2 R3 72 71 70 BVSS2 69 DVDD_CHIP 68 DVSS_CHIP AVSS_CHIP 67 DVDD18_CHIP 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 100 66 65 R4 0(DIP) 64 R5 0(DIP) 63 R6 0(DIP) DVDD18_CHIP 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C + C15 100uF(A) DVSS_CHIP HEADER 15X2 62 61 60 59 DVDD18_CHIP 57 DVSS_CHIP 56 DVDD_CHIP JP6 HEADER 2 1 2 58 CLKO2 55 54 R8 100 SDOUT6 53 R10 100 SDOUTA1 52 STO 51 RDY SO DVDD_6 74 73 B 50 49 DVDD_CHIP DVSS_6 DVDD18_6 48 SI/CAD0 RQ_N/CAD1 P_DSPRST SCLK/SCL 46 45 DVSS_CHIP 100 100 RDY 47 12.288MHz 44 C20 22pF(DIP) P_ADRST SDOUT3 75 2 1 77 AINM TESTO 78 79 AINL4 AINR4 81 82 80 AINR3 AINL3 AINR2 83 AINL2 AVDD3 84 85 87 86 VCOM VREFH AVSS3 VREFL 90 88 91 89 AINRN AINLP AINLN AINRP 94 92 93 AINL5 AINR5 95 96 AINL6 STO X'TAL1 R14 R15 AINR6 98 SDOUT2 DVDD18_CHIP 22pF(DIP) 97 SDOUTA1 26 R13 0(DIP) AINL7 SDOUT1 B C19 SDOUT6 43 25 JP7 BITCLK_O P_CKRST 24 100 CLKO2 INIT_RESET 100 R12 DVDD_7 LRCLK_O 42 R11 DVDD3 41 23 DVSS_7 40 100 DVDD18_7 DVSS3 SDOUT4 default 1-2short R9 DVDD18_3 DVSS_5 1 2 3 JX2 DVDD18_5 HEADER 3 22 CKM2 39 21 JX1 DVSS_CHIP 20 100 CKM0 LRCLK_I DVDD_CHIP R7 JX0 38 19 SDIN1 CKM1 37 DVSS_CHIP SRC_BICK DVDD18_2 DVDD18_CHIP DVDD18_CHIP 18 DVSS2 BITCLK_I 17 SRC_LRCK SDIN5 16 HEADER 15X2 SDA XTO SDIN4 15 AK7780 XTI 36 DVDD18_CHIP 14 P_SRCRST 35 13 DVSS1 SDIN3 12 DVDD18_8 SDIN2 11 XTO DVSS_8 DVDD1 34 XTI DVSS_CHIP BVSS1 33 10 32 9 DVSS_CHIP DVDD18_4 DVDD_CHIP 1 2 JP3 HEADER 2 DVDD_8 DVSS_4 DVSS_CHIP default short BVSS2 SRCSET0 31 C13 100uF(A) TEST1 I2CSEL SRCSET1 SRCSET0 MCLK CKM1 CKM0 CKM2 LRCLK_O BITCLK_O SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SRCSET1 DVDD18_CHIP + 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 P_SRCSMUTE DVDD_4 8 JP5 DVDD18_CHIP I2CSEL CLKO1 7 BVSS1 TEST2 30 AVSS_CHIP TEST1 29 6 C AVDD2 28 5 AVSS2 AVDD1 DVSS_CHIP 4 C14 8.2nF(DIP) JP4 HEADER 2 AVSS1 DVDD_CHIP 3 AINR7 100 AINL8 2 AVDD_AD C12 1.5uF(DIP) SRC_LFLT SDOUT5 AVSS_CHIP LFLT 27 1 AINR8 U1 99 47nF(DIP) C16 0uF(DIP) AK7780 C17 0uF(DIP) C18 0uF(DIP) HEADER 2 1 2 DVDD_CHIP JP8 TP(BLACK) TP2 C21 0.1uF JP9 1 DVDD_CHIP + C31 100uF(A) DVSS_CHIP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R16 100 SDIN2 SDIN3 SDIN4 SDIN5 BITCLK_I LRCLK_I INIT_RESET P_CKRST P_ADRST P_DSPRST RQ_N SI SCLK SO CLKO1 (9,10) R17 R18 0(DIP) 0(DIP) R21 R19 R20 0(DIP) 0(DIP) 0(DIP) + C27 10uF (9,10) C22 0.1uF (19,20) + C28 10uF (19,20) C29 0.1uF (29,30) + C23 10uF (29,30) C24 0.1uF (48,49) + C25 10uF (56,57) C30 0.1uF (56,57) C26 0.1uF (68,69) DVDD18_CHIP C32 0.1uF + C33 10uF C34 0.1uF + C35 10uF C36 0.1uF C37 0.1uF + C38 10uF C39 0.1uF + C40 10uF C41 0.1uF C42 0.1uF + C43 10uF HEADER 15X2 (13,14) A C44 0uF(DIP) C45 0uF(DIP) C46 0uF(DIP) C47 0uF(DIP) (13,14) (18,19) (18,19) (30,31) (38,39) (38,39) (47,48) (47,48) (57,58) (67,68) (67,68) A C48 0uF(DIP) Title Socket Size A2 Date: 5 4 3 2 Document Number <Doc> Rev NC Wednesday, July 12, 2006 1 Sheet 1 of 1