Mitel MH89760BN St-busâ ¢ family t1/esf framer & interface preliminary information Datasheet


ST-BUS FAMILY MH89760B
T1/ESF Framer & Interface
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ISSUE 5
Complete interface to a bidirectional T1 link
D3/D4 or ESF framing and SLC-96 compatible
Two frame elastic buffer with 32µs jitter buffer
Insertion and detection of A, B, C, D bits
Signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow and blue alarm signal capabilities
Bipolar violation count, FT error count, CRC
error count
Frame and superframe sync. signals, Tx and Rx
Per channel, overall, and remote loop around
8 kHz synchronization output
Digital phase detector between T1 line and STBUS
ST-BUS compatible
Pin compatible with the MH89760
Inductorless clock recovery
Loss of Signal (LOS) indication
Available in standard, narrow and surface
mount formats
May 1995
Ordering Information
MH89760B
MH89760BN
MH89760BS
40 Pin DIL Hybrid 1.3" row pitch
40 Pin DIL Hybrid 0.8" row pitch
40 Pin Surface Mount Hybrid
0°C to 70°C
Description
The MH89760B is a complete T1 interface solution,
meeting the Extended Super Frame (ESF), D3/D4
and SLC-96 formats. The MH89760B interfaces to
the DS11.544 Mbit/sec digital trunk.
The MH89760B is a pin-compatible enhancement of
the MH89760, permitting the removal of the tuneable
inductor and inclusion of the external NAND gate
used for generating RxD.
Applications
•
•
•
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
TxSF
C2i
F0i
RxSF
DSTo
C1.5i
ST-BUS
Timing
Circuitry
CSTi0
CSTi1
CSTo
DS1
LINK
INTERFACE
Data
Interface
DSTi
RxFDLClk
RxFDL
1544-2048
Two Frame
Elastic
Buffer
Transmitter
2048 - 1544
Converter
Receiver
Serial
Control
Interface
ABCD
Signalling RAM
Clock
Extractor
VDD
XCtl
XSt
Control
Logic
Phase
Detector
DS1
Counter
TxFDLClk
TxFDL
OUTA
OUTB
RxA
RxT
LOS
RxR
RxB
E1.5o
E8Ko
VSS
Figure 1 - Functional Block Diagram
4-55
MH89760B
Preliminary Information
NC
E1.5o
VDD
RxA
RxT
RxR
RxB
NC
CSTi1
CSTi0
E8Ko
XCtl
XSt
CSTo
NC
DSTi
C2i
E1.5o
F0i
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
LOS
NC
TxFDL
NC
TxFDLClk
VSS
RxFDLClk
DSTo
RxFDL
OUTB
C1.5i
RxSF
TxSF
OUTA
NC
NC
NC
VSS
Figure 2 - Pin Connections
Pin Description
Pin #
Name
2
NC
3
E1.5o
4
VDD
System Power Supply. +5V.
5
RxA
Received A (Output): The bipolar DS1 signal received by the device at RxR and RxT is
converted to a unipolar format and output at this pin.
6
7
RxT
RxR
Receive Tip and Ring Inputs: Bipolar split phase inputs designed to be connected
directly to the input transformer. Impedance to ground is approximately 1kΩ.
Impedance between pins=430Ω.
8
RxB
Received B (Output): The bipolar DS1 signal received by the device at RxR and RxT is
converted to a unipolar format and output at this pin.
9
NC
No Connection.
10
CSTi1
Control ST-BUS Input #1: A 2048 kbit/s serial control stream which carries 24 perchannel control words.
11
CSTi0
Control ST-BUS Input #0: A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
12
E8Ko
8 kHz Extracted Clock (Output): This is an 8 kHz output generated by dividing the
extracted 1.544 MHz clock by 193 and aligning it with the received DS1 frame. The 8
kHz signal can be used for synchronizing system clocks to the extracted 1.544 MHz
clock. When digital loopback is enabled, the 8kHz is derived from C1.5.
13
XCtl
External Control (Output): This is an uncommitted external output pin which is set or
reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per
frame.
14
XSt
External Status (Schmitt Trigger Input): The state of this pin is sampled once per
frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.
15
CSTo
16
NC
4-56
Description
No Connection.
1.544 MHz Extracted Clock (Output): This clock is extracted by the device from the
received DS1 signal. It is used internally to clock in data received at RxT and RxR.
Control ST-BUS Output: This is a 2048 kbit/s serial control stream which provides the
24 per-channel status words, and two master status words.
No Connection.
MH89760B
Preliminary Information
Pin Description (Continued)
Pin #
Name
Description
17
DSTi
Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 24
PCM or data channels to be transmitted on the T1 trunk.
18
C2i
2.048 MHz System Clock (Input): This is the master clock for the ST-BUS section of
the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the
rising edge.
19
E1.5o
20
F0i
Frame Pulse Input: This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
21
VSS
System ground.
22-24
NC
No Connection.
25
OUTA
Output A (Open Collector Output): This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
26
TxSF
Transmit Superframe Pulse Input: A low pulse applied at this pin will determine the
start of the next transmit superframe as illustrated in Figure 20. The device will free run if
this pin is held high.
27
RxSF
Received Superframe Pulse Output: A pulse output on this pin indicates that the next
frame of data on the ST-BUS is from frame 1 of the received superframe. The period is
12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is
synchronized to received DS1 signal.
28
C1.5i
1.544 MHz Clock Input: The rising edge of this clock is used to output data on OUTA,
OUTB. C1.5i must be phase-locked to the C2i system clock.
29
OUTB
Output B (Open Collector Output): This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
30
RxFDL
Received Facility Data Link (Output): A 4 kbit/s serial output stream that is
demultiplexed from the FDL bits in ESF mode, or the received FS bit pattern when in
SLC96 mode. It is clocked out on the rising edge of RxFDLClk.
31
DSTo
32
RxFDLClk
33
VSS
34
TxFDLClk
35
NC
36
TxFDL
37
NC
No Connection.
38
LOS
Loss of Signal (Output): This pin goes high when 128 contiguous ZEROs are received
on the RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is
reset when 48 ones are received in a two T1-frame period.
39
NC
No Connection.
40
NC
No Connection.
1.544 MHz Extracted Clock (Output): Internally connected to Pin 3.
Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 24 PCM or
data channels received from the DS1 line.
Receive Facility Data Link Clock Output: A 4 kHz clock used to output FDL
information on RxFDL. Data is clocked out on the rising edge of the clock.
No Connection.
Transmit Facility Data Link Clock Output: A 4 kHz clock used to input FDL
information on TxFDL. Data is clocked in on the rising edge of the clock.
No Connection.
Transmit Facility Data Link (Input): A 4 kbit/s serial input stream that is muxed into the
FDL bits in the ESF mode, or the FS pattern when in SLC96 mode. It is clocked in on the
rising edge of TxFDLClk.
4-57
4-58
1
2
3
3
X
3
3
3
3
4
5
4
5
5
6
5
6
4
5
6
4
5
6
PC PC PC
CW CW CW
1
1
1
4
X
4
X
7
X
6
7
6
7
8
10
1
2
3
0
1
2
PC PC PC
CW CW CW
2
2
2
3
X
4
1
2
3
3
0
1
2
PCS PCS PCS PS
W
W
W W
4
5
6
4
5
6
PCS PCS PCS
W
W
W
6
7
X
7
X
12
X
10
13
11
14
X = UNUSED
12
15
16
X
13
17
14
18
15
19
20
X
16
21
8
10
7
8
9
10
13
11
14
12
15
16
X
13
17
14
18
15
19
20
X
16
21
11
X
10
11
12
12
13
14
PC PC PC
CW CW CW
1
1
1
15
MC
W1
13
14
15
16
17
18
PC PC PC
CW CW CW
1
1
1
19
X
9
11
X
10
11
12
12
13
14
PC PC PC
CW CW CW
2
2
2
15
X
13
14
15
16
17
18
PC PC PC
CW CW CW
2
2
2
19
X
8
9
11
X
10
11
12
14
15
19
X
16
17
18
16
17
16
17
18
20
21
22
PCS PCS PCS
W
W
W
18
20
21
22
PC PC PC
CW CW CW
2
2
2
Figure 3 - ST-BUS Channel Allocations
ST-BUS VERSUS DS1 CHANNEL STATUS
13
15
12
13
14
16
17
18
PCS PCS PCS MS PCS PCS PCS
W
W
W W1 W
W
W
17
22
17
22
20
21
22
PC PC PC
CW CW CW
1
1
1
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
8
8
9
10
PCS PCS PCS
W
W
W
7
12
X
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
8
9
10
PC PC PC
CW CW CW
2
2
2
7
9
11
ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED
7
9
PCSW=Per Channel Status Word, PSW=Phase Status Word, MSW=Master Status Word
DS1
CSTo
5
4
5
6
PC PC PC
CW CW CW
2
2
2
PCCW=Per Channel Control Word
DS1
CSTi1
9
11
ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED
7
9
8
9
10
PC PC PC
CW CW CW
1
1
1
8
X
8
X
PCCW=Per Channel Control Word, MCW1/2=Master Control Word 1/2
DS1
0
1
2
PC PC PC
CW CW CW
1
1
1
CSTi0
2
1
2
2
2
DS1
1
0
X
DSTo
1
1
0
X
DS1
DSTi
23
X
23
X
23
X
18
23
18
23
19
25
19
25
20
26
20
26
20
21
20
21
19
20
21
24
25
26
PCS PCS PCS
W
W
W
19
24
25
26
PC PC PC
CW CW CW
2
2
2
19
24
25
26
PC PC PC
CW CW CW
1
1
1
24
X
24
X
27
X
27
X
27
X
21
27
21
27
22
29
22
29
23
30
23
30
23
24
23
24
31
X
31
MC
W2
24
31
24
31
22
23
24
31
28
29
30
PCS PCS PCS MS
W
W
W W2
22
28
29
30
PC PC PC
CW CW CW
2
2
2
22
28
29
30
PC PC PC
CW CW CW
1
1
1
28
X
28
X
MH89760B
Preliminary Information
MH89760B
Preliminary Information
Functional Description
The MH89760B is a thick film hybrid solution for a T1
interface.
All of the formatting and signalling
insertion and detection is done by the device.
Various programmable options in the device include:
ESF, D3/D4 or SLC-96 mode, common channel or
robbed bit signalling, zero code suppression, alarms,
and local and remote loopback. The MH89760B also
has built in bipolar line drivers and receivers and a
clock extraction circuit.
All data and control information is communicated to
the MH89760B via 2048 kbit/s serial streams
conforming to Mitel’s ST-BUS format.
The ST-BUS is a TDM serial bus that operates at
2048 kbits/s. The serial streams are divided into 125
µsec frames that are made up of 32 8-bit channels. A
serial stream that is made up of these 32 8 bit
channels is known as an ST-BUS stream, and one of
these 64 kbit/s channels is known as an ST-BUS
channel.
The system side of the MH89760B is made up of STBUS inputs and outputs, i.e., control inputs and
outputs (CSTi/o) and data inputs and outputs
(DSTi/o). These signals are functionally represented
in Figure 32. The DS1 line side of the device is made
up of split phase inputs (RxT, RxR) and outputs
(OUTA, OUTB) which can be connected to line
coupling transformers. Functional
transmit
and
receive timing is shown in Figures 33 and 34.
Data for transmission on the DS1 line is clocked
serially into the device at the DSTi pin. The DSTi pin
accepts a 32 channel time division multiplexed STBUS stream. Data is clocked in with the falling edge
of the C2i clock. ST-BUS frame boundaries are
defined by the frame pulse applied at the F0i pin.
Only 24 of the available 32 channels on the ST-BUS
serial stream are actually transmitted on the DS1
side. The unused 8 channels are ignored by the
device.
Data received from the DS1 line is clocked out of the
device in a similar manner at the DSTo pin. Data is
clocked out on the rising edge of the C2i clock. Only
24 of the 32 channels output by the device contain
the information from the DS1 line. The DSTo pin is,
however, actively driven during the unused channel
timeslots. Figure 3 shows the correspondence
between the DS1 channels and the ST-BUS
channels.
All control and monitoring of the device is
accomplished through two ST-BUS serial control
inputs and one serial control output. Control ST-BUS
input number 0 (CSTi0) accepts an ST-BUS serial
stream which contains the 24 per channel control
words and two master control words. The per channel
control words relate directly to the 24 information
channels output on the DS1 side. The master control
words affect operation of the whole device. Control
ST-BUS input number 1 (CSTi1) accepts an ST-BUS
stream containing the A, B, C and D signalling bits.
The relationship between the CSTi channels and the
controlled DS0 channels is shown in Figure 3. Status
and signalling information is received from the device
via the control ST-BUS output (CSTo). This serial
output stream contains two master status words, 24
per channel status words and one Phase Status
Word. Figure 3 shows the correspondence between
the received DS1 channels and the status words.
Detailed information on the operation of the control
interface is presented below.
Programmable Features
The main features in the device are programmed
through two master control words which occupy
channels 15 and 31 in Control ST-BUS input stream
number 0 (CSTi0). These two eight bit words are
used to:
•
•
•
Select the different operating modes of the
device ESF, D3/D4 or SLC-96.
Activate the features that are needed in a
certain application; common channel signalling,
zero code suppression, signalling debounce,
etc.
Turn on in service alarms, diagnostic loop
arounds, and the external control function.
Tables 1 and 2 contain a complete explanation of the
function of the different bits in Master Control Words
1 and 2.
Major Operating Modes
The major operating modes of the device are
enabled by bits 2 and 4 of Master Control Word 2.
The Extended Superframe (ESF) mode is enabled
when bit 4 is set high. Bit 2 has no effect in this
mode. The ESF mode enables the transmission of
the S bit pattern shown in Table 3. This includes the
frame/superframe pattern, the CRC-6, and the
Facility Data Link (FDL). The device generates the
frame/multiframe pattern and calculates the CRC for
each superframe. The data clocked into the device
on the TxFDL pin is incorporated into the FDL. ESF
mode will also insert A, B, C and D signalling bits into
the 24 frame multiframe. The DS1 frame begins after
approximately 25 periods of the C1.5i clock from the
F0i frame pulse.
4-59
MH89760B
Preliminary Information
.
Bit
Name
Description
7
Debounce
When set the received A, B, C and D signalling bits are reported directly in the per
channel status words output at CSTo. When clear, the signalling bits are debounced for
6 to 9 ms before they are placed on CSTo.
6
TSPZCS
Transparent Zero Code Suppression. When this bit is set, no zero code suppression is
implemented.
5
B8ZS
Binary Eight Zero Suppression. When this bit is set, B8ZS zero code suppression is
enabled. When clear, bit 7 in data channels containing all zeros is forced high before
being transmitted on the DS1 side. This bit is inactive if the TSPZCS bit is set.
4
8kHSel
8 kHz Output Select. When set, the E8Ko pin is held high. When clear, the E8Ko
generates an 8 kHz output derived from the extracted 1.544 MHz clock or C1.5i clock
(see Pin Description for E8Ko).
3
XCtl
External Control Pin. When set, the XCtl pin is held high. When clear, XCtl is held low.
2
ESFYLW
ESF Yellow Alarm. Valid only in ESF mode. When set, a sequence of eight 1’s followed
by eight 0’s is sent in the FDL bit positions. When clear, the FDL bit contains data input at
the TxFDL pin.
1
Robbed bit
When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When
clear, A, B, C and D signalling bits are inserted into bit position 8 of all DS0 channels in
every 6th frame.
0
YLALR
Yellow Alarm. When set, bit 2 of all DS0 channels is set low. When clear, bit 2 operates
normally.
Table 1. Master Control Word 1 (Channel 15, CSTi0)
Bit
Name
Description
7
RMLOOP
Remote Loopback. When set, the data received at RxR and RxT is looped back to OUTB
and OUTA respectively. The data is clocked into the device with the extracted 1.544 MHz
clock. The device still monitors the received data and outputs it at DSTo. The device
operates normally when the bit is clear.
6
DGLOOP
Digital Loopback. When set, the data input on DSTi is looped around to DSTo. The
normal received data on RxR and RxT is ignored. However, the data input at DSTi is still
transmitted on OUTA and OUTB. The device frames up on the looped data using the C1.5i
clock.
5
ALL1'S
All One’s Alarm. When set, the chip transmits an unframed all 1's signal on OUTA and
OUTB.
4
ESF/D4
ESF/D4 Select. When set, the device is in ESF mode. When clear, the device is in D3/D4
mode.
3
ReFR
Reframe. If set for at least one frame and then cleared, the chip will begin to search for a
new frame position. Only the change from high to low will cause a reframe, not a
continuous low level.
2
SLC-96
SLC-96 Mode Select. The chip is in SLC-96 mode when this bit is set. This enables input
and output of the FS bit pattern using the same pins as the facility data link in ESF mode.
The chip will use the same framing algorithm as D3/D4 mode. The user must insert the
valid FS bits in 2 out of 6 superframes to allow the receiver to find superframe sync, and
the transmitter to insert A and B bits in every 6th frame. The SLC-96 FDL completely
replaces the FS pattern in the outgoing S bit position. Inactive in ESF mode.
1
CRC/MIMIC
In ESF mode, when set, the chip disregards the CRC calculation during synchronization.
When clear, the device will check for a correct CRC before going into synchronization. In
D3/D4 mode, when set, the device will synchronize on the first correct S-bit pattern
detected. When this bit is clear, the device will not synchronize if it has detected more than
one candidate for the frame alignment pattern (i.e., a mimic).
0
Maint.
4-60
Maintenance Mode. When set, the device will declare itself out-of-sync if 4 out of 12
consecutive FT bits are in error. When clear, the out-of-sync threshold is 2 errors in 4 FT
bits. In this mode, four consecutive bits following an errored FT bit are examined.
Table 2. Master Control Word 2 (Channel 31, CSTi0)
MH89760B
Preliminary Information
Frame #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FPS
FDL
CRC
Signalling †
X
CB1
X
0
X
CB2
A
X
0
X
CB3
X
1
B
X
Frame #
FT
1
2
3
4
5
6
7
8
9
10
11
12
1
FS
Signalling †
0
0
0
1
1
A
0
1
1
1
0
0
B
Table 4. D3/D4 Framer
† These signalling bits are only valid if the robbed bit signalling is
active.
CB4
X
0
X
CB5
C
X
1
X
Standard D3/D4 framing is enabled when bit 4 of
Master Control Word 2 is reset (logic 0). In this mode
the device searches for and inserts the framing
pattern shown in Table 4. This mode only supports
AB bit signalling, and does not contain a CRC check.
CB6
X
1
D
Table 3. ESF Frame Pattern
† These signalling bits are only valid if the robbed bit signalling is
active.
During synchronization the receiver locks on to the
incoming frame, calculates the CRC and compares it
to the CRC received in the next multiframe. The
device will not declare itself to be in synchronization unless a valid framing pattern in the S-bit is
detected and a correct CRC is received. The CRC
check in this case provides protection against false
framing. The CRC check can be turned off by setting
bit 1 in Master Control Word 2.
The device can be forced to resynchronize itself. If
Bit 3 in Master Control Word 2 is set for one frame
and then subsequently reset, the device will start to
search for a new frame position. The decision to
reframe is made by the user’s system processor on
the basis of the status conditions detected in the
received master status words. This may include
consideration of the number of errors in the received
CRC in conjunction with an indication of the
presence of a mimic. When the device attains
synchronization the mimic bit in Master Status Word
1 is set if the device found another possible
candidate when it was searching for the framing
pattern.
Note that the device will resynchronize automatically
if the errors in the terminal framing pattern (FT or
FPS) exceed the threshold set with bit 0 in Master
Control Word 2.
The CRC/MIMIC bit in Master Control Word 2, when
set high, allows the device to synchronize in the
presence of a mimic. If this bit is reset, the device will
not synchronize in the presence of a mimic. (Also
refer to section on Framing Algorithm.)
In the D3/D4 mode the device can also be made
compatible with SLC-96 by setting bit two of Master
Control Word 2. This allows the user to insert and
extract the signalling framing pattern on the DS1 bit
stream using the FDL input and output pins. The
user must format this 4 kbits of information externally
to meet all of the requirements of the SLC-96
specification (see Table 5). The device multiplexes
and demultiplexes this information into the proper
position. This mode of operation can also be used for
any other application that uses all or part of the
signalling framing pattern. As long as the serial
stream clocked into the TxFDL contains two proper
sets of consecutive synchronization bits (as shown in
Table 5 for frames 1 to 24), the device will be
able to insert and extract the A, B signalling bits.
The TxSF pin should be held high in this mode.
Superframe boundaries cannot be defined by a pulse
on this input. The RxSF output functions normally
and indicates the superframe boundaries based on
the synchronization pattern in the FS received bit
position.
Zero Code Suppression
The combination of bits 5 and 6 in Master Control
Word 1 allow one of three zero code suppression
schemes to be selected. The three choices are:
none, binary 8 zero suppression (B8ZS), or jammed
bit (bit 7 forced high). No zero code suppression
4-61
MH89760B
Frame
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
FT
Preliminary Information
FS†
1
0
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
X
0
X
1
X
0
X
1
X
0
X
Frame
FT
#
37
1
38
39
0
40
41
1
42
43
0
44
45
1
46
47
0
Resynchronization
48
Data
49
1
Bits
50
51
0
52
53
1
54
55
0
56
57
1
58
59
0
60
61
1
62
63
0
64
65
1
X =Concentrator
66
Field Bits
67
0
68
69
1
70
71
0
72
Table 5. SLC-96 Framing Pattern
Notes
FS†
Notes
X
X
X = Concentrator
Field Bits
X
X
X
S
S = Spoiler Bits
S
S
C
C = Maintenance
Field
Bits
C
C
A
A = Alarm Field
Bits
A
L
L = Line Switch
Field Bits
L
L
L
S = Spoiler Bits
S
† Note: The FS pattern has to be supplied by the user.
DATA
B
0
0
0
V
0
B
B8ZS
B
V
B
V = Violation
B = Bipolar
0 = No Pulse
0
0
B
0
0
V
B
B8ZS
B
V
Figure 4 - B8ZS Output Coding
4-62
B
MH89760B
Preliminary Information
allows the device to interface with systems that have
already applied some form of zero code suppression
to the data input on DSTi. B8ZS zero code
suppression replaces all strings of 8 zeros with a
known bit pattern and a specific pattern of bipolar
violations. This bit pattern and violation pattern is
shown in Figure 4. The receiver monitors the
received bit pattern and the bipolar violation pattern
and replaces all matching strings with 8 zeros.
Loopback Modes
Remote and digital loopback modes are enabled by
bits 6 and 7 in Master Control Word 2. These modes
can be used for diagnostics in locating the source of
a fault condition. Remote loop around loops back
data received at RxR and RxT back out on OUTA
and OUTB, thus effectively sending the received
DS1 data back to the far end unaltered so that the
transmission line can be tested. The received signal
with the appropriate received channels on the DS1
side made available in the proper format at DSTo.
The digital loop around mode diverts the data
received at DSTi back out the DSTo pin. Data
received on DSTi is, however, still transmitted out via
OUTA and OUTB. This loop back mode can be used
to test the near end interface equipment when there
is no transmission line or when there is a suspected
failure of the line.
The all ones transmit alarm (also known as the blue
alarm or the keep alive signal) can be activated in
conjunction with the digital loop around so that the
transmission line sends an all 1's signal while the
normal data is looped back locally.
The MH89760B also has a per channel loopback
mode. See Table 6 and the following section for more
information.
Per Channel Control Features
In addition to the two master control words in CSTi0
there are also 24 Per Channel Control Words. These
control words only affect individual DS0 channels.
The correspondence between the channels on
CSTi0 and the affected DS0 channel is shown in Fig.
3. Each control word has three bits that enable
robbed bit signalling, DS0 channel loopback and
inversion of the DS0 channel. A full description of
each of the bits is provided in Table 6.
Transmit Signalling Bits
Control ST-BUS input number 1 (CSTi1) contains 24
additional per channel control words. These 24 STBUS channels contain the A, B, C and D signalling
bits that the device uses at transmit time. The
position of these 24 per channel control words in the
ST-BUS is shown in Figure 3 and the position of the
ABCD signalling bits is shown in Table 7. Even
though the device only inserts the signalling
information in every 6th DS1 frame this information
must be input every ST-BUS frame.
Robbed bit signalling can be disabled for all
channels on the DS1 link by bit 1 of Master Control
Word 1. It can also be disabled on a per channel
basis by bit 0 in the Per Channel Control Word 1.
Bit
Name
Description
7-3
IC
2
Polarity
When set, the applicable channel is not inverted on the transmit or the receive side of the device.
When clear, all the bits within the applicable channel are inverted both on transmit and receive
side.
1
Loop
Per Channel Loopback. When set, the received DS0 channel is replaced with the transmitted
DS0 channel. Only one DS0 channel may be looped back in this manner at a time. The
transmitted DS0 channel remains unaffected. When clear the transmit and receive DS0 sections
operate normally.
0
Data
Data Channel Enable. When set, robbed bit signalling for the applicable channel is disabled.
When clear, every 6th DS1 frame is available for robbed bit signalling. This feature is enabled
only if bit 1 in Master Control Word is low.
Internal Connections. Must be kept at 0 for normal operation.
Table 6. Per Channel Control Word 1 Input at CSTi0
Bit
Name
7-4
Unused
3
2
1-0
A
B
C, D
Description
Keep at 0 for normal operation
These are the 4 signalling bits inserted in the appropriate channels of the DS1 stream being
output from the chip, when in ESF mode. In D3/D4 modes where there are only two signalling
bits, the values of C and D are ignored.
Table 7. Per Channel Control Word 2 Input at CSTi1
4-63
MH89760B
Preliminary Information
.
Bit
Name
Description
7
YLALR
Yellow Alarm Indication. This bit is set when the chip is receiving a 0 in bit position 2 of every
DS0 channel.
6
MIMIC
This bit is set if the frame search algorithm found more than one possible frame candidate when
it went into frame synchronization.
5
ERR
Terminal Framing Bit Error. The state of this bit changes every time the chip detects 4 errors in
the FT or FPS bit pattern. The bit will not change state more than once every 96ms.
4
ESFYLW
ESF Yellow Alarm. This bit is set when the device has observed a sequence of eight one’s and
eight 0’s in the FDL bit positions.
3
MFSYNC
Multiframe Synchronization. This bit is cleared when D3/D4 multiframe synchronization has
been achieved. Applicable only in D3/D4 and SLC-96 modes of operation.
2
BPV
Bipolar Violation Count. The state of this bit changes every time the device counts 256 bipolar
violations.
1
SLIP
Slip Indication. This bit changes state every time the elastic buffer in the device performs a
controlled slip.
0
SYN
Synchronization. This bit is set when the device has not achieved synchronization. The bit is
clear when the device has synchronized to the received DS1 data stream.
Table 8. Master Status Word 1 (Channel 15, CSTo)
Bit
Name
Description
7
BlAlm
Blue Alarm. This bit is set if the receiver has detected two frames of 1’s and an out of frame
condition. It is reset by any 250 microsecond interval that contains a zero.
6
FrCnt
Frame Count. This is the ninth and most significant bit of the “Phase Status Word" (see Table
10). If the phase status word is incrementing, this bit will toggle when the phase reading exceeds
channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the reading
goes below channel 0, bit 0.
5
XSt
External Status. This bit reflects the state of the external status pin (XSt). The state of the XSt
pin is sampled once per frame.
4-3
BPVCnt
Bipolar Violation Count. These two bits change state every 128 and every 64 bipolar violations,
respectively.
2-0
CRCCNT
CRC Error Count. These three bits count received CRC errors. The counter will reset to zero
when it reaches terminal count. Valid only in ESF mode.
Table 9. Master Status Word 2 (Channel 31, CSTo)
Bit
Name
Description
7-3
ChannelCnt
Channel Count. These five bits indicate the ST-BUS channel count between the ST-BUS frame
pulse and the rising edge of E8Ko.
2-0
BitCnt
Bit Count. These three bits provide one bit resolution within the channel count described above.
Table 10. Phase Status Word (Channel 3, CSTo)
Operating Status Information
Status Information regarding the operation of the
device is output serially via the Control ST-BUS
output (CSTo). The CSTo serial stream contains
Master Status Words 1 and 2, 24 Per Channel Status
Words, and a Phase Status Word. The Master Status
Words contain all of the information needed to
determine the state of the interface and how well it is
operating. The information provided includes frame
and super frame synchronization, slip, bipolar
violation counter, alarms, CRC error count, FT error
count, synchronization pattern mimic and a phase
status word. Tables 8 and 9 give a description of each
4-64
of the bits in Master Status Words 1 and 2, and Table
10 gives a description of the Phase Status Word.
In addition, the MH89760B has a Loss of Signal
(LOS) pin that is set High when 128 consecutive
ZEROs are received. While LOS is set High, RxA and
RxB are forced High. The LOS signal goes Low when
a ONEs density on 12.5% of the bits (equivalent to 48
bits) occurs in a two DS1 frame period.
MH89760B
Preliminary Information
.
Bit
Name
7-4
Unused
3
2
1
0
A
B
C
D
Description
Unused Bits. Will be output as 0’s.
These are the 4 signalling bits as extracted from the received DS1 bit stream.
The bits are debounced for 6 to 9 ms if the debounce feature is enabled via bit 7 in Master
Control Word 1.
Table 11. Per Channel Status Word Output on CSTo
Alarm Detection
The device detects the yellow alarm for both D3/D4
frame format and ESF format. The D3/D4 yellow
alarm will be activated if a ‘0‘ is received in bit
position 2 of every DS0 channel for 600 msec. It will
be released in 200 msec after the contents of the bit
change. The alarm is detectable in the presence of
errors on the line.
The ESF yellow alarm will
become active when the device has detected a string
of eight 0’s followed by eight 1’s in the facility data
link. It is not detectable in the presence of errors on
the line. This means that the ESF yellow alarm will
drop out for relatively short periods of time, so the
system will have to integrate the ESF yellow alarm.
The blue alarm signal, in Master Status Word 2, will
also drop out if there are errors on the line.
Mimic Detection
The mimic bit in Master Status Word 1 will be set if,
during synchronization, a frame alignment pattern
(FT or FPS bit pattern) was observed in more than
one position, i.e., if more than one candidate for the
frame synchronization position was observed. It will
be reset when the device resynchronizes. The mimic
bit, the terminal framing error bit and the CRC error
counter can be used separately or together to decide
if the receiver should be forced to reframe.
Bipolar Violation Counter
The Bipolar Violation bit in Master Status Word 1 will
toggle after 256 violations have been detected in the
received signal. It has a maximum refresh time of 96
ms. This means that the bit can not change state
faster than once every 96 ms. For example, if there
are 256 violations in 80 ms the BPV bit will not
change state until 96 ms. Any more errors in that
extra 16 ms are not counted. If there are 256 errors
in 200 ms then the BPV bit will change state after
200 ms. In practical terms this puts an upper limit
on the error rate that can be calculated from the BPV
information, but this rate (1.7 X 10-3) is well above
any normal operating condition.
Bits 4 and 3 also provide bipolar violations information. Bit 4 will change state after 128 violations.
Bit 3 changes state after 64 bipolar violations. These
bits are refreshed independently and are not subject
to the 96 ms refresh rate described above.
DS1/ST-BUS Phase Difference
An indication of the phase difference between the
ST-BUS and the DS1 frame can be ascertained from
the information provided by the eight bit Phase
Status Word and the Frame Count bit. Channel three
on CSTo contains the Phase Status Word. Bits 7-3 in
this word indicate the number of ST-BUS channels
between the ST-BUS frame pulse and the rising
edge of the E8Ko signal. The remaining three bits
provide one bit resolution within the channel count
indicated by bits 7-3. The frame count bit in Master
Status Word 2 is the ninth and most significant bit of
the phase status word. It will toggle when the phase
status word increments above channel 31, bit 7 or
decrements below channel 0, bit 0. The E8Ko signal
has a specific relationship with received DS1 frame.
The rising edge of E8Ko occurs during bit 2, channel
17 of the received DS1 frame. The Phase Status
Word in conjunction with the frame count bit, can be
used to monitor the phase relationship between the
received DS1 frame and the local ST-BUS frame.
The local 2.048 MHz ST-BUS clock must be phaselocked to the 1.544 MHz clock extracted from the
received data. When the two clocks are not phaselocked, the input data rate on the DS1 side will differ
from the output data rate on the ST-BUS side. If the
average input data rate is higher than the average
output data rate, the channel count and bit count in
the phase status word will be seen to decrease over
time, indicating that the E8Ko rising edge, and
therefore the DS1 frame boundary is moving with
respect to the ST-BUS frame pulse. Conversely, a
lower average input data rate will result in an
increase in the phase reading.
In an application where it is necessary to minimize
jitter transfer from the received clock to the local
system clock, a phase lock loop with a relatively
large time constant can be implemented using
information provided by the phase status word. In
such a system, the local 2.048 MHz clock is derived
from a precision VCO. Frequency corrections are
made on the basis of the average trend observed in
4-65
MH89760B
the phase status word. For example, if the channel
count in the phase status word is seen to increase
over time, the feedback applied to the VCO is used
to decrease the system clock frequency until a
reversal in the trend is observed.
The elastic buffer in the MH89760B permits the
device to handle eight channels of jitter/wander (see
description of elastic buffer in the next section). In
order to prevent slips from occurring, the frequency
corrections would have to be implemented such that
the deviation in the phase status word is limited to
eight channels peak to peak. It is possible to use a
more sophisticated protocol which would center the
elastic buffer and permit more jitter/wander to be
handled. However, for most applications, the eight
channels of jitter/wander tolerance is acceptable.
Received Signalling Bits
The A, B, C and D signalling bits are output from the
device in the 24 Per Channel Status Words. Their
location in the serial steam output at CSTo is shown
in Figure 3 and the bit positions are shown in Table
11. The internal debouncing of the signalling bits
can be turned on or off by Master Control Word 1. In
ESF mode, A, B, C and D bits are valid. Even
though the signalling bits are only received once
every six frames the device stores the information so
that it is available on the ST-BUS every frame. The
ST-BUS will always contain the most recent
signalling bits. The state of the signalling bits is
frozen if synchronization is lost.
In D3/D4 mode, only the A and B bits are valid. The
state of the signalling bits is frozen when terminal
frame synchronization is lost. The freeze is disabled
when
the
device
regains
terminal
frame
synchronization. The signalling bits may go through
a random transition stage until the device attains
multiframe synchronization.
Preliminary Information
kHz signal is output at the E8Ko pin and can be used
to phase lock the local system C2 and the transmit
C1.5 clocks to the extracted clock.
The MH89760B requires three clock signals which
have to be generated externally.
The ST-BUS
interface on the device requires a 2.048 MHz signal
which is applied at the C2i pin and an 8
The
kHz framing signal applied at the F0i pin.
framing signal is used to delimit individual STBUS frames. Figure 19 illustrates the relationship
between the C2i and F0i signals. The F0i signal can
be derived from the 2.048 MHz C2 clock. The
transmit side of the DS1 interface requires a 1.544
MHz clock applied at C1.5i. The C1.5 and C2 clocks
must be phase locked. There must be 193 clock
cycles of the C1.5 clock for every 256 cycles of the
C2 clock in order for the 2.048 to 1.544 rate
converter to function properly.
In synchronous operation the slave end of the link
must have its C2 and C1.5 clocks phase locked to
the extracted clock. In plesiochronous clocking
applications where the master and slave end are
operating under controlled slip conditions, phase
locking to the extracted clock is generally not
required.
Mitel’s MT8941 Digital Phase Lock Loop (DPLL) can
be used to generate all timing signals required by the
MH89760B. The MT8941 has two DPLLs built into
the device. Figure 5 shows how DPLL #1 can be set
up to generate the C1.5 clock phase locked to the
F0i which in turn is derived from the same source
as the C2 clock.
Figure 5 also shows how DPLL
#2 is set up to generate the ST-BUS clocks that are
phase locked to the received data rate. If E8Ko from
the MH89760B is connected to the C8Kb input on
the MT8941, DPLL #2 in the device will generate the
ST-BUS clocks that are phase locked to the T1 line.
MT8941
DPLL #1
Clock and Framing Signals
The MH89760B has a built in clock extraction circuit
which creates a 1.544 MHz clock synchronized to
the received DS1 signal.
This clock is used
internally by the MH89760B to clock in data
received on RxT and RxR, and is also output at the
E1.5o pin.
The circuit has been designed to
operate within the constraints imposed by the
minimum 1’s density requirements, typically
specified for T1 networks (maximum of 15
consecutive 0’s).
CVb
ENCv
F0i
C12i
C1.5
+5V
MS1
C8Kb
C16i
MS0
DPLL #2
F0b
F0i
C4b
C2o
C4i
ENC4o
5V
MS2
C2i
+5V
ENC2o
MS3
Ai
Yo
Bi
The extracted clock is internally divided by 193 and
aligned with the received DS1 frame. The resulting 8
4-66
Figure 5 - MT8941 Clock Generator
MH89760B
Preliminary Information
MH89760B
MH89761
OUTA
TR1
EIT
+12V
L2
Transmit
Data
EIR
R1
1:
TxT
:0.5
C2
1:
OUTB
TxR
L1
S1
EA
C1
S2
S3
EB
S4
S5
S6
S7
E1.5o
EC
SW
RCLT
RCHT
RCLR
RCHR
Ti
TL
Ri
RL
RxA
RxB
RxT
Extracted
Clock
TR2
1:
Rx
Line
Receiver
:1
Received
Data
1:
RxR
+5V VDD
S1
S2
S4
S4
S5
S6
S7
COMPONENT VALUES:
R1 = 150Ω 1% 14 W
C1 = 0.01 µF 5% 250V
C2 = 0.47 µF 5% 100V
L1 = 33 µH 130mA
L2 = 33 µH 165 mA
TR1 = 1:1:0.5 Filtran* Part # TFS2573
TR2 = 1:1:1
Filtran* Part # TFS2574
*Filtran Ltd.
229 Colonnade Road
Nepean, Ontario
Canada K2E 7K3
613-226-1626
0-150’
CLOSE
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
150-450’
OPEN
CLOSE
OPEN
CLOSE
OPEN
CLOSE
OPEN
450-655’
OPEN
OPEN
CLOSE
OPEN
CLOSE
OPEN
CLOSE
Equalizer settings
Note: The equalizer has been optimized for 22 gauge ABAM
cable. The exact distances may vary with the type of cable and the
output transformer. Different line length settings may be
required if a transformer other than the Filtran TFS2573 is used.
Figure 6 - Input/Output Configuration
DS1 Line Interface
Line Transmitter
The transmit line interface is made up of two open
collector drivers (OUTA and OUTB) that can be
coupled to the line with a center tapped pulse
transformer (see Figure 6). A step function is applied
to the transformer when either of the transistors is
turned on. By operating in the transient portion of the
inductance response, the secondary of the
transformer produces an almost square pulse. The
capacitor and inductor on the center tap of the
transmit transformer shown in Figure 6 suppress
transients in the 12 volt supply. The series RLC
across the output of the transformer shape the pulse
to meet the AT & T or CCITT pulse templates. A
4-67
MH89760B
Preliminary Information
detailed transformer specification is presented in the
applications section of this data sheet.
To complete the interfaces to the transmit line, a preequalizer and line impedance matching network is
required. The pulse output at the transformer
secondary must be pre-equalized to drive different
lengths of cable. Mitel‘s MH89761 T1 Equalizer is
configurable to provide pre-emphasis for 0-150, 150450 and 450-655 foot lengths of 22 AWG
transmission line. A separate 6dB pad is also
provided on the MH89761 for use in implementing
external looparound. Both circuits have input and
output impedance of 100Ω. Figure 6 shows how the
equalizer is connected in a typical application. (Refer
to the MH89761 data sheet for more details.)
Line Receiver
The bipolar receiver inputs on the device, RxT and
RxR, are intended to be coupled to the line through a
center tapped pulse transformer as shown in Figure
6. The device presents a 400Ω impedance to the
receive transformer to permit matching to 100Ω
twisted pair cable. The signal detect threshold level
of the receiver circuit is set at approximately 1.5V.
There is no equalization of the received signal. The
receiver circuit is designed to accurately decode a
signal attenuated by a maximum of 3 dB from the
digital crossconnect point. The MH89760B is not
designed to directly accept a signal from the last
network repeater. Interface to the public network
generally requires a Channel Service Unit (CSU).
The receiver decodes the bipolar signal into a split
phase unipolar return to zero format. The two
resulting unipolar signals are used for bipolar
violation detection within the device and are also
output at RxA and RxB. The input jitter tolerance of
the MH89760B is shown in Figure 7.
Elastic Buffer
The MH89760B has a two frame elastic buffer which
absorbs jitter in the received DS1 signal. The buffer
is also used in the rate conversion between the
1.544 Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS
data rate.
20
J
I
T
T
E
R
A
M
P
L
I
T
U
D
E
(UI)PP
➀
10
➁
5
1.3
1
0.5
0.1
120
10
100
40k
6k
1k
10k
JITTER FREQUENCY (Hz)
➀ Typical input jitter tolerance of MH89760B receiver.
➁ Minimum jitter tolerance specified by CCITT in Recommendation I.431.
Figure 7 - Input Jitter Tolerance of the MH89760B
4-68
100k
MH89760B
Preliminary Information
The received data is written into the elastic buffer
with the extracted 1.544 MHz clock. The data is read
out of the buffer on the ST-BUS side with the system
2.048 MHz clock. The maximum delay through the
buffer is 1.3 ST-BUS frames (i.e., 42 ST-BUS
channels). The minimum delay required to avoid bus
contention in the buffer memory is two ST-BUS
channels.
Under normal operating conditions, the system C2i
clock is phase locked to the extracted E1.5o clock
using external circuitry. If the two clocks are not
phase-locked, then the rate at which the data is
being written into the device on the DS1 side may
differ from the rate at which it is being read out on
the ST-BUS side. The buffer circuit will perform a
controlled slip if the throughput delay conditions
described above are violated. For example, if the
data on the DS1 side is being written in at a rate
slower than what it is being read out on the ST-BUS
side, the delay between the received DS1 write
pointer and the ST-BUS read pointer will begin to
decrease over time. When this delay approaches the
minimum two channel threshold, the buffer will
perform a controlled slip which will reset the internal
ST-BUS read pointers so that there is exactly 34
channels delay between the two pointers. This will
result in some ST-BUS channels containing
information output in the previous frame. Repetition
of up to one DS1 frame of information is possible.
Conversely, if the data on the DS1 side is being
written into the buffer at a rate faster than that at
which it is being read out on the ST-BUS side, the
delay between the DS1 frame and the ST-BUS frame
will increase over time. A controlled slip will be
performed when the throughput delay exceeds 42
ST-BUS channels. This slip will reset the internal STBUS counters so that there is a 10 channel delay
between the DS1 write pointer and the ST-BUS read
pointer, resulting in loss of up to one frame of
received DS1 data.
Note that when the device performs a controlled slip,
the ST-BUS address pointers are repositioned so
that there is either a 10 channel or a 34 channel
delay between the input DS1 frame and the output
ST-BUS frame. Since the buffer performs a
controlled slip only if the delay exceeds 42 channels
or is less than 2 channels, there is an 8 channel
hysteresis built into the slip mechanism. The device
can, therefore, absorb 8 channels or 32.5µs of jitter
in the received signal.
There is no loss of frame sync, multiframe sync or
any errors in the signalling bits when the device
performs a slip. The information on the FDL pins in
ESF or SLC-96 mode will, however, undergo slips at
the same time.
Framing Algorithm
A state diagram of the framing algorithm is shown in
Figure 8. The dotted lines show which feature can be
switched in and out depending upon the operating
mode of the device.
In ESF mode, the framer searches for the FPS bits.
Once this pattern is detected and verified, bit 0 in
Master Status Word 1 is cleared.
When the device is operating in the D3/D4 format,
the framer searches for the FT pattern, i.e., a
repeating 1010... pattern in a specific bit position
every alternate frame. It will synchronize to this
pattern
and
declare
valid
terminal
frame
synchronization by clearing bit 0 in Master Status
Word 1. The device will subsequently initiate a
search for the FS pattern to locate the signalling
frames (see Table 4). When a correct FS pattern has
been located, bit 3 in Master Status Word 1 is
cleared indicating that the device has achieved
multiframe synchronization.
Note: the device will remain in terminal frame
synchronization even if no FS pattern can be located.
In D3/D4 format, when the CRC/MIMIC bit in Master
Control Word 1 is cleared, the device will not go into
synchronization if more than one bit position in the
frame has a repeating 1010.... pattern, i.e., if more
than one candidate for the terminal framing position
is located. The framer will continue to search until
only one terminal framing pattern candidate is
discovered. It is, therefore, possible that the device
may not synchronize at all in the presence of PCM
code sequences (e.g., sequences generated by
some types of test signals) which contain mimics of
the terminal framing pattern.
Setting CRC/MIMIC bit high will force the framer to
synchronize to the first terminal framing pattern
detected. In standard D3/D4 applications, the user’s
system software should monitor the multiframe
synchronization state indicated by bit 3 in Master
Status Word 1. Failure of the device to achieve
multiframe synchronization within 4.5ms of terminal
frame synchronization, is an indication that the
device has framed up to a terminal framing pattern
mimic and should be forced to reframe.
One of the main features of the framer is that it
performs its function "off line". That is, the framer
repositions the receive circuit only when it has
4-69
MH89760B
Preliminary Information
False Candidate
Hunt Mode
Candidate
False
Candidate
Out of
Sync.
Forced
Reframe
False
Candidate
Verify
Candidate
Candidate
CRC
Check
*
Candidate
In sync
Maintenance
Valid Candidate
Valid Candidate
New Frame Position
Resync
Receiver
* Note: Only when in ESF mode and CRC
option is enabled.
Figure 8 - Off-Line Framer State Diagram
detected a valid frame position. When the framer
exits maintenance mode the receive counters remain
where they are until the framer has found a new
frame position. This means that if the user forces a
reframe when the device was really in the right
place, there will not be any disturbance in the circuit
because the framer has no effect on the receiver
until it has found synchronization. The out of
synchronization criterion can be controlled by bit 0 in
Master Control Word 2. This bit changes the out of
frame conditions for the maintenance state.
The out of sync threshold can be changed from 2 out
of 4 errors in FT (or FPS) to 4 out of 12 errors in FT
(or FPS). The average reframe time is 24 ms for ESF
mode, and 12ms for D3/D4 modes.
Figure 9 is a bar graph which shows the probability
of achieving frame synchronization at a specific time.
4-70
The chart shows the results for ESF mode with CRC
check, and D3/D4 modes of operation. The average
reframe time with random data is 24 ms for ESF, and
13 ms for D3/D4 modes. The probability of a
reframe time of 35 ms or less is 88% for ESF
mode, and 97% for D3/D4 modes. In ESF mode it is
recommended that the CRC check be enabled
unless the line has a high error rate. With the CRC
check disabled the average reframe time is greater
because the framer must also check for mimics.
MH89760B
Preliminary Information
AAAAAAA
AAAAAAA
AAAAAAA
D4 AAAA
AAAAAAA
AAA
AAAAAAA
ESF
50
Percentage Reframe Time Probability Versus Reframe Time
With Pseudo Random Data
40
%
30
20
10
0
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AA
AAA
AA
AAA
AAA
AA
AAA
AA
AA
AAA
AAA
AA
AA
AAA
AA
AAA
AAA
AA
AA
AAA
AA AAA
AAA
AA AAA
AAA
AAA
AAA
AA
AA AAA
AAA
AA AAA
AAA
AAA
AAA
AA
AA AAA
AAA
AAA
AAA
AA
AA
AAA
AAA
AA
AAA
AAA
AA AAA
AAA
AA AAA
AAA
AA
AAA
AAA
AA AAA
AAA
AAA
AAA
AAA
AA
AA AAA
AAA
AAA
AA AAA
AAA
AAA
AA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAAAA
AAA
AAA
AAA
AAA
AAAAAAA
AAAAA
AAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAA
0
7 8
10
12
14
16
18
20
22
Reframe Time (ms)
AA
AA
AAA
AA
AAA
AAA
AA
AA
AAA
AA
AAAAAA
AA
AAA
AA AAAAAAA
AAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAA
24
26
28
30
AAA
AAA
AAA
AAA
AAA
32
34
Figure 9 - Reframe Time
Applications
1. Typical T1 Application
Figure 10 shows the external components that are
required in a typical T1 application using the
MH89760B. The MT8980 is used to control and
monitor the device as well as switch data to DSTi and
DSTo (refer to Application Note MSAN-123 for more
information on the operation of the MT8980). The
MT8952, HDLC protocol controller, is shown in this
application to illustrate how the data on the FDL
could be used. The digital phase-locked loop, the
MT8941, provides all the clocks necessary to make
a functional interface.
The 1.544 MHz clock
extracted by the MH89760B is used to clock in data
at RxT and RxR. It is also internally divided by 193
to obtain an 8 kHz clock which is output at E8Ko.
The MT8941 uses this 8 kHz signal to provide a
phase locked 2.048 MHz clock for the ST-BUS
interface and a 1.544 MHz clock for the DS1 transmit
side.
Note: the configurations shown in Figures 10 and 12
using the MT8941 may not meet specific jitter
performance requirements. A more sophisticated
PLL may be required for applications designed to
meet specific standards. Please refer to the MT8941
data sheet for further details on its jitter performance.
The split phase unipolar signals output by the
MT8976 at TxA and TxB are used by the line driver
circuit to generate a bipolar AMI signal. The line
driver is transformer coupled to an equalization
circuit and the DS1 line. Equalization of the
transmitted signal is required to meet AT & T
specifications for crossconnect compatible equipment (see AT&T Technical Advisory #34). Specifications for the input and output transformers are shown
in Figure 11. On the receive side the bipolar line
signal is converted into a unipolar format by the line
receiver circuit. The resulting split phase signals
are input at the RxA and RxB pins on the MT8976.
The signals are combined to produce a composite
return to zero signal which is clocked into the
MT8976 at RxD.
2. Interfacing the MH89760B to a Parallel Bus
The MH89760B can be interfaced to a high speed
parallel bus or to a microprocessor using the
MT8920B Parallel Access Circuit (STPA). Fig. 12
shows the MT8976 interfaced to a parallel bus
structure using two STPA‘s operating in modes 1 and
2.
The first STPA operating in mode 2 (MMS=0,
MS1=1, 24/32=0), routes data and/or voice information between the parallel telecom bus and the T1
or CEPT link via DSTi and DSTo. The second STPA,
operating in mode 1 (MMS=1) provides access from
4-71
MH89760B
Preliminary Information
To other
interfaces
From other
interfaces
C8Kb
16.384
MHz Osc.
C2o
12.352
MHz Osc.
MT8941
C4b C2o F0b F0i CVb
MH89761
} To other
MT8980
Interfaces
EIT
EIR
EA
EB
EC
SW
C4i
F0i
STo3
MT8926
STo0
STo1
STi0
STo2
STi1
STi7
E8Ko
CSTo
DSTi0
DSTi1
VDD
IRQ
1SEC
R2
STo7
µP
INT0
INT1
FDLi
VDD
MT8952
MH89760B
C1.5i
RxA
TR1
RxB
OUTA +12V
E1.5o
L2 1:
F0i
C2i
:0.5 L1
C2
CSTi1
C1
1:
E8Ko
CSTo
OUTB
TR2
TxFDL
RxT
DSTi
CSTi0
1:
DSTo
:1
RxFDLClk
RxFDL
1:
TxFDLClk
RxR
XSt LOS
RxA
RxB
EClk
F0i
C2i
CSTi1
E8Ki
CSTi0
FDLo
DSTo
D Q
D Q
CDSTo
Q
C2
Q
RCLT
RCHT
RCLR
RCHR
Ti
Ri
RxCEN
LOS
C2
Line Side
•
1 O
MH89760B
•
•
8 O
MH89760B
O 3
1 O
•
O 6
O 4
5
2
•
O 5
6 O
Input Transformer
O
O
Line Side
•
O 4
O8
Output Transformer
Units
100
100
Ω
Inductance
(1-8) >2.2
(4-8) 0.46
mH
Turns Ratio
(1-8):(3-6) 1:1
(1-8):(4-5) 1:1
(1-5):(4-8) 1.89:1
(2-6):(4-8) 1.89:1
1500
1500
Isolation
V(rms)
Figure 11 - Typical Parameters of the Input and Output Transformers
4-72
TL
RL
T1 RECEIVE
Figure 10 - Typical ESF Configuration
Line Impedance
TxR
R1=150Ω, 1%, 1/4w
R2 = 4.7KΩ
R3 =4.7KΩ
C1 = 0.01µF, 5% 250V
C2 = 0.47µF, 5% 100V
L1 = 33µH, 130mA
L2 = 33µH, 165mA
TR1 & TR2 see Figures 6 & 11
CDSTi
Parameter
TxT
C2
TxCEN
CKi
R1
STi2
R3
To/From Other Interfaces
T1 TRANSMIT
To other T1 Interfaces
MH89760B
Preliminary Information
MH89760B
High Speed
Parallel
Telecom Bus
MT8920B
(Mode 2)
DIP
Switch
MT8976
OUTA
D0-D7
STo0
STi0
STo1
A0-A5
DSTi
TxA
DSTo
TxB
Tx
Line
Driver
CSTi0
CS
EQU
OUTB
MH89761
CSTo
CSTi1
R/W
C4i
OE
F0i
•
MMS MS1 24/32
F0i
RxA
C2i
RxB
•
RxT
Rx
Line
Driver
•
C1.5i
RxR
+5V
RxD
MT8920B
Signalling and
Link Control
BUS
•
(Mode 1)
D0-D7
STo0
A0-A5
STi0
STo1
CS
DS
R/W
DTACK
IRQ
C4i
F0i
E8Ko
E1.5i
Clock
Extractor
•
•
IACK
MMS
MT8941
1.544 MHz
CVb
12.352 MHz
Osc.
F0i
+5V
C2o
•
F0b
C4b
C8Kb
16.384 MHz
Osc.
Figure 12 - Using the MH89760B in a Parallel Bus Environment
the signalling and link control bus to the MH89760B
status and control channels. All signalling and link
functions may be controlled easily through the STPA
transmit RAM’s Tx0, Tx1, while status information is
read at receive RAM Rx0. In addition, interrupts can
be set up to notify the system in case of slips, loss of
sync, alarms, violations, etc.
3. PCM/Voice Channel Bank
The D3/D4 channel bank is one of the most widely
used pieces of equipment in the North American
network today. The D3/D4 channel converts 24
analog telephone lines into the 24 channels of a T1
serial stream. The channel bank is the interface point
between a digital switching or transmission system
and the analog telephone loop. The industry is
moving towards end-to-end digital connections
(ISDN), but the analog channel bank will still be in
use for many years to come.
Figure 13 shows a block diagram of a channel bank
that has been divided into four sections, the analog
line interface, signalling interface, switch matrix, and
T1 interface. The subscriber line interface circuit
(SLIC) provides interface to the telephone line, i.e.,
provides loop current and ringing voltage, and
converts the analog voice signal into µ-Law PCM.
The SLIC also detects the off-hook condition for
conventional POTS (Plain Old Telephone Set)
signalling.
Once the voice is encoded into digital format the
switch matrix transfers the 24 consecutive channels
that are received from the SLICs to the 24 valid
channels used by the MH89760B. The MH89760B
formats and transmits this information on the T1 line.
Signalling information from the telephone sets can
be routed straight through to the output T1 channel,
or it can be routed to the DTMF receiver pool. This is
4-73
MH89760B
Preliminary Information
T
PCMi
SLIC #1
•
CTLi
OFHK
R
•
•
•
•
T
R
•
PCMo
•
•
••
••
••
•
T1 Interface
Switch Matrix
Analog Line Interface
•
STo0
STi0
STo3
STi3
MT8980
STo1
STi1
MH89760B
DSTi
OUTA
STo2
STi2
STo4
OUTB
MUX
DSTo
CSTi0
CSTo
Equalizer
RxT
CSTi1
RxR
C2i
F0i
SLIC #24
F0i
C1.5i
C4i
CTLo
OFHK
E8Ko
µP
MT8941
DPLL#1
Signalling Interface
CVb
F0i
C1.5i
•
Shift
Reg.
MT8870
STD
#1
MT8964
PCMi
#1
D3
Do
Shift
Reg.
•
•
•
MT8870
STD
#N
MT8964
12.352
MHz Osc.
DPLL#2
F0i
C4i
•
•
•
C12i
C2i
•
F0b
C8Kb
C4b
C2o
C16i
16.384
MHz Osc.
#N
D3
Do
Figure 13 - PCM/Voice Data Channel Bank
easily accomplished by the MT8980 switch matrix
once the SLIC has digitized the analog signal.
Channel banks must be able to operate in a loop
timed mode so that they meet the clock
synchronization requirements of a level four entity.
Phase-locked loop #2 of the MT8941 generates the
ST-BUS clocks that are synchronized to the
extracted 8kHz clock, and phase-locked loop #1
generates the transmit T1 clock synchronized to the
ST-BUS.
4. ISDN Voice/Data Channel Bank/Concentrator
The ISDN channel bank is a term that is used in this
context to describe a system that performs the same
logical function as the D3/D4 channel bank. That is,
it concentrates the subscribers digital loop into the
primary digital transmission scheme, the T1 trunk.
4-74
The ISDN channel bank in Figure 14 is divided into
four blocks, the digital line interface, the switch
matrix, the D channel processing, and the T1
interface. Beginning with the digital line interface, the
MT8910 provides 2B+D 160k bit bidirectional
communication over single twisted pair wiring. The
MT8910 converts the 160kbit line signal into ST-Bus
format, where it can be manipulated by the MT8980
switch matrix. The data received from the MT8910 is
then transferred to the D channel processor by the
switch matrix. The D channel processor converts the
2B+D format used on the 160 kBit digital line into the
23B+D format used on the T1 Link.
MH89760B
Preliminary Information
MT8910
DSTo
DSTi
MT8980
•
ZT
•
••
••
••
••
••
••
••
MH89760B
STi0
STo1
STo0
STi1
C4i
F0i
•
DSTi
DSTo
OUTA
STo2
STi3
CSTi0
CSTo
OUTB
STo3
CSTi1
•
Equalizer
RxR
RxT
C2i
F0i
µP
E8Ko
C1.5i
D-Channel Processing
MT8952
MT8952
DSTo
MT8910
ZT
T1 Interface
Switch Matrix
Digital Line Interface
DSTo
DSTi
•
•
•
DSTo
DSTi
•
•
•
•
MT8941
DSTi
F0i
µP
µP
C1.5
•
F0o
C2o
MT8952
E8Ko
C4o
DSTo
DSTi
µP
Figure 14 - ISDN Voice Data Channel Bank
To control and monitor the MT8910s and the T1
interface the switch matrix operates some of its input
and output streams in message mode. This enables
the system to control all of the functions of the
MT8910s and the T1 interface through the Control
ST-BUS points, (CSTi/o).
Clock synchronization is done by the MT8941.
Phase-locked loop # 2 generates ST-BUS clocks that
are synchronized to the extracted 8kHz output from
the T1 interface. Phase-locked loop #1 generates
the transmit T1 clock synchronized to the ST-BUS
clocks, which are synchronized to the extracted T1
clock. This scheme will also allow the system to
operate in a loop timed mode.
With appropriate multiplexing a single D channel
processor can handle all 23 2B+D interfaces. If both
B channels on all 24 lines are going to be used then
it would be necessary to use two T1 trunk interfaces.
5. Digital Access Cross Connect System
(DACS)
The Digital Access Cross Connect System (DACS) is
a T1 switch with 127 T1 lines as input and output
plus one T1 line that is reserved for test and
maintenance purposes. A DACS is capable of
switching any input channel on any T1 trunk to any
output channel on any T1 trunk.
There are four main blocks in Figure 15, the T1
interfaces, the switch matrix, the control matrix, and
the clock generator. The digital trunk interface is
made up of the MH89760B plus the additional
components required to interface to the transmission
line. The MH89760B handles all of the required
transmit and receive data formatting, and converts
the 1.544 MHz serial stream into ST-BUS format so
that it can be routed through the MT8980
synchronous switch matrix.
4-75
MH89760B
Preliminary Information
The switch matrix can be built so that the maximum
throughput delay is 1 frame +2 channels. The switch
matrix will not only route data channels to their
destination, but it will also route the received
signalling bits through to the destination channel.
This is necessary because the receiving MH89760B
decodes the T1 stream, and the transmitting
MH89760B has to reconstruct the outgoing T1
stream. In other words, there is no multiframe
integrity between received data and transmitted
data. The total throughput delay is one frame plus
ten ST-BUS channels for the MH89760B receiver,
2.5 ST-BUS channels for the MH89760B transmitter,
and one frame plus two ST-BUS channels for the
switch matrix for a total of 2.5 frames worst case.
The control block only interfaces with the switch
matrix. Besides routing channels and signalling
through to the proper destination, the switch matrix
must also supply the Master Control Words, and
monitor the Master Status Words for each
MH89760B.
The clock generation block supplies the ST-BUS
clocks and the T1 transmit clocks that are
synchronized to one of the T1 trunks. All of the
extracted 8 kHz outputs are NANDed together before
they are input to PLL #2 of the MT8941.
Phase-locked Loop #2 of the MT8941, will generate
ST-BUS clock signals for the MH89760Bs and the
MT8980s that are synchronized with the chosen T1
line. The E8Ko of all of the other MH89760Bs can be
tristated from the Master Control Word, which allows
the system controller to select any one of 128 T1
lines to act as the synchronization source. By
MH89760B
MT8980
Switch
Matrix
STo0
STi0
OUTA
DSTi
DSTo
Equalizer
OUTB
CSTi0
CSTo
CSTi1
RxT
RxR
F0i
STo7
C4i
STi7
C2i
F0i
E8Ko
C1.5i
MT8980
M
I
C
R
O
STo0
•
•
•
•
•
•
STi0
STo1
STo2
Control
Matrix
F0i
STo7
C4i
STi7
DSTi
Clock
Generator
CVb
OUTA
DSTo
CSTi0
CSTo
CSTi1
MT8941
DPLL #1
C1.5i
MH89760B
OUTB
RxT
RxR
C2i
C12i
F0i
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AAAAAAAAAAAAAAAAAAAA
AAAA
A
DPLL #2
F0i
12.352
MHz Osc.
F0b
C8Kb
C4i
C4b
C2i
C20
C16i
16.384
MHz Osc.
F0i
•
•
•
•
•
•
•
C1.5i
E8Ko
T1 Interfaces
Figure 15 - Digital Access Cross Connect System (DACS)
4-76
Equalizer
MH89760B
Preliminary Information
Asynchronous
Interface
Protocol Converter
T1 Interface
Switch Matrix
MT8980
ACIA
D0-D7
A0-A7
R
S
2
3
2
STo1
STi1
MT89760B
DSTi
OUTA
DSTo
D0-D7
STo2
CSTi0
OUTB
A0-A7
STi2
CSTo
RxT
STo3
CSTi1
MT8952
•
STi0
•
STo0
Equalizer
RxR
C2i
Micro
ACIA
D0-D7
R
S
2
3
2
A0-A7
•
•
F0i
MT8952
F0i
C1.5i
C4i
68008
•
•
E8Ko
D0-D7
A0-A7
MT8941
DPLL #1
ACIA
D0-D7
R
S
2
3
2
A0-A7
• •
•
•
•
CVb
C1.5i
MT8952
F0i
•
DPLL #2
D0-D7
F0i
A0-A 7
•
•
•
•
•
•
•
C12i
• ••
•
•
•
C4i
C2i
•
12.352
MHz
Osc.
F0b
C8Kb
C4b
C20
16.384
MHz
Osc.
Figure 16 - Digital Multiplex Interface (DMI)
connecting the frame pulse output, F0o, of PLL #2 to
F0i of PLL # 1, the MT8941 will generate the T1
transmit clock that is phase-locked to F0o, which in
turn is phase-locked to the master synchronization
signal, E8Ko. If all of the T1 trunks are from the
network any short term differences in the received
data rate will be absorbed by the elastic buffer in the
MH89760B.
protocol converter (micro and MT8952s), the switch
matrix (MT8980), and the T1 interface (MH89760B).
The Asynchronous Communications Interface
Adapters (ACIA) provide a standard RS232 interface
that is compatible with many off-the-shelf modems
and data sets. A single microprocessor is capable of
handling the protocol conversion between the RS232
ports and the MT8952 HDLC protocol controller.
6. Digital Multiplex Interface (DMI)
Figure 16 illustrates an implementation of the Digital
Multiplex Interface (DMI) specification, which defines
a computer to PBX interface. This interface can
convert 300 baud to 64 kbaud asynchronous or
synchronous data channels to T1 format with clear
channel capabilities and common channel signalling.
Figure 16 is broken down into four functional blocks
which are the asynchronous interface (ACIAs), the
The MT8952 interfaces directly to the ST-BUS, which
in turn interfaces directly to the T1 interface devices.
Instead of the MT8952 operating at 64 kbit/s
continuously, it operates at 2.048 Mbit/s and
inputs/outputs an 8 bit burst every 125 µsec. This
feature eliminates the need for an additional rate
conversion circuit to multiplex the HDLC outputs up
to the T1 data rate. Each of the HDLC chips is
assigned a timeslot on the ST-BUS in a manner that
is similar to enabling a voice codec. When the
MT8952 is not enabled the output driver is tristated.
4-77
MH89760B
Preliminary Information
The channel assignment circuit is therefore very
simple.
The switch matrix, in the message mode, passes
monitor and control information between the
microprocessor and the T1 interface over ST-BUS
stream 0. The MT8980 is also used to reformat the
ST-BUS data streams between the protocol
converter and the MH89760B interface.
The MH89760B and the MT8941 form the T1
interface. The MH89760B converts the data received
on the ST-BUS into a 1.544 MHz T1 stream. All of
the formatting and decoding of the T1 signal is
performed by this device. The MT8941 provides the
clock synchronization required to operate in a loop
timed mode. Digital phase-locked loop #2 provides
ST-BUS clocks that are synchronized to the
extracted 8kHz, and digital phase-locked loop #1
provides the transmit 1.544 MHz clock synchronized
to the ST-BUS.
7. High Speed Data Transmission Link
communications. The basic mode of transmission is
to assemble data into packets (e.g., HDLC or
ethernet) which are transported on a T1 link
configured as a 1.536 Mbit/s serial channel. No T1
repeaters are required if the transmission link length
is 1300 ft. or less (e.g., business complex or
university). However, if the transmission link length is
greater than 1300 ft., a repeatered T1 line must be
leased from the local telephone operating company.
Figure 17 is divided into three functional blocks
which are the protocol converter, switch matrix, and
T1 interface. The protocol section is dependent on
the particular format that is chosen. In this example it
is assumed that the protocol is HDLC. The Transmit
Clock Enable (TxCEN) and the Receive Clock
Enable (RxCEN) of the MT8952 are active for a
period of 24 consecutive ST-BUS channels, and the
clock speed is 2.048 MHz. This enables the protocol
conversion section to interface directly to the switch
matrix. The switch matrix switches the first 24
channels received from the protocol section into the
24 valid timeslots used by the MH89760B. Once the
data enters the T1 interface the MH89760B formats
and transmits the data on the T1 line.
High speed data links are becoming increasingly
popular in private networks and computer
Protocol Converter
Switch Matrix
MT8952
T1 Interface
MT8980
CDSTo
CDSTi
TxCEN
RxCEN
STi0
STo0
•
MH89760B
DSTi
OUTA
STo1
STi1
DSTo
STo2
STi2
CSTi1
CSTo
STo3
CSTi0
OUTB
EQUALIZER
RxT
RxR
C2i
F0i
F0i
C4i
C4i
F0i
C1.5i
E8Ko
MT8941
DPLL #1
CVb
F0i
C1.5i
MICRO
C12i
12.352
MHz Osc.
DPLL #2
F0i
•
F0b
C8Kb
C4i
C2i
C4b
C20
C16i
Figure 17 - High Speed Data Transmission Link
4-78
16.384
MHz Osc.
MH89760B
Preliminary Information
Control and monitoring of the T1 interface is done
through the MT8980 switch matrix. CSTi0 and
CSTo1 are connected to the ST-BUS streams that
are configured for message mode so the controlling
microprocessor can access the Master Control
Words and the Master Status Words.
systems is the ST-BUS. Therefore, a T1 to CEPT
digital trunk converter can be realized.
Figure 18 shows five blocks which are the T1
interface, switch matrix, CEPT interface, clock
generation and synchronization, and DSP Element.
The T1 interface converts the 1.544 MHz serial
stream into the ST-BUS format which interfaces to
the switch matrix through DSTi and DSTo. The CEPT
interface converts the 2.048 MHz serial stream into
the ST-BUS format and interfaces to the switch
matrix through the DSP element.
The received portion of the T1 interface extracts the
data from the T1 stream and formats it into ST-BUS
channels. The MT8980 switches these ST-BUS
channels into the first 24 consecutive channels of an
ST-BUS stream, which is passed to the protocol
conversion block. HDLC packets are disassembled
from the incoming ST-BUS stream by the MT8952.
With both the T1 data and the CEPT data converted
to the ST-BUS format, the two digital trunks can
exchange information through the switch matrix.
Unfortunately, the signalling information from the two
formats is not exchanged as easily. The T1 A and B
signalling bits must be read by the controlling
microprocessor and converted in software to the
CEPT ABCD signalling bits, and vice versa. The
circuit must also convert all the channels carrying
voice data to the appropriate encoding scheme, (i.e.,
T1 µ-Law or CEPT A-Law). This is done by the block
labelled DSP in Figure 18, Digital Signal Processor.
Clock generation and synchronization are handled
by the MT8941. DPLL #2 generates ST-BUS clocks
that are phase-locked to the extracted 8KHz, and
DPLL #1 generates the transmit T1 clock that is
phase-locked to the ST-BUS frame pulse. Therefore,
the interface is operating in a loop timed mode and
there will be no loss of information due to slips. The
MT8941 can also be configured to operate in a
master timing mode.
8. T1 to CEPT Digital Trunk Converter
The final component of the system is the MT8941.
The extracted 8 kHz outputs from the T1 and the
CEPT interfaces are combined with an AND gate
before being connected to the MT8941. One of the
The two main digital trunk transmission formats in
use today are T1 and CEPT. Mitel's T1 and CEPT
interfaces convert the digital trunk format into STBUS format. The common element between the two
CEPT Interface
Switch Matrix
MH89790B
RxA
RxB
OUTA
OUTB
DSTi
DSTo
T1 Interface
MH89760B
MT8980
DSP
Element
RxT
CSTi0
CSTi1
CSTo
STi0
STo0
STo1
STi1
DSTi
STo3
STo4
STi4
STi2
STo2
STo3
CSTo
DSTo
C4i
C2i
F0i
E8Ko
F0i
RxR
CSTi0
CSTi1
OUTA
F0i
OUTB
C2i
C1.5i
E8Ko
µP
MT8941
DPLL #1
C1.5o
DPLL #2
F0o
C2o
E8Ki
C4o
Clock Generator
Figure 18 - T1 to CEPT Digital Trunk Converter
4-79
MH89760B
interfaces is selected as the synchronization source
by enabling its output through the Master Control
Word of the chosen interface. Phase-locked loop #2
will then generate ST-BUS clocks that are
synchronized to either the T1 network or the CEPT
network. Phase-locked loop #1 is configured to
generate the T1 transmit clock synchronized to the
ST-BUS. Therefore, if the ST-BUS is synchronized to
one network then the elastic buffer in the opposite
interfaces will perform controlled slips between that
network and the T1 to CEPT converter.
Preliminary Information
Magnetics Information
For supporting initial design activities, Mitel
Semiconductor has available the MH89760B
Magnetic Kit which contains the magnetics shown in
Figure 11. Alternatively, they are available directly
from the following manufacturer:
Filtran Ltd.
229 Colonnade Road
Nepean, Ontario
Canada K2E 7K3
Telephone: (613) 226-1626
Please refer to Figure 6 for the transformer part
numbers.
4-80
MH89760B
Preliminary Information
.
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD
-0.3
7
V
VSS-0.3
VDD+0.3
V
1
Supply Voltage with respect to VSS
2
Voltage on any pin other than supplies, OUTA or OUTB
3
Voltage on OUTA or OUTB
15
V
4
Current at any pin other than supplies, OUTA or OUTB
20
mA
5
Current at OUTA or OUTB
200
mW
6
Storage Temperature
85
°C
TST
-20
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameters
1
2
3
4
I
n
p
u
t
s
Sym
Min
Operating Temperature
TOP
0
Supply Voltage
VDD
4.5
Input High Voltage
VIH
2.4
VIH
Input Low Voltage
VIH
Typ‡
5.0
Max
Units
70
°C
5.5
V
VDD
V
Digital Inputs
V
Line Inputs
V
Digital Inputs
V
Line Inputs
3.0
VSS
VIL
0.4
0.3
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Clocked operation over recommended temperature ranges.
Parameters
1
2
3
4
I
n
p
u
t
s
5
6
7
8
9
O
u
t
p
u
t
s
Sym
Min
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
IIL
Output High Current
IOH
7
Output Low Current
IOL
2
Output Low Voltage
OUTA or OUTB
VOL
Input Impedance RxT to RxR
RxT or RxR to Gnd
ZIN
Schmitt Trigger Input (XSt)
VT+
VT-
Typ‡
Max
Units
12
25
mA
2.0
Test Conditions
Outputs Unloaded
V
Digital Inputs
0.8
V
Digital Inputs
±10
µA
Digital Inputs VIN=0 to VDD
20
mA
Source Current VOH=2.4V
10
mA
Sink Current VOL=0.4V
±1
0.25
V
400
Ω
1K
Ω
4.0
1.5
IOL=10mA
V
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Capacitance
Characteristics
Sym
Min
Typ‡
Max
Units
1
Input Pin Capacitance
CI
10
pF
2
Output Pin Capacitance
CO
10
pF
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
4-81
MH89760B
Preliminary Information
AC Electrical Characteristics† - Clock Timing (Figures 19 & 20)
Characteristics
Sym
Min
Typ‡
Max
Units
1
C2i Clock Period
tp20
400
488
600
ns
2
C2i Clock Width High or Low
tW20
200
244
300
ns
3
Frame Pulse Setup Time
tFPS
50
ns
4
Frame Pulse Hold Time
tFPH
50
ns
5
Frame Pulse Width
tFPW
50
ns
6
RxSF Output Delay
tFPOD
7
TxSF Hold Time
tTxSFH
8
TxSF Setup Time
tTxSFS
125
ns
0.5
124.5
µs
0.5
124.5
µs
Test Conditions
tP20 = 488 ns
50 pF Load
NB: Frame Pulse is repeated every 125µs in synchronization with the clock.
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
F0i
Frame 1
Frame 12/24
Frame 2
RxSF
TxSF
C2i
ST-BUS
BIT CELLS
Bit
7
Bit
6
Bit
5
Bit
4
Bit
7
Bit
6
Bit
5
Bit
4
Bit
7
Bit
6
Bit
5
Bit
4
Figure 19 - Clock & Frame Alignment for ST-BUS Streams
tP20
C2i
tW20
VIH
VIL
tW20
tFPS
F0i
VIH
tFPH
tFPS
tFPW
VIL
tFPOD
RxSF
tFPOD
VOH
VOL
AA
AAAA
AA
AA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
F0i
Frame 1
Frame 12/24
VIH
C2i
VIL
tTxSFH
tTxSFS
VIH
TxSF
VIL
Figure 20 - Clock & Frame Pulse Timing for ST-BUS Streams
4-82
MH89760B
Preliminary Information
AC Electrical Characteristics† - Timing For DS1 Link Bit Cells (Figure 21)
Characteristics
Sym
Min
Typ‡
Max
Units
1
E1.50 Clock Period
tPEC
648
ns
2
E1.5o Clock Width High or Low
tWEC
324
ns
3
E1.5o Clock Rise Time
tREC
60
ns
4
E1.5o Clock Fall Time
tFEC
20
ns
Test Conditions
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
BIT CELL
DS1 BIT CELLS FOR
RECEPTION
BIT CELL
tW1EC
tR1EC
E1.5o
VOH
VOL
tR1EC
tP1EC
tW1EC
Figure 21 - DS1 Receive Clock Timing
AC Electrical Characteristics† - 2048 kbit/s ST-BUS Streams (Figure 22)
Characteristics
Sym
Min
Typ‡
Max
Units
125
ns
1
Serial Output Delay
tSOD
2
Serial Input Setup Time
tSIS
15
ns
3
Serial Input Hold Time
tSIH
50
ns
Test Conditions
150 pF load
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Bit Cell Boundaries
C2i
V IH
VIL
DSTo
or CSTo
VOH
VOL
tSOD
DSTi,
CSTi0/CSTi1
tSOD
VIH
VIL
tSIS
tSIH
Figure 22 - ST-BUS Stream Timing
4-83
MH89760B
Preliminary Information
AC Electrical Characteristics† - XCtl, XSt, & E8Ko (Figures 23, 24, & 25)
Parameters
Sym
Min
Typ‡
Max
Units
1
External Control Delay
tXCD
140
ns
2
External Status Setup Time
tXSS
100
ns
3
External Status Hold Time
tXSH
400
ns
4
8 kHz Output Delay
t8OD
150
ns
5
8 kHz Output Low Width
t8OL
78
µs
6
8 kHz Output High Width
t8OH
47
µs
7
8 kHz Rise Time
t8R
10
ns
8
8 kHz Fall Time
t8F
10
ns
Test Conditions
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
ST-BUS Bit Cell Boundary Between
Bit 2 Channel 30 and Bit 1 Channel 30
ST-BUS Bit Cell Boundary Between
Bit 0 Channel 15 and Bit 7 and Channel 16
C2i
2.0V
C2i
2.0V
0.8V
0.8V
2.0V
2.4V
XSt
XCtl
0.4V
0.8V
tXCD
tXSS
Figure 23 - XCtl Timing
Received
DS1 Bits
Channel 2
Bit 1
tXSH
Figure 24 - XSt Timing
Channel 17
Bit 2
• • •
• • •
Channel 2
Bit 1
VOH
E1.5o
VOL
t8OD
t8OD
t8OD
VOH
E8Ko
VOL
t8OL
t8F
t8OH
t8R
Figure 25 - E8Ko Timing
4-84
t8F
MH89760B
Preliminary Information
AC Electrical Characteristics† - DS1 Link Timing (Figures 26 and 27)
Typ‡
Characteristics
Sym
Min
Max
Units
1
Transmit Steering Delay
tTSD
50
150
ns
2
E1.5o Clock Period
tPEC
648
ns
3
E1.5o Clock Width High or Low
tWEC
324
ns
4
Receive Data Setup Time
tRDS
50
ns
5
Receive Data Hold Time
tRDH
50
ns
6
Receive Data Pulse Width
tRDW
324
ns
7
Receive Data Fall Time
tRDF
20
ns
8
Receive Data Rise Time
tRDR
20
ns
9
C1.5i Period
tPC1.5
500
648
10
C1.5i Pulse Width High or Low
tWC1.5
250
324
800
Test Conditions
150 pF Load
ns
ns
† Timing is over recommended operating temperature and power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Transmitted DS1 Link
Bit Cells
Bit Cell
tPC1.5
VIH
C1.5i
VIL
tTSD
OUTA
or
OUTB
tWC1.5
tTSD
VOH
VOL
Figure 26 - Transmit Timing for DS1 Link
Received DS1 Link
Bit Cells
Bit Cell
tPEC
tWEC
tWEC
VOH
E1.5o
VOL
tRDS
RxA
or
RxB
tRDH
VOH
VOL
tRDW
tRDF
tRDR
Figure 27 - Receive Timing for DS1 Link
4-85
MH89760B
Preliminary Information
AC Electrical Characteristics† - DS1 Link Timing (Figures 28 & 29)
Parameters
Sym
Min
Typ‡
Max
Units
1
Transmit FDL Setup Time
tDLS
110
ns
2
Transmit FDL Hold Time
tDLH
70
ns
3
Receive FDL Output Delay
tDLOD
0
4
Receive FDL Clock Delay
tFRCD
185
5
Transmit FDL Clock Delay
tTFCD
135
ns
Test Conditions
50 pF Load
50 pF Load
ns
50 pF Load
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Frame 1
Frame 12/24
F0i
Frame 2
C2i
RxFDLClk
RxFDL
TxFDLClk
TxFDL
Figure 28 - Clock & Frame Alignment for RxFDL and TxFDL
C2i
2.0V
0.8V
Frame
2.0V
0.8V
tRFCD
2.0V
RxFDLClk
RxFDL
0.8V
tDLOD
2.0V
0.8V
tTFCD
TxFDLClk
2.0V
0.8V
tDLS
TxFDL
2.0V
0.8V
Figure 29 - Facility Data Link Timing
4-86
tDLH
MH89760B
Preliminary Information
125µs
CHANNEL
31
CHANNEL
0
• • • • • • • •
CHANNEL
30
CHANNEL
31
CHANNEL
0
(8/2.048)µs
NB:
Numbering
differs from
Fig 31.
Most
Significant
Bit (First)
BIT 7
BIT 5
BIT 6
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Least
Significant
Bit (Last)
Figure 30 - Format of 2048 kbit/s ST/BUS Streams
125µs
CHANNEL
24
S Bit
• • • • • •
CHANNEL
1
(1/1.544)µs
NB:
Numbering
differs from
Fig 30.
CHANNEL
23
CHANNEL
24
S Bit
CHANNEL
1
(8/1.544)µs
Most
Significant
Bit (First)
BIT 1
BIT 3
BIT 2
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Least
Significant
Bit (Last)
Figure 31 - DS1 Link Frame Format
125µs
C2i
DSTi
DSTo
7
6
5
4
3
2
1
0
• • • • • • • • •• •
7
7
6
5
4
3
2
1
0
• • • • • • • • •• •
7
CSTi0/CSTi1
CSTo
Figure 32 - Functional ST-BUS Timing
125µs
E1.5i
INT DATA
1
1
0
0
1
1
0
1
RxT/RxR
LINE SIGNAL
RxA
RxB
E8Ko
Figure 33 - Functional DS1 Receive Timing
4-87
MH89760B
Preliminary Information
C1.5i
INT DATA
OUTA
OUTB
AMI LINE
Figure 34 - DS1 Transmit Timing
Packaging
The MH89760B is available in three package options
which are:
• The MH89760BS which is a surface mountable
version of the MH89760BN is suitable for
Infrared Reflow (I.R.) soldering. See Figure 35
for the dimensional drawing, and Figure 36 for
the recommended footprint.
•
The MH89760B which is pin compatible with the
MH89760, has a row pitch of 1.3” and is fitted
with a plastic lid. See Figure 37 for the
dimensional drawing for this part.
•
The MH89760BN which is a narrow version of
the MH89760B and has a row pitch of 0.8”. See
Figure 38 for the dimensional drawing for this
part.
0.25
(6.35)
2.0
(50.8)
AAAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
0.125
(3.18)
0.78
(19.81)
0.10 + 0.01
(2.54 + 0.25)
MH89760BS
0.06
(1.52)
0.06
(1.52)
0.9
(22.86)
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
0.020 + 0.002
(0.51 + 0.051)
Note 1
Notes:
1) Pin 1 not fitted.
2) All dimensions are typical and in inches (mm).
3) Not to scale.
Figure 35 - Physical Dimensions for the 40 Pin Dual in Line S.M.T. Hybrid
4-88
0.125
(3.18)
MH89760B
Preliminary Information
0.760
(19.3)
Pin 2 position
0.090
(2.29)
0.040
(1.02)
0.060
(1.52)
Figure 36 - Recommended Footprint for the 40 Pin Dual in Line S.M.T. Hybrid
2.12
(53.85)
.31
(7.87)
1.3
(33.0)
Note 2
0.10 + 0.01
(2.54 + 0.25)
MH89760B
AAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
0.09
(2.3)
0.260
(6.6)
Note 1
2.0
(50.8)
0.020 + 0.002
(0.51 + 0.051)
Notes:
1) Pin 1 not fitted.
2) Row pitch is to the centre of the pins.
3) All dimensions are typical and in inches (mm).
4) Not to scale.
Figure 37 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 1.3" Row Pitch
4-89
MH89760B
Preliminary Information
2.0
(50.8)
AAAA
AAAAAAAAAAAAAAA
AAAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAAAAAAAAAAAAA
0.25
(6.35)
0.8
(20.32)
Note 2
0.10 + 0.01
(2.54 + 0.25)
MH89760BN
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAA
0.09
(2.3)
Note 1
0.020 + 0.002
(0.51 + 0.051)
Notes:
1) Pin 1 not fitted.
2) Row pitch is to the centre of the pins.
3) All dimensions are typical and in inches (mm).
4) Not to scale.
Figure 38 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch
4-90
0.260
(6.6)
MH89760B
Preliminary Information
Appendix
Control and Status Register Summary
7
6
Debounce
5
TSPZCS
4
B8ZS
8KHSel
3
XCtI
2
1
ESFYLW
0
Robbed Bit
YLALR
1 Disabled
1 Disabled
1 B8ZS
1 Disabled
1 Set High
1 Enabled
1 Disabled
1 Enabled
0 Enabled
0 Enabled
0 Jammed
Bit
0 Enabled
0 Cleared
0 Disabled
0 Enabled
0 Disabled
Master Control Word 1 (Channel 15, CSTi0)
RMLOOP
DGLOOP
ALL1’s
ESF/D4
1 Enabled
1 Enabled
1 Enabled
1 ESF
0 Disabled
0 Disabled
0 Disabled
0 D3/D4
Reframe
Device
Reframes on
High to Low
Transition
SLC-96
CRC/MIMIC
1 Enabled
See Note 1
0 Disabled
Maint.
1 4/12
0 2/4
Master Control Word 2 (Channel 31, CSTi0)
UNUSED - KEEP AT 0
Polarity
Loop
1 No Inversion
1 Ch. looped
back
0 Inversion
Data
1 Enabled
0 Disabled
0 Normal
Per Channel Control Words (All Channels on CSTi0 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31)
UNUSED - KEEP AT 0
A
B
C
D
Txt. Sig. Bit
Txt. Sig. Bit
Txt. Sig. Bit
Txt. Sig. Bit
Per Channel Control Words (All Channels on CSTi1 Except Channels 3, 7, 11, 15, 19, 23, 27 & 31)
YLAIR
MIMIC
ERR
1 Detected
1 Detected
0 Normal
0 Not
Detected
ESFYLW
FT Error
Count
MFSYNC
BPV
1 Detected
1 Not Detected
0 Not
Detected
0 Detected
Bipolar
Violation
count
SLIP
Changes
State
when Slip
Performed
SYN
1 Out-of-Sync.
0 In-Sync
Master Status Word 1 (Channel 15, CSTo)
BlAlm
FrCnt
1 Detected
Frame
Count
0 Not Detected
XSt
1 Xst High
BIPOLAR VIOLATION COUNT
CRC-ERROR COUNT
0 Xst Low
Master Status Word 2 (Channel 31, CSTo)
CHANNEL COUNT
BIT COUNT
Phase Status Word (Channel 3, CSTo)
UNUSED
A
Rec’d. Sig. Bit
B
Rec’d. Sig. Bit
C
Rec’d. Sig. Bit
D
Rec’d. Sig. Bit
Per Channel Status Word (All Channels on CSTo Except Channels 3, 7, 11, 15, 19, 23, 27, 31)
Note 1:
In ESF mode:
1: CRC calc. ignored during Sync.
0: CRC checked for Sync.
In D3/D4 mode:
1: Sync. to first correct S-bit pattern.
0: Will not Sync. if Mimic detected.
4-91
MH89760B
Notes:
4-92
Preliminary Information