FIDELIX CMP0817BA1 512k x 16 bit super low power and low voltage full cmos ram Datasheet

CMP0817BAx-E
CMOS LPRAM
Document Title
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM
Revision History
Revision
No.
History
Draft date
Remark
0.0
Initial Draft
Dec. 22nd, 2003
Preliminary
0.1
Add tCP=10ns in AC characteristics
Minor Changes
Mar. 10th, 2004
Final
0.2
Minor Changes
Jul. 6th, 2004
Final
0.3
Modified functional description & MRS update timing
Minor Changes
Nov. 8th, 2004
Final
0.4
Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions
Removed the MRS DPD function
Minor Changes
Oct. 26th, 2005
Final
0.5
Removed 60ns part descriptions
Aug. 22nd, 2006
Final
1
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM
FEATURES
• Process Technology : Full CMOS
• Three state output and TTL Compatible
• Package Type : 48-FBGA-6.00x8.00 mm2
• Separated I/O power(VCCQ) & Core Power(VCC)
• Page read/write operation up to 16 words
• Organization : 512K x 16
• Power Supply Voltage : 2.7~3.3V
• Low Power & Page Modes
CMP0817BA1 : support the PASR function
CMP0817BA2 : support the DPD function
CMP0817BA4 : support the PASR/PAGE function
CMP0817BA5 : support the DPD/PAGE function
(CMP0817BA4, CMP0817BA5)
• DPD mode when /ZZ goes low
(CMP0817BA2, CMP0817BA5)
PRODUCT FAMILY
Operating
Temperature
Product Family
Power Dissipation
Operating
Voltage (V)
ICC2
f = 1MHz
f = fmax
Speed
Min. Typ. Max.
Extended
(-25~85’C)
CMP0817BAx-F70E
ICC1
2.7
3.0
3.3
70ns
ISB1
(CMOS Standby
Current)
Typ.
Max.
Typ.
Max.
Typ.
Max.
1.5mA
3mA
12mA
20mA
30uA
70uA
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C.
2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
PIN DESCRIPTION
1
2
3
4
5
6
A
/LB
/OE
A0
A1
A2
/ZZ
B
I/O9
/UB
A3
A4
/CS
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
VSS
I/O12
A17
A7
I/O4
VCC
E
VCCQ
I/O13
DNU
A16
I/O5
VSS
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
NC
A12
A13
/WE
I/O8
H
A18
A8
A9
A10
A11
NC
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
VCC
VSS
Row
Addresses
I/O1~I/O8
Function
Name
Function
/ZZ
Low Power Modes
VCC
Core Power
I/O Power
Chip Select Input
VCCQ
Output Enable Input
VSS
Ground
/CS
/WE
Write Enable Input
/UB
Upper Byte(I/O9~16)
/OE
A0~A18
Address Inputs
/LB
Lower Byte(I/O 1~8)
/WE
Data Inputs/Outputs
No Connection
DNU
I/O Circuit
Column select
Column Addresses
/CS
NC
Data
cont
Memory array
Data
cont
/OE
I/O1~I/O16
Row
select
Data
cont
I/O9~I/O16
48-FBGA : Top View(Ball Down)
Name
Precharge circuit.
/UB
Control Logic
/LB
Do Not Use
/ZZ
2
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
PRODUCT LIST
Extended Temperature Products(-25~85’C)
Part Name
Function
CMP0817BAx-F70E
48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
FUNCTIONAL DESCRIPTION
/CS
/ZZ
/OE
/WE
/LB
/UB
I/O1-8
I/O9-16
Mode
Power
H
H
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
Standby
X1)
L
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
DPD2)
H
L
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
Low Power Modes3)
X1)
H
X1)
X1)
H
H
High-Z
High-Z
Deselected
Standby
H
H
H
L
X1)
High-Z
High-Z
Output Disabled
Active
H
H
H
X1)
L
High-Z
High-Z
Output Disabled
Active
L
H
Dout
High-Z
Lower Byte Read
Active
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
Dout
Dout
Word Read
Active
L
H
Din
High-Z
Lower Byte Write
Active
H
L
High-Z
Din
Upper Byte Write
Active
L
L
Din
Din
Word Write
Active
L
L
L
H
H
X1)
L
1. X means don’t care.(Must be low or high state)
2. In case of CMP0817BA2 & CMP0817BA5 product
3. In case of CMP0817BA1 & CMP0817BA4 product
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Symbol
Ratings
VIN, VOUT
-0.2 to Vcc+0.3V
V
Vcc
-0.2 to 3.6
V
Voltage on Vcc supply relative to Vss
PD
1.0
W
TSTG
-65 to 150
’C
TA
-25 to 85
’C
Power Dissipation
Storage temperature
Unit
Operating Temperature
1. Str es s e s g r e ate r tha n th o s e l i st e d u n d er “ A bsolute Maxim um Ratings” may cause permanent dam age to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
I/O operating voltage (VCCQ ≤ VCC)
Ground
CMP0817BA
Max
VCC
2.7
3.3
2.7
3.3
2.7
3.3
V
VCCQ
2.7
3.3
2.25
2.75
1.65
1.95
V
VSS
0
0
0
0
0
0
V
Input high voltage
VIH
0.8VCCQ
VCC+0.22)
0.8VCCQ
VCC+0.22)
0.8VCCQ
VCC+0.22)
V
Input low voltage
VIL
-0.23)
0.2VCCQ
-0.23)
0.2VCCQ
-0.23)
0.2VCCQ
V
Supply voltage
Min
Max
Min
Max
Unit
Min
Note :
1.TA=-25 to 85’C, otherwise specified.
2. Overshoot : Vcc+1.0V in case of pulse width≤20ns.
3. Undershoot : -1.0V in case of pulse width≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
3
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
CAPACITANCE1) (f=1MHz , TA=25’C)
Symbol
Test Condition
Min
Max
Input capacitance
Item
CIN
VIN=0V
-
8
Unit
pF
Input/Output capacitance
CIO
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Min
Typ
Max
Unit
Input leakage current
Item
Symbol
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC
-1
-
1
uA
ICC1
Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH,
VIN≤0.2V or VIN≥VCC-0.2V
-
-
3
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH,
VIN=VIL or VIH
-
-
25
mA
Output low voltage
VOL
IOL=0.5mA
0.2VCCQ
V
Output high voltage
VOH
IOH=-0.5mA
Standby Current(TTL)
ISB
/CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL
-
-
0.3
mA
Standby Current(CMOS)
Deep Power Down
Current1)
ISB1
/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC
-
-
70
uA
ISB0
/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)
-
-
10
uA
ISB0a
/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection
-
-
40
uA
ISB0b
/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection
-
-
50
uA
ISB0c
/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection
-
-
70
uA
Average operating current
Low Power Modes
Test Conditions
0.8VCCQ
V
1. CMP0817BA2 & CMP0817BA5 products support DPD(Deep Power Down) Current
4
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
1TTL
30pf
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : TA=-25 to 85’C)
Parameter List
Read Cycle Time
Read
tRC
Max
70
80k
ns
ns
tAA
-
70
Chip Select to Output
tCO
-
70
ns
Output Enable to Valid Output
tOE
-
25
ns
/UB, /LB Access Time
tBA
-
70
ns
ns
tLZ
10
-
/UB, /LB Enable to Low-Z Output
Chip Select to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
tHZ
0
5
ns
/UB, /LB Disable to High- Z Output
tBHZ
0
5
ns
Output Disable to High- Z Output
tOHZ
0
5
ns
Output Hold from Address Change
tOH
5
-
ns
Write Cycle Time
tWC
70
80k
ns
Chip Select to End of Write
tCW
60
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
60
-
ns
/UB, /LB Valid to End of Write
tBW
60
-
ns
Write Pulse Width
tWP
50
-
ns
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
tWR
0
-
ns
tWHZ
0
5
ns
tDW
20
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
Page Mode Cycle Time
Page
Units
Min
Address Access Time
Chip Disable to High- Z Output
Write
70ns
Symbol
tPC
25
-
ns
Page Mode Address Access Time
tPAA
-
25
ns
Maximum Cycle Time
tMRC
-
80k
ns
tCP
10
-
ns
/CS High Pulse Width1)
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
5
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
Power Up Sequence
1. Apply Power
2. Maintain stable power for a minimum of 200us with /CS=VIH
Standby Mode State machines
Power On
/CS=VIH
Wait 200us
/CS=VIH, /ZZ=VIH
Initial State
/CS=VIL, /ZZ=VIH
/UB or/and /LB=VIL
/CS=VIH, /ZZ=VIL
Active
Mode
/CS=VIlL
/ZZ=VIH
/CS=VIH
/ZZ=VIL
/CS=VIH
(or/and /UB=/LB=VIH)
/ZZ=VIH
/CS=VIH, /ZZ=VIL
Standby Mode
/CS=VIlL
/ZZ=VIH
Low Power
Modes 1
(8M/4M/2M bits)
DPD
(Data Invalid)
/CS=VIH, /ZZ=VIL
Standby Mode Characteristics
Mode
Memory Cell Data
Standby Current(uA)
Wait Time(us)
Standby
Valid
70 (ISB1)
0
Deep Power Down Mode
Invalid
10 (ISB0)
200
¼ valid
40 (ISB0a)
0
½ valid
50 (ISB0b)
0
valid
70 (ISB0c)
0
Low Power Modes
6
Revision 0.5
Aug. 2006
CMP0817BAx-E
READ CYCLE (1)
CMOS LPRAM
(Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tOH
Data Out
READ CYCLE (2)
tAA
Previous Data Valid
Data Valid
(/ZZ=/WE=VIH)
tRC
Address
tOH
tAA
tCO
/CS
tHZ
tBA
/UB, /LB
tBHZ
tOE
/OE
tOLZ
Data Out
tOHZ
tBLZ
tLZ
High-Z
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
PAGE READ CYCLE
(/ZZ=/WE=VIH, 16 words access)
tMRC
tRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
tAA
A4~A18
tOH
tCO
/CS
tHZ
tBA
/UB, /LB
tBHZ
tOE
/OE
tOLZ
tBLZ
Data Out
High-Z
tLZ
tPAA
tPAA
Data Valid
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tOHZ
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
7
Revision 0.5
Aug. 2006
CMP0817BAx-E
WRITE CYCLE (1)
CMOS LPRAM
(/WE controlled, /ZZ=VIH)
tWC
Address
tCW(2)
tWR(4)
/CS
tAW
tBW
/UB, /LB
tWP(1)
/WE
tAS(3)
tDW
Data in
tWHZ
Data Out
WRITE CYCLE (2)
tDH
Data Valid
High-Z
High-Z
tOW
Data Undefined
(/CS controlled, /ZZ=/WE=VIH)
tWC
Address
tAS(3)
tWR(4)
tCW(2)
/CS
tAW
tBW
/UB, /LB
tWP(1)
/WE
tDW
Data in
Data Out
WRITE CYCLE (3)
tDH
Data Valid
High-Z
High-Z
(/UB, /LB controlled, /ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
/CS
tAW
tBW
/UB, /LB
tAS(3)
tWP(1)
/WE
tDW
Data in
Data Out
tDH
Data Valid
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
8
Revision 0.5
Aug. 2006
CMP0817BAx-E
PAGE WRITE CYCLE
CMOS LPRAM
(Address controlled, /ZZ=VIH)
tMRC
tPC
tWC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
A4~A18
/CS
/UB, /LB
tAS(3)
/WE
tDW
Data in
High-Z
tDH
Data Valid
tDW
tDH
Data Valid
tDW
Data Valid
tWHZ
Data Out
tDH
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
High-Z
tOW
Data Undefined
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
9
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
LOW POWER MODES
1. Mode Register Set
A18 ~ A5
A4
A3
A2
0
1
Array On/Off
on /ZZ
Half Selection
Array Refresh Area
A1
A0
Array Refresh Area
Half Selection (Top / Bottom)
A1
A0
Type
A2
Type
0
0
Full Array (Default)
0
Bottom (Default)
0
1
RFU1)
1
Top
1
0
½ Array
1
1
¼ Array
Array On/Off on /ZZ
1. RFU : Reserved for the Future Use
A3
Type
0
Partial Array Refresh Mode (Default)
1
Reduced Memory Size Mode
Note: The RMS(Reduced Memory Size) mode is enabled after
/ZZ goes high and remains enabled after /ZZ goes high. To
change to a different mode, the mode register will have to be
rewritten.
2. MRS Update
tWC
Address
tAS(3)
tCW(2)
tWR(4)
/CS
tAW
tBW
/UB, /LB
tWP(1)
/WE
/ZZ
tZZWE
Register Write Start
Register Write
Complete
Register Update
Complete
The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any
updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a
don’t care When /ZZ is low during the register updates.
10
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
3. Deep Power Down Mode Entry/Exit
tZZmin
/ZZ
vih
vil
tCDR
tR
/CS
Parameter
Description
Min
Max
Units
tCDR
Chip Deselect to ZZ Low
0
-
ns
tR(Deep Power Down Mode only)
Operation Recovery Time
200
-
us
tZZmin
Low Power Mode Time
10
-
us
4. Address Information
Partial Array Refresh Mode (A3=0, A4=1)
A2
A1,A0
Refresh Section
Address
Size
Density
0
11
1/4
00000h-1FFFFh
128Kbx16
2Mb
0
10
1/2
00000h-3FFFFh
256Kbx16
4Mb
X
00
Full
00000h-7FFFFh
512Kbx16
8Mb
1
11
1/4
60000h-7FFFFh
128Kbx16
2Mb
1
10
1/2
40000h-7FFFFh
256Kbx16
4Mb
Reduced Memory Size Mode (A3=1, A4=1)
A2
A1,A0
Refresh Section
Address
Size
Density
0
11
1/4
00000h-1FFFFh
128Kbx16
2Mb
0
10
1/2
00000h-3FFFFh
256Kbx16
4Mb
1
11
1/4
60000h-7FFFFh
128Kbx16
2Mb
1
10
1/2
40000h-7FFFFh
256Kbx16
4Mb
11
Revision 0.5
Aug. 2006
CMP0817BAx-E
CMOS LPRAM
PACKAGE DIMENSION
Unit : millimeters
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
Bottom View
B
A1 INDEX MARK
B1
B
0.05
0.05
6
5
4
3
2
1
A
B
C
#A1
C
C
C1
D
C1/2
E
F
G
H
B/2
0.25/Typ.
E2
D
A
Y
0.85/Typ.
E
Detail A
E1
0.30
Side View
C
-
Min
Typ
A
-
0.75
Max
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
7.90
8.00
8.10
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
1.00
-
E1
-
0.75
-
E2
0.20
0.25
0.30
Y
-
-
0.08
12
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
Revision 0.5
Aug. 2006
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