AT9933 Hysteretic Boost-Buck (Ćuk) LED Driver IC Features General Description • • • • • • • • Constant Current LED Driver Steps Input Voltage Up or Down Low Electromagnetic Interference (EMI) Variable Frequency Operation Internal 75V Linear Regulator Input and Output Current Sensing Input Current Limit Enable and Pulse-width Modulation (PWM) Dimming • Ambient Temperature Rating of up to 125°C The AT9933 is a variable frequency PWM controller IC, designed to control an LED lamp driver using a low-noise boost-buck (Ćuk) topology. It uses patent-pending Hysteretic Current-mode control to regulate both the input and the output currents. This enables superior input surge immunity without the necessity for complex loop compensation. Input current control enables current limiting during Startup, Input Undervoltage and Output Overload conditions. The AT9933 provides a low-frequency PWM dimming input that can accept an external control signal with a duty cycle of 0%–100% and a high dimming ratio. Applications This AT9933-based LED driver is ideal for LED lamps. The part is rated for up to 125°C ambient temperatures. • LED Lighting Applications Package Type 8-lead SOIC (Top View) VIN 1 8 REF CS1 2 7 CS2 GND 3 6 VDD GATE 4 5 PWMD See Table 2-1 for pin information. 2016 Microchip Technology Inc. DS20005597A-page 1 AT9933 Functional Block Diagram Regulator VIN Input Comparator VDD 7.5V CS1 100mV GATE 0mV CS2 Output Comparator 1.25V REF PWMD GND AT9933 DS20005597A-page 2 2016 Microchip Technology Inc. AT9933 Typical Application Circuit C1 D2 (optional) L2 L1 VDC RD - CD D3 D1 Q1 VO + RCS1 RCS2 RS1 C2 VIN GATE RREF1 VDD RS2 PWMD CS1 CS2 GND REF AT9933 RREF2 C3 2016 Microchip Technology Inc. DS20005597A-page 3 AT9933 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VIN to GND ................................................................................................................................................–0.5V to +75V CS1, CS2, PWMD and GATE to GND ............................................................................................. –0.3V to VDD +0.3V VDD(MAX) ................................................................................................................................................................. +12V Operating Temperature Range............................................................................................................. –40°C to +125°C Junction Temperature.......................................................................................................................................... +150°C Storage Temperature Range ............................................................................................................... –65°C to +150°C Continuous Power Dissipation (TA = +25°C): 8-lead SOIC ............................................................................................................................................ 700 mW † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Specifications are at TA = 25°C, VIN = Open and VDD = 7.5V unless otherwise noted. Parameter Sym. Min. Typ. Max. Unit Conditions Input DC Supply Voltage Range VINDC Note 3 — 75 V Shutdown Mode Supply Current IINSD — 0.5 1 mA VDD 7 7.5 9 V VIN = 8V–75V, IDD(EXT) = 0, 500 pF capacitor at GATE, PWMD = GND (Note 1) UVLO 6.35 6.7 7.05 V VDD rising (Note 1) ∆UVLO — 500 — mV 1.212 1.25 1.288 1.187 1.25 1.312 VREFLINE 0 — 20 mV IREF –0.01 — 500 µA VREFLOAD 0 — 10 mV INPUT DC input voltage (Note 1 and Note 2) PWMD connected to GND, VIN = 12V (Note 2) INTERNAL REGULATOR Internally Regulated Voltage VDD Undervoltage Lockout Threshold VDD Undervoltage Lock-out Hysteresis REFERENCE REF Pin Voltage 0°C < TA < +85°C REF Pin Voltage –40°C < TA < +125°C Line Regulation of Reference Voltage Reference Output Current Range Load Regulation of Reference Voltage V VREF REF bypassed with a 0.1 µF capacitor to GND, IREF = 0, PWMD = 5V REF bypassed with a 0.1 µF capacitor to GND, IREF = 0, VDD = 7V–9V, PWMD = 5V REF bypassed with a 0.1 µF capacitor to GND, IREF = 0, VDD = 7V–9V, PWMD = 5V REF bypassed with a 0.1 µF capacitor to GND, IREF = 0 µA–500 µA, PWMD = 5V PWM DIMMING — — 0.8 V VDD = 7V–9V (Note 1) PWMD Input Low Voltage VPWMD(LO) PWMD Input High Voltage VPWMD(HI) 2 — — V VDD = 7V–9V (Note 1) Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC. 2: Also limited by package power dissipation limit, whichever is lower 3: Depends on the current drawn by the part. See Section 4.0 “Application Information” DS20005597A-page 4 2016 Microchip Technology Inc. AT9933 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Specifications are at TA = 25°C, VIN = Open and VDD = 7.5V unless otherwise noted. Parameter Sym. PWMD Pull-down Resistance RPWMD GATE DRIVER GATE Short Circuit Current ISOURCE GATE Sinking Current ISINK GATE Output Rise Time TRISE GATE Output Fall Time TFALL INPUT CURRENT SENSE COMPARATOR Min. Typ. Max. Unit 50 100 150 kΩ VPWMD = 5V 0.165 0.165 — — — — 30 30 — — 50 50 A A ns ns VGATE = 0V VGATE = VDD CGATE = 500 pF CGATE = 500 pF Voltage required to turn on GATE VTURNON1 85 100 115 mV Voltage required to turn off GATE VTURN- –15 0 15 mV Delay to Output (Turn-on) TD1,ON — 150 250 ns Delay to Output (Turn-off) TD1,OFF — 150 250 ns OFF1 Conditions CS2 = 200 mV, CS1 increasing, GATE goes LOW to HIGH (Note 1) CS2 = 200 mV, CS1 decreasing, GATE goes HIGH to LOW (Note 1) CS2 = 200 mV, CS1 = 50 mV to +200 mV step CS2 = 200 mV, CS1 = 50 mV to –100 mV step OUTPUT CURRENT SENSE COMPARATOR CS1 = 200 mV, CS2 increasing, GATE goes LOW to HIGH (Note 1) VTURNCS1 = 200 mV, CS2 decreasing, Voltage required to turn off GATE –15 0 15 mV GATE goes HIGH to LOW (Note 1) OFF2 CS1 = 200 mV, Delay to Output (Turn-on) TD2,ON — 150 250 ns CS2 = 50 mV to +200 mV step CS1 = 200 mV, Delay to Output (Turn-off) TD2,OFF — 150 250 ns CS2 = 50 mV to –100 mV step Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC. 2: Also limited by package power dissipation limit, whichever is lower 3: Depends on the current drawn by the part. See Section 4.0 “Application Information” Voltage required to turn on GATE VTURNON2 85 100 115 mV Sym. Min. Typ. Max. Unit TA –40 — +125 °C TEMPERATURE SPECIFICATIONS Parameter Conditions TEMPERATURE RANGE Operating Temperature Junction Temperature TJ — — +150 °C Storage Temperature TS –65 — +150 °C JA — +101 — PACKAGE THERMAL RESISTANCE 8-lead SOIC °C/W Note 1 Note 1: Mounted on a FR-4 board, 25 mm x 25 mm x 1.57 mm 2016 Microchip Technology Inc. DS20005597A-page 5 AT9933 2.0 PIN DESCRIPTION The details on the pins of AT9933 are listed on Table 2-1. Refer to Package Type for the location of the pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name 1 VIN This pin is the input of an 8V–75V voltage regulator. 2 CS1 This pin is used to sense the input and output currents of the boost-buck converter. It is a non-inverting input of the internal comparator. 3 GND This is the ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. 4 GATE This pin is the output gate driver for an external N-channel power Metal-oxide Semiconductor Field-effect Transistor (MOSFET). 5 PWMD When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to a voltage greater than 2V will enable the gate driver output. 6 VDD This is a power supply pin for all internal circuits. It must be bypassed to GND with a low-ESR capacitor greater than 0.1 µF. 7 CS2 This pin is used to sense the input and output currents of the boost-buck converter. It is a non-inverting input of the internal comparator. 8 REF This pin provides accurate reference voltage. It must be bypassed with a 0.01 µF–0.1 µF capacitor to GND. DS20005597A-page 6 Description 2016 Microchip Technology Inc. AT9933 DETAILED DESCRIPTION 3.1 Power Topology The AT9933 is optimized to drive a Continuous Conduction Mode (CCM) boost-buck DC/DC converter topology commonly referred to as Ćuk converter. (Refer to Typical Application Circuit.) This power converter topology offers numerous advantages useful for driving high-brightness light-emitting diodes (HB LED). These advantages include step-up or step-down voltage conversion ratio and low input and output current ripple. The output load is decoupled from the input voltage with a capacitor, making the driver inherently failure-safe for the output load. The AT9933 offers a simple and effective control technique for a boost-buck LED driver. It uses two Hysteretic mode controllers—one for the input and one for the output. The outputs of these two hysteretic comparators are ANDED and used to drive the external FET. This control scheme gives accurate current control and constant output current in the presence of input voltage transients without the need for complicated loop design. 3.2 Input Voltage Regulator The AT9933 can be powered directly from its VIN pin that can withstand a maximum voltage of up to 75V. When a voltage is applied to the VIN pin, the AT9933 seeks to regulate a constant 7.5V (typical) at the VDD pin. The regulator also has a built-in undervoltage lockout which shuts off the IC when the voltage at the VDD pin falls below the UVLO threshold. The VDD pin must be bypassed by a low-ESR capacitor (≥0.1 μF) to provide a low-impedance path for the high frequency current of the output gate driver. The input current drawn from the VIN pin is the sum of the 1 mA current drawn by the internal circuit and the current drawn by the gate driver, which in turn depends on the switching frequency and the gate charge of the external FET. Refer to Equation 3-1. EQUATION 3-1: the VDD is greater than the undervoltage lockout. Thus, under certain conditions, the converter will be able to start at VIN voltages of less than 8V. The start/stop voltages at the VIN pin can be determined using the maximum voltage drop across the linear regulator as a function of the current drawn. The data for ambient temperatures 25ºC and 125ºC are shown in Figure 3-1 below: 3.5 Voltage Drop (V) 3.0 3.0 2.5 2.0 125OC 1.5 25OC 1.0 0.5 0 0 3.3 Minimum Input Voltage at VIN Pin The minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. The internal linear regulator will control the voltage at the VDD pin when VIN is between 8V and 75V. However, when the VIN is less than 8V, the converter will still function as long as 2016 Microchip Technology Inc. 2 FIGURE 3-1: Input Current. 3 4 5 IIN (mA) 6 7 Maximum Voltage Drop vs. Assume an ambient temperature of 125°C. Provided that the IC is driving a 15 nC gate charge FET at 300 kHz, the total input current is estimated to be 5.5 mA (using Equation 3-1). At this input current, the maximum voltage drop from Figure 3-1 can be approximately estimated to be VDROP = 2.7V. However, before the IC starts switching, the current drawn will be 1 mA. At this current level, the voltage drop is approximately VDROP1 = 0.5V. Thus, the start/stop VIN voltages can be computed as shown in Equation 3-2 and Equation 3-3: EQUATION 3-2: V IN – START = UVLO MAX + V DROP1 = 6.95V + 0.5V = 7.45V EQUATION 3-3: V IN – STOP = UVLO MAX – UVLO + V DROP = 6.95V – 0.5V + 2.7V I IN = 1mA + Q G f S In the above equation, fS is the switching frequency, and QG is the gate charge of the external FET which can be obtained from the data sheet of the FET. 1 = 9.15V Note: Since the gate driver draws too much current in this situation, VIN-START is less than VIN-STOP. The control IC will oscillate between on and off if the input voltage is between the start and stop voltages. In these circumstances, it is recommended that the input voltage be kept higher than VIN-STOP. The IC will operate normally if the input voltage is kept higher than 9.2V. DS20005597A-page 7 AT9933 In case of input transients that reduce the input voltage below 8V (e.g. Cold Crank condition in an automotive system), the VIN pin of the AT9933 can be connected to the MOSFET drain through a switching diode using a small (1 nF) capacitor between VIN and GND as long as the drain voltage does not exceed 75V. Since the drain of the FET is at a voltage equal to the sum of the input and output voltages, the IC will still be operational when the input goes below 8V. Therefore, a larger capacitor is needed at the VDD pin to supply power to the IC when the MOSFET is switched on. In this case, VDD UVLO cannot be relied upon to turn off the IC at low input voltages when input current levels can get too large. In such cases, the input current limit must be chosen to ensure that the input current is set to a safe level. 3.4 each time, ensuring a quick response time for the output current. The recommended PWM dimming frequency range is from 100 Hz to a few kilohertz. The flying capacitor in the Ćuk converter (C1) is initially charged to the input voltage VDC (through diodes D1 and D2). When the circuit is turned on and reaches Steady state, the voltage across C1 will be VDC+VO. In the absence of diode D2, when the circuit is turned off, capacitor C1 will discharge through the LEDs and the input voltage source VDC. Thus, during PWM dimming, if capacitor C1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. By adding diode D2, the voltage across capacitor C1 is held at VDC+VO even when the circuit is turned off, enabling the circuit to return quickly to its Steady state (and bypassing the start-up stage) upon being enabled. Reference An internally trimmed voltage reference of 1.25V is provided at the REF pin. The reference can supply a maximum output current of 500 µA to drive external resistor dividers. This reference can be used to set the current thresholds of the two comparators as shown in the Typical Application Circuit section. 3.5 Current Comparators The AT9933 features two identical comparators with a built-in 100 mV hysteresis. When the GATE is low, the inverting terminal is connected to 100 mV, but when the GATE is high, it is connected to GND. One comparator is used for the input current control and the other for the output current control. The input side hysteretic controller is in operation during Start-up, Overload and Input Undervoltage conditions. This ensures that the input current never exceeds the designed value. During normal operation, the input current is less than the programmed current. Therefore, the output of the input side comparator will be high. The output of the AND gate will then be dictated by the output current controller. The output side hysteretic comparator controls the external MOSFET during Steady state operation of the circuit. This comparator turns the MOSFET on and off based on the LED current. 3.6 PWM Dimming PWM Dimming can be achieved by applying a TTL-compatible square wave signal to the PWM pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or connected to GND, the gate driver is disabled and the external MOSFET turns off. The signal at the PWMD pin inhibits the driver only and the IC need not go through the entire start-up cycle DS20005597A-page 8 2016 Microchip Technology Inc. AT9933 4.0 APPLICATION INFORMATION 4.4 4.1 Overvoltage Protection The choice of the resistor dividers to set the input and output current levels is illustrated by means of the design example given below. Overvoltage protection can be added by splitting the output side resistor RS2 into two components and adding a Zener diode D3. (Refer to Figure 4-1 below.) When there is an Open LED condition, the diode D3 will clamp the output voltage and the Zener diode current will be regulated by the sum of RS2A and RCS2. 4.2 The parameters of the power circuit are: V IN MIN = 9.01V V IN MAX = 16V V O = 28V I O = 0.35A f S MIN = 300kHz Damping Circuit The Ćuk converter is inherently unstable when the output current is being controlled. An uncontrolled input current will lead to an undamped oscillation between L1 and C1, causing excessively high voltages across capacitor C1. To prevent these oscillations, a damping circuit consisting of RD and CD is applied across the capacitor C1. This damping circuit will stabilize the circuit and help in the proper operation of the converter. 4.3 Design Example Using these parameters, the values of the power stage inductors and capacitor can be computed. (See figures below.) Refer to Application Note AN-H51 for more details. L 1 = 82H L 2 = 150H Design and Operation of the Boost-buck Converter C 1 = 0.22F The input and output currents for this design are: I IN MAX = 1.6A For details on the design for a boost-buck converter using the AT9933 and the calculation of the damping components, refer to Application Notes AN-H51 and AN-H58. I IN = 0.21A I O = 350mA I O = 87.5mA C1 D2 (optional) L2 L1 RD VDC - CD CO D1 Q1 VO + RCS2 RCS1 RS1 RS2A C2 VIN GATE RREF1 FIGURE 4-1: D3 VDD PWMD CS1 CS2 GND REF AT9933 RS2B RREF2 C3 Design Example Circuit. 2016 Microchip Technology Inc. DS20005597A-page 9 AT9933 4.5 Current Limits The current sense resistor RCS2, combined with the other resistors RS2 and RREF2, determines the output current limits. The resistors can be chosen using Equation 4-1 and Equation 4-2. EQUATION 4-1: RS I R CS = 1.2V ------------- – 0.05V R REF Where I is the current (either IO or IIN) and ∆I is the peak-to-peak ripple in the current (either ∆IO or ∆IIN). Using IO = 350 mA and ∆IO = 87.5 mA in Equation 4-1 and Equation 4-2, RCS2 = 1.78Ω and RS2/RREF2 = 0.5625. Before the design of the output side is complete, overvoltage protection has to be included in the design. For this application, choose a 33V Zener diode. This is the voltage at which the output will clamp in case of an Open LED condition. For a 350 mW diode, the maximum current rating at 33V works out to about 10 mA. Using a 2.5 mA current level during Open LED conditions, and assuming the same RS2/RREF2 ratio, the Zener current limiting resistor can be determined as illustrated in Equation 4-6. EQUATION 4-6: R CS + R S2A = 120 EQUATION 4-2: RS I R CS = 0.1V ------------- + 0.1V R REF Where I is the current (either IO or IIN) and ∆I is the peak-to-peak ripple in the current (either ∆IO or ∆IIN). For the input side, the current level used in the equations should be larger than the maximum input current, so that it does not interfere with the normal operation of the circuit. The peak input current can be computed as shown in Equation 4-3. EQUATION 4-3: I IN I IN PK = I IN MAX + ---------- 2 = 1.706A Assuming a 30% peak-to-peak ripple when the converter is in Input Current Limit mode, the minimum value of the input current is calculated as seen in Equation 4-4. Choose the following values for the resistors: RCS2 = 1.65Ω, 1/4W, 1% RREF2 = 10 kΩ, 1/8W, 1% RS2A = 100Ω, 1/8W, 1% RS2B = 5.23 kΩ, 1/8W, 1% The current sense resistor needs to be at least a 1/4W, 1% resistor. Similarly, using IIN = 2.1A and ∆IIN = 0.3 x IIN = 0.63 in Equation 4-1 and Equation 4-2, the following values can be determined: R S1 --------------= 0.442 R REF1 R CS1 = 0.228 P RCS1 = I 2 IN LIM R CS1 = 1W Choose the following values for the resistors: RCS1 = parallel combination of three 0.68Ω, 1/2W, 5% resistors EQUATION 4-4: I LIM MIN = 0.85 I IN LIM RREF1 = 10kΩ, 1/8W, 1% RS1 = 4.42kΩ, 1/8W, 1% Setting I LIM MIN = 1.05 I IN PK The current level to limit the converter can then be computed. See equation Equation 4-5. EQUATION 4-5: 1.05 I IN LIM = ---------- I IN PK 0.85 = 2.1A DS20005597A-page 10 2016 Microchip Technology Inc. AT9933 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-lead SOIC XXXXXXXX e3 YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example AT9933LG e3 1645 222 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 2016 Microchip Technology Inc. DS20005597A-page 11 AT9933 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. DS20005597A-page 12 2016 Microchip Technology Inc. AT9933 APPENDIX A: REVISION HISTORY Revision A (October 2016) • Converted Supertex Doc# DSFP-AT9933 to Microchip DS20005597A • Changed the quantity of the 8-lead SOIC package from 3000/Reel to 3300/Reel • Made minor text changes throughout the document 2016 Microchip Technology Inc. DS20005597A-page 13 AT9933 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. Device XX - Package Options X - Environmental X Media Type Device: AT9933 = Hysteretic Boost-Buck (Ćuk) LED Driver IC Package: LG = 8-lead SOIC Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 3300/Reel for an LG Package DS20005597A-page 14 Example: a) AT9933LG-G: Hysteretic Boost-buck (Ćuk) LED Driver IC, 8-lead SOICPackage, 3300/Reel 2016 Microchip Technology Inc. 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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. 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