11.3 Gbps Active Back-Termination, Differential Laser Diode Driver ADN2526 FEATURES GENERAL DESCRIPTION 3.3 V operation Up to 11.3 Gbps operation Typical 24 ps rise/fall times Full back-termination of output transmission lines Drives TOSAs with resistances ranging from 5 Ω to 50 Ω Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Voltage input control for bias and modulation currents Data inputs sensitivity: 150 mV p-p diff Automatic laser shutdown (ALS) Cross point adjustment (CPA) XFP-compliant bias current monitor SFP+ MSA compliant Optical evaluation board available Compact 3 mm × 3 mm LFCSP The ADN2526 laser diode driver is designed for direct modulation of packaged laser diodes that have a differential resistance ranging from 5 Ω to 50 Ω. The active back-termination in the ADN2526 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. ADN2526 is an SFP+ MSAcompliant device, and its small package and enhanced ESD protection provide the optimum solution for compact modules where laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average optical power and extinction ratio control schemes, including closed-loop or look-up table control. The automatic laser shutdown (ALS) feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with a LVTTL logic source. APPLICATIONS SONET OC-192 and SDH STM-64 optical transceivers 10 Gb Fibre Channel transceivers 10 Gb Ethernet optical transceivers SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules The product is available in a space-saving 3 mm × 3 mm LFCSP specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM VCC CPA ALS VCC ADN2526 VCC IMODP 50Ω 50Ω 50Ω GND DATAP IMOD IMODN VCC CROSS POINT ADJUST DATAN IBMON IBIAS 800Ω 800Ω 200Ω VEE BSET 200Ω 2Ω 07511-001 MSET 200Ω Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADN2526 TABLE OF CONTENTS Features .............................................................................................. 1 Automatic Laser Shutdown (ALS) ........................................... 11 Applications ....................................................................................... 1 Modulation Current ................................................................... 11 General Description ......................................................................... 1 Load Mistermination ................................................................. 12 Functional Block Diagram .............................................................. 1 Crosspoint Adjustment.............................................................. 13 Revision History ............................................................................... 2 Power Sequence .......................................................................... 13 Specifications..................................................................................... 3 Power Consumption .................................................................. 13 Thermal Specifications ................................................................ 4 Applications Information .............................................................. 14 Absolute Maximum Ratings............................................................ 6 Typical Application Circuit ....................................................... 14 ESD Caution .................................................................................. 6 Layout Guidelines....................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Design Example .......................................................................... 15 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 16 Theory of Operation ...................................................................... 10 Ordering Guide .......................................................................... 16 Input Stage ................................................................................... 10 Bias Current ................................................................................ 10 REVISION HISTORY 8/09—Rev. 0 to Rev. A Changes to θJ-PAD Maximum Value (Table 2)................................. 4 Changes to Figure 5 and Figure 6 ................................................... 8 1/09—Revision 0: Initial Version Rev. A | Page 2 of 16 ADN2526 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at TA = 25°C, IMOD 1 = 40 mA, unless otherwise noted. D Table 1. Parameter BIAS CURRENT (IBIAS) Bias Current Range Bias Current While ALS Asserted Compliance Voltage 2 MODULATION CURRENT (IMODP, IMODN) Modulation Current Range Modulation Current While ALS Asserted Rise Time (20% to 80%) 3, 4 Fall Time (20% to 80%)3, 4 Random Jitter3, 4 Deterministic Jitter3, 5 Pulse Width Distortion3, 4 Differential |S22| Compliance Voltage2 DATA INPUTS (DATAP, DATAN) Input Data Rate Differential Input Swing Differential |S11| Input Termination Resistance BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain BSET Input Resistance MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain MSET Input Resistance BIAS MONITOR (IBMON) IBMON to IBIAS Ratio Accuracy of IBIAS to IBMON Ratio AUTOMATIC LASER SHUTDOWN (ALS) VIH VIL IIL IIH ALS Assert Time ALS Negate Time Min Typ Max Unit Test Conditions/Comments 100 300 VCC VCC mA μA V V ALS = high IBIAS = 100 mA IBIAS = 10 mA 80 0.5 32.5 32.5 0.9 12 5 mA diff mA diff ps ps ps rms ps p-p ps dB dB V RLOAD = 5 Ω to 50 Ω differential ALS = high −16.8 100 Gbps V p-p diff dB Ω NRZ Differential, ac-coupled f < 10 GHz, Z0 = 100 Ω differential Differential 90 1000 mA/V Ω 10 0.6 0.6 10 24 24 0.4 7.2 2 −10 −14 VCC − 1.1 VCC + 1.1 0.15 11.3 1.6 50 78 1000 100 10 −5.0 −4.0 −2.5 −2 +5.0 +4.0 +2.5 +2 μA/mA % % % % 0.8 +30 200 2 V V μA μA μs 10 μs 2.0 −30 0 mA/V Ω Rev. A | Page 3 of 16 Includes pulse width distortion PWD = (|THIGH – TLOW|)/2 5 GHz < f < 10 GHz, Z0 = 50 Ω differential f < 5 GHz, Z0 = 50 Ω differential See Figure 29 10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ 20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ 40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ 70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ Rising edge of ALS to falling edge of IBIAS and IMOD below 10% of nominal, see Figure 2 Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal, see Figure 2 ADN2526 Parameter POWER SUPPLY VCC ICC 6 ISUPPLY 7 CPA Cross Point Min Typ Max Unit Test Conditions/Comments 3.0 3.3 46 74 1.88 50 3.6 55 95 V mA mA V % VBSET = VMSET = 0 V VBSET = VMSET = 0 V; ISUPPLY = ICC + IMODP + IMODN In NC mode (refer to Table 4) From an optical eye in NC mode 1 IMOD is the total modulation current sink capability for a differential driver. IMOD = IMODP + IMODN, the dynamic current sank by the IMODP and IMODN pins. Refers to the voltage between the pin for which the compliance voltage is specified and VEE. The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps. 4 Measured using the high speed characterization circuit shown in Figure 3. 5 The pattern used is K28.5 (00111110101100000101) at a 11.3 Gbps rate. 6 Only includes current in the VCC pins. 7 Without laser diode loaded. 2 3 THERMAL SPECIFICATIONS Table 2. Min 2.6 65 Typ 5.8 72.2 Max 10.7 79.4 125 Unit °C/W °C/W °C Conditions/Comments Thermal resistance from junction to bottom of exposed pad Thermal resistance from junction to top of package ALS NEGATE TIME ALS t IBIAS AND IMOD 90% 10% t ALS ASSERT TIME Figure 2. ALS Timing Diagram Rev. A | Page 4 of 16 07511-002 Parameter θJ-PAD θJ-TOP IC Junction Temperature ADN2526 VEE VEE VEE GND 10Ω 1kΩ VBSET TP1 TP2 10nF GND VCC GND VEE VCC ADN2526 Z0 = 50Ω 10nF Z0 = 50Ω J2 DATAP IMODP GND GND GND GND Z0 = 50Ω 10nF Z0 = 50Ω Z0 = 25Ω J3 DATAN GND GND GND GND Z0 = 25Ω IMODN 35Ω GND VCC VCC MSET CPA ALS VMSET GND 10nF VEE VEE VCPA J8 J5 GND GND VEE VEE GND ATTENUATOR OSCILLOSCOPE ADAPTER BIAS TEE ATTENUATOR 50Ω GND GND BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219 ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER ATTENUATOR: PASTERNACK PE-7046 2.92mm 20dB ATTENUATOR 22µF VEE GND GND 50Ω ADAPTER GND 70Ω Z = 50Ω 35Ω 0 GND GND Z0 = 50Ω BIAS TEE GND Figure 3. High Speed Characterization Circuit Rev. A | Page 5 of 16 07511-003 BSET IBMON IBIAS ADN2526 ABSOLUTE MAXIMUM RATINGS VEE connected to supply ground. Table 3. Parameter Supply Voltage, VCC to VEE IMODP, IMODN to VEE DATAP, DATAN to VEE All Other Pins HBM ESD on IMODP, IMODN HBM ESD on All Other Pins Junction Temperature Storage Temperature Range Soldering Temperature (Less Than 10 sec) Rating −0.3 V to +4.2 V 1.1 V to 4.75 V VCC − 1.8 V to VCC − 0.4 V −0.3 V to VCC + 0.3 V 200 V 1 kV 150°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 6 of 16 ADN2526 CPA 2 ADN2526 11 IBMON ALS 3 TOP VIEW (Not to Scale) 10 IBIAS 12 BSET 9 VEE VCC 8 VCC 5 VEE 4 IMODP 7 PIN 1 INDICATOR IMODN 6 MSET 1 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VCC OR THE GND PLANE. 07511-004 14 DATAP 13 VCC 15 DATAN 16 VCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (EPAD) 1 Mnemonic MSET CPA ALS VEE VCC IMODN IMODP VCC VEE IBIAS IBMON BSET VCC DATAP DATAN VCC Exposed Pad (EPAD) I/O 1 AI AI DI P P AI AI P P AI AO AI P AI AI P P Description Modulation Current Control Input. Adjustable Cross Point. Defaults to not connected (NC) mode (floating). Automatic Laser Shutdown. Negative Power Supply. Normally connected to system ground. Positive Power Supply. Modulation Current Sink, Negative. Modulation Current Sink, Positive. Positive Power Supply. Negative Power Supply. Normally connected to system ground. Bias Current Sink. Bias Current Monitoring Output. Bias Current Control Input. Positive Power Supply. Data Signal Positive Input. Data Signal Negative Input. Positive Power Supply. The exposed pad on the bottom of the package must be connected to VCC or the GND plane. AI = analog input, DI = digital input, P = power, AO = analog output. Rev. A | Page 7 of 16 ADN2526 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 3.3 V, unless otherwise noted. 27.0 9 26.5 8 7 6 25.5 JITTER (ps) 25.0 24.5 5 4 3 24.0 2 23.5 0 20 40 60 80 100 IMOD (mA) 0 07511-005 23.0 0 20 100 80 Figure 8. Deterministic Jitter vs. IMOD 27.0 0.35 26.5 0.30 26.0 IBIAS = 100 0.25 TOTAL IVCC (A) 25.5 25.0 24.5 IBIAS = 50 0.20 0.15 IBIAS = 10 0.10 24.0 0.05 23.5 0 20 40 60 80 100 IMOD (mA) 0 07511-006 23.0 0 10 20 30 40 50 60 70 80 90 100 IMOD (mA) Figure 6. Fall Time vs. IMOD Figure 9. Total Supply Current vs. IMOD 0.7 0 0.6 –5 –10 DIFFERENTIAL |S11| (dB) 0.5 0.4 0.3 0.2 0.1 –15 –20 –25 –30 0 0 20 40 60 IMOD (mA) 80 100 07511-007 –35 Figure 7. Random Jitter vs. IMOD –40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz) Figure 10. Differential |S11| Rev. A | Page 8 of 16 07511-009 FALL TIME (ps) 60 IMOD (mA) Figure 5. Rise Time vs. IMOD JITTER (ps) 40 07511-008 1 07511-036 RISE TIME (ps) 26.0 ADN2526 0 DIFFERENTIAL |S22| (dB) –5 –10 –15 –20 –25 –30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz) 07511-035 –40 07511-014 –35 Figure 11. Differential |S22| Figure 14. Electrical Eye Diagram (11.3 Gbps, PRBS31, IMOD = 80 mA) 16 14 OCCURRENCE (%) 12 10 8 6 07511-015 4 0 23 24 25 26 27 RISE TIME (ps) 28 29 30 07511-012 2 Figure 15. Filtered SONET OC192 Optical Eye Diagram (for Reference) Figure 12. Worst-Case Rise Time Distribution (VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C) 16 14 10 8 6 07511-016 4 2 0 23 24 25 26 27 FALL TIME (ps) 28 29 30 07511-013 OCCURRENCE (%) 12 Figure 16. Filtered 10 Gb Ethernet Optical Eye Figure 13. Worst-Case Fall Time Distribution (VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C) Rev. A | Page 9 of 16 ADN2526 THEORY OF OPERATION 50Ω 50Ω ADN2526 C DATAP DATAN C 07511-018 As shown in Figure 1, the ADN2526 consists of an input stage and two voltage-controlled current sources for bias and modulation. The bias current, which is available at the IBIAS pin, is controlled by the voltage applied at the BSET pin and can be monitored at the IBMON pin. The differential modulation current, which is available at the IMODP and IMODN pins, is controlled by the voltage applied to the MSET pin. The output stage implements the active back-match circuitry for proper transmission line matching and power consumption reduction. The ADN2526 can drive a load having differential resistance ranging from 5 Ω to 50 Ω. The excellent back-termination in the ADN2526 absorbs the signal reflections from the TOSA end, enabling excellent optical eye quality, even though the TOSA is significantly misterminated. DATA SIGNAL SOURCE Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs BIAS CURRENT The bias current is generated internally using a voltage-to-current converter consisting of an internal operational amplifier and a transistor, as shown in Figure 19. VCC INPUT STAGE ADN2526 The input stage of the ADN2526 converts the data signal applied to the DATAP and DATAN pins to a level that ensures proper operation of the high speed switch. The equivalent circuit of the input stage is shown in Figure 17. R R IBMON BSET IBMON 800Ω IBIAS IBIAS DATAP 50Ω 200Ω VCC 200Ω 2Ω 07511-019 VCC GND Figure 19. Voltage-to-Current Converter Used to Generate IBIAS Figure 17. Equivalent Circuit of the Input Stage The DATAP and DATAN pins are terminated internally with a 100 Ω differential termination resistor. This minimizes signal reflections at the input, which can otherwise lead to degradation in the output eye diagram. It is not recommended to drive the ADN2526 with single-ended data signal sources. The ADN2526 input stage must be ac-coupled to the signal source to eliminate the need for matching between the commonmode voltages of the data signal source and the input stage of the driver (see Figure 18). The ac-coupling capacitors should have an impedance much less than 50 Ω over the required frequency range. Generally, this is achieved using 10 nF to 100 nF capacitors. The voltage-to-current conversion factor is set at 100 mA/V by the internal resistors, and the bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a 1 kΩ resistor between IBMON and VEE, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor must be used for the IBMON resistor (RIBMON). Any error in the value of RIBMON that is due to tolerances or to drift in its value over temperature contributes to the overall error budget for the IBIAS monitor voltage. If the IBMON voltage is connected to an ADC for analog-to-digital conversion, RIBMON should be placed close to the ADC to minimize errors due to voltage drops on the ground plane. The equivalent circuits of the BSET, IBIAS, and IBMON pins are shown in Figure 20, Figure 21, and Figure 22. In SFP+ MSA applications, the DATAP and DATAN pins need to be connected to the SFP+ connector directly. This connection requires enhanced ESD protection to support the SFP+ module hot plug-in application. Rev. A | Page 10 of 16 VCC VCC BSET 800Ω 200Ω Figure 20. Equivalent Circuit of the BSET Pin 07511-020 DATAN 07511-017 50Ω ADN2526 IBIAS VCC VCC Table 5. ALS Functions 2kΩ ALS Logic State High Low Floating 07511-021 100Ω 2Ω The ALS pin is compatible with 3.3 V CMOS and LVTTL logic levels. Its equivalent circuit is shown in Figure 24. Figure 21. Equivalent Circuit of the IBIAS Pin VCC IBIAS and IMOD Disabled Enabled Enabled VCC VCC 500Ω VCC 100Ω ALS 07511-024 40kΩ 2kΩ Figure 24. Equivalent Circuit of the ALS Pin 100Ω MODULATION CURRENT IBMON 07511-022 VCC Figure 22. Equivalent Circuit of the IBMON Pin The recommended configuration for BSET, IBIAS, and IBMON is shown in Figure 23. The modulation current can be controlled by applying a dc voltage to the MSET pin. This voltage is converted into a dc current by using a voltage-to-current converter using an operational amplifier and a bipolar transistor, as shown in Figure 25. TO LASER CATHODE VCC IBIAS IMODP IBIAS 50Ω ADN2526 GND IBMON gm × VO FROM INPUT STAGE R 1kΩ MSET 07511-023 VBSET IMODN IBMON BSET IMOD 800Ω VO Figure 23. Recommended Configuration for the BSET, IBIAS, and IBMON Pins The circuit used to drive the BSET voltage must be able to drive the 1 kΩ input resistance of the BSET pin. For proper operation of the bias current source, the voltage at the IBIAS pin must be between the compliance voltage specifications for this pin over supply, temperature, and bias current range (see Table 1). The maximum compliance voltage is specified for only two bias current levels (10 mA and 100 mA), but it can be calculated for any bias current by VCOMPLIANCE_MAX (V) = VCC (V) − 0.75 − 4.4 × IBIAS (1) See the Applications Information section for examples of headroom calculations. The function of the inductor, L, is to isolate the capacitance of the IBIAS output from the high frequency signal path. For recommended components, see Table 7. AUTOMATIC LASER SHUTDOWN (ALS) The ALS pin is a digital input that enables/disables both the bias and modulation currents, depending on the logic state applied, as shown in Table 5. 200Ω ADN2526 GND 07511-025 L Figure 25. Generation of Modulation Current on the ADN2526 This dc current is switched by the data signal applied to the input stage (DATAP and DATAN pins) and amplified by the output stage to generate the differential modulation current at the IMODP and IMODN pins. The output stage also generates the active back-termination, which provides proper transmission line termination. Active back-termination uses feedback around an active circuit to synthesize a broadband termination resistance. This provides excellent transmission line termination, while dissipating less power than a traditional resistor passive back-termination. A small portion of the modulation current flows in the virtual 50 Ω active back-termination resistor. All of the preset IMOD modulation current, the range specified in Table 1, flows into the external load. The equivalent circuits for MSET, IMODP, and IMODN are shown in Figure 26 and Figure 27. The two 25 Ω resistors in Figure 27 are not actual resistors. They represent the active back-termination resistance. Rev. A | Page 11 of 16 ADN2526 VCC VCC Using the resistance of the TOSA, the user can calculate the voltage range that should be applied to the MSET pin to generate the required modulation current range (see the example in the Applications Information section). MSET 07511-026 800Ω 200Ω Figure 26. Equivalent Circuit of the MSET Pin VCC IMODN VCC IMODP 25Ω 25Ω 3.3Ω 07511-027 3.3Ω Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side The recommended configuration of the MSET, IMODP, and IMODN pins is shown in Figure 28. See Table 7 for the recommended components. The circuit used to drive the MSET voltage must be able to drive the 1 kΩ resistance of the MSET pin. To be able to drive 80 mA modulation currents through the differential load, the output stage of the ADN2526 (the IMODP and IMODN pins) must be ac-coupled to the load. The voltages at these pins have a dc component equal to VCC and an ac component with single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is the case even if the load impedance is less than 50 Ω differential, because the transmission line characteristic impedance sets the peak-to-peak amplitude. For proper operation of the output stage, the voltages at the IMODP and IMODN pins must be between the compliance voltage specifications for these pins over supply, temperature, and modulation current range, as shown in Figure 30. See the Applications Information section for examples of headroom calculations. IMODP, IMODN IBIAS VCC ADN2526 L Z0 = 25Ω L VCC + 1.1V Z0 = 25Ω C IMODP NORMAL OPERATION REGION VCC TOSA Z0 = 25Ω MSET Z0 = 25Ω C IMODN VCC – 1.1V VEE L VCC VCC 07511-030 L 07511-028 VMSET Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins 220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 MAXIMUM TYPICAL MINIMUM 0 10 20 30 40 50 DIFFERENTIAL LOAD RESISTANCE (Ω) 60 Figure 30. Allowable Range for the Voltage at IMODP and IMODN LOAD MISTERMINATION Due to its excellent S22 performance, the ADN2526 can drive differential loads that range from 5 Ω to 50 Ω. In practice, many TOSAs have differential resistance less than 50 Ω. In this case, with 50 Ω differential transmission lines connecting the ADN2526 to the load, the load end of the transmission lines are misterminated. This mistermination leads to signal reflections back to the driver. The excellent back-termination in the ADN2526 absorbs these reflections, preventing their reflection back to the load. This enables excellent optical eye quality to be achieved, even when the load end of the transmission lines is significantly misterminated. The connection between the load and the ADN2526 must be made with 50 Ω differential (25 Ω single-ended) transmission lines so that the driver end of the transmission lines is properly terminated. 07511-029 IMOD/VMSET (mA/V) The ratio between the voltage applied to the MSET pin and the differential modulation current available at the IMODP and IMODN pins is a function of the load resistance value, as shown in Figure 29. Figure 29. MSET Voltage-to-Modulation Current Ratio vs. Differential Load Resistance Rev. A | Page 12 of 16 ADN2526 CROSSPOINT ADJUSTMENT The optical eye cross point is adjustable between 35% and 65% using the cross point adjust (CPA) control input. The equivalent circuit for the CPA pin is shown in Figure 31. In a default CPA setting, leave CPA unconnected (maintain pin-to-pin compatibility with the ADN2525). The internal bias circuit presents about 1.9 V at the CPA pin and the eye cross point is set to 50%. To set the cross point at various points, apply an external voltage to the CPA pin. junction-to-ambient thermal resistance (θJA) do not yield accurate results. THERMAL COMPOUND MODULE CASE TTOP DIE TJ THERMOCOUPLE PACKAGE T PAD 07511-032 PCB COPPER PLANE VIAS 7kΩ 7kΩ Figure 32. Typical Optical Module Structure 7kΩ The parameters in Table 6 can be used to estimate the IC junction temperature. VCC Table 6. Definitions 07511-031 CPA Figure 31. Equivalent Circuit for CPA Pin POWER SEQUENCE To ensure reliable operation, the recommended power-up sequence is: the supply rail to ADN2526 first, then the BSET pin, followed by the MSET pin, and, finally, the CPA pin. Parameter TTOP TPAD TJ P θJ-TOP Description Temperature at the top of the package Temperature at the package exposed paddle IC junction temperature Power dissipation Thermal resistance from the IC junction to the package top Thermal resistance from the IC junction to the package exposed paddle Unit °C °C °C W °C/W To turn off the ADN2526, the operation is reversed: shut down CPA first, then MSET, followed by BSET, and, last, the supply rail. θJ-PAD POWER CONSUMPTION TTOP and TPAD can be determined by measuring the temperature at points inside the module, as shown in Figure 32. The thermocouples should be positioned to obtain an accurate measurement of the package top and paddle temperatures. Using the model shown in Figure 33, the junction temperature can be calculated by ⎛V ⎞ P = VCC × ⎜ MSET + I SUPPLY ⎟ + VIBIAS × IBIAS 13.5 ⎝ ⎠ where: VCC is the power supply voltage. VMSET is the voltage applied to the MSET pin. ISUPPLY is the sum of the currents that flow into VCC, IMODP, and IMODN, which are sank by the ADN2526 when VBSET = VMSET = 0 V, expressed in amps (see Table 1). VIBIAS is the average voltage presented on the IBIAS pin. IBIAS is the bias current sank by the ADN2526. TJ = ( ) P × θ J −PAD × θ J −TOP + TTOP × θ J − PAD + TPAD × θ J −TOP θ J −PAD + θ J −TOP where: θJ-TOP and θJ-PAD are given in Table 2. P is the power dissipated by the ADN2526. TTOP θJ-TOP Considering VBSET/IBIAS = 10 mV/mA as the conversion factor from VBSET to IBIAS, the dissipated power becomes P ⎛V ⎞ V P = VCC × ⎜ MSET + I SUPPLY ⎟ + BSET × VIBIAS 13 . 5 10 ⎝ ⎠ θJ-PAD TPAD To ensure long-term reliable operation, the junction temperature of the ADN2526 must not exceed 125°C, as specified in Table 2. For improved heat dissipation, the SFP+ module case can work as a heat sink, as shown in Figure 32. A compact optical module is a complex thermal environment, and calculations of device junction temperature using the package Rev. A | Page 13 of 16 TTOP 07511-033 The power dissipated by the ADN2526 is given by °C/W Figure 33. Electrical Model for Thermal Calculations ADN2526 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT LAYOUT GUIDELINES Figure 34 shows the typical application circuit for the ADN2526. The dc voltages applied to the BSET and MSET pins control the bias and modulation currents. The bias current can be monitored as a voltage drop across the 1 kΩ resistor connected between the IBMON pin and GND. The ALS pin allows the user to turn on or turn off the bias and modulation currents, depending on the logic level applied to the pin. The data signal source must be connected to the DATAP and DATAN pins of the ADN2526 using 50 Ω transmission lines. The modulation current outputs, IMODP and IMODN, must be connected to the load (TOSA) using 50 Ω differential (25 Ω single-ended) transmission lines. It is recommended that the components shown in Table 7 be used between the ADN2526 and the TOSA for an example ac coupling circuit. For up-to-date component recommendations, contact your local Analog Devices, Inc., sales representative. Due to the high frequencies at which the ADN2526 operates, care should be taken when designing the PCB layout to obtain optimum performance. Well controlled transmission line impedance must be used for the high speed signal paths. The length of the transmission lines must be kept to a minimum to reduce losses and pattern-dependent jitter. The PCB layout must be symmetrical, on both the DATAP and DATAN inputs and the IMODP and IMODN outputs, to ensure a balance between the differential signals. All VCC and VEE pins must be connected to solid copper planes by using low inductance connections. When the connections are made through vias, multiple vias should be used in parallel to reduce the parasitic inductance. Each VEE pin must be locally decoupled with high quality capacitors. If proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each VEE pin. A 20 μF tantalum capacitor must be used as a general decoupling capacitor for the entire module. For guidelines on the surface-mount assembly of the ADN2526, see the Amkor Technology® Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages. Working with a TOSA laser sample, the circuit in Figure 34 delivers optical performance shown in Figure 15 and Figure 16. For additional applications information and optical eye performance of other laser samples, contact your local Analog Devices sales representative. Table 7. Recommended Components for AC-Coupling Component R1, R2 R3, R4 C3, C4 L2, L3 L6, L7 L1, L4, L5, L8 Value 36 Ω 200 Ω 100 nF 20 nH 0402 size ferrite 10 μH Description 0603 size resistor 0603 size resistor 0603 size capacitor, Phycomp 223878615649 0402 size inductor, Murata LQW15AN20NJ0 Murata BLM15HG102SN1 0603 size inductor, Murata LQM21FN100M70L VCC GND BSET R5 1kΩ GND C5 10nF TP1 L1 R1 L8 R4 VCC VCC BSET IBMON IBIAS VEE VCC VCC Z0 = 50Ω VCC L2 L7 Z0 = 25Ω DATAP DATAP C1 DATAN DATAN Z0 = 25Ω Z0 = 25Ω TOSA IMODN C2 VCC C4 GND ADN2526 Z0 = 50Ω Z0 = 25Ω IMODP VCC MSET CPA ALS VCC VEE GND L3 VCC C3 L6 VCC C6 10nF 3.3V VCC C7 200µF GND CPA ALS L4 R2 L5 R3 GND VCC Figure 34. Typical Application Circuit Rev. A | Page 14 of 16 VCC 07511-034 MSET ADN2526 DESIGN EXAMPLE This design example covers: • • Headroom calculations for the IBIAS, IMODP, and IMODN pins. Calculation of the typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents. This design example assumes that the resistance of the TOSA is 25 Ω, the forward voltage of the laser at low current is VF = 1 V, IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V. Headroom Calculations To ensure proper device operation, the voltages on the IBIAS, IMODP, and IMODN pins must meet the compliance voltage specifications in Table 1. VLB is the dc voltage drop across L1, L2, L3, and L4. Assuming that VLB = 0 V and IMOD = 60 mA, the minimum voltage at the modulation output pins is equal to VCC − (IMOD × 25)/2 = VCC − 0.75 VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement. The maximum voltage at the modulation pins is equal to VCC + (IMOD × 25)/2 = VCC + 0.75 VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement. Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions. BSET and MSET Pin Voltage Calculation Considering the typical application circuit shown in Figure 34, the voltage at the IBIAS pin can be written as VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2526 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and the typical IBIAS/VBSET ratio of 100 mA/V, the BSET voltage is given by VBSET = 100 mA/V = 40 = 0.4 V 100 The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V, as specified by the minimum IBIAS compliance specification in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using Assuming that the voltage drop across the 25 Ω transmission lines is negligible and that VLA = 0 V, VF = 1 V, and IBIAS = 40 mA VMSET = VIBIAS = 3.3 − 1 − (0.04 × 25) = 1.3 V IMOD K where K is the MSET voltage to IMOD ratio. VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement. The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS IBIAS (mA) (2) For this example, VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V The value of K depends on the actual resistance of the TOSA. It can be read using the plot shown in Figure 29. For a TOSA resistance of 25 Ω, the typical value of K is equal to 120 mA/V. Assuming that IMOD = 60 mA and using the preceding equation, the MSET voltage is given by VMSET = VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement. To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC, due to the ac-coupled configuration, and a swing equal to IMOD × 25 Ω. For proper operation of the ADN2526, the voltage at each modulation output pin should be within the normal operation region shown in Figure 30. IMOD (mA) 120 mA/V = 60 = 0. 5 V 120 The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 29. Rev. A | Page 15 of 16 ADN2526 OUTLINE DIMENSIONS 0.60 MAX 3.00 BSC SQ BOTTOM VIEW 0.45 TOP VIEW 13 12 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.23 0.18 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 16 9 4 8 5 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. 071708-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADN2526ACPZ 1 ADN2526ACPZ-R21 ADN2526ACPZ-R71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ, 7” Tape & Reel, 250-Piece Reel 16-Lead LFCSP_VQ, 7” Tape & Reel, 1,500-Piece Reel Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07511-0-8/09(A) Rev. A | Page 16 of 16 Package Option CP-16-3 CP-16-3 CP-16-3 Branding F0C F0C F0C