Infineon HYS72D32020GU-7-A Unbuffered ddr sdram-module Datasheet

D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS[64/72]D16000GU-[7/8]-A
HYS[64/72]D32020GU-[7/8]-A
Unbuff ered DDR SDRAM- Modul es
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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Due to technical requirements components may contain dangerous substances. For information on the types in
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be endangered.
D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS[64/72]D16000GU-[7/8]-A
HYS[64/72]D32020GU-[7/8]-A
Unbuff ered DDR SDRAM- Modul es
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS[64/72]D16000GU-[7/8]-A, HYS[64/72]D32020GU-[7/8]-A
Revision History:
Rev. 1.03
2004-01
Previous Version:
Rev. 1.02
2003-11
Page
Subjects (major changes since last revision)
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Template: mp_a4_v2.2_2003-10-07.fm
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Table of Contents
Page
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
5
16
16
18
20
Rev. 1.03, 2004-01
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
184-pin Unbuffered 8-Byte Dual-In-Line DDR SDRAM non-parity and ECC-Modules for PC and Server main
memory applications
One rank 16M x 64, 16M x 72 and two rank 32M x 64, 32M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single + 2.5 V (± 0.2 V) power
supply
Built with 128 Mb DDR SDRAMs organised as 16Mb x 8 in 66-Lead TSOPII package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor:
133.35 mm × 31.75 mm × 4.00 mm max.
JEDEC standard reference layout
Gold plated contacts
Table 1
Performance -8/-7
Part Number Speed Code
Speed Grade
max. Clock Frequency
–7
–8
Unit
Component
DDR266A
DDR200
—
Module
PC2100-2033
PC1600-2022
—
143
125
MHz
133
100
MHz
@CL2.5
@CL2
1.2
fCK2.5
fCK2
Description
The HYS64/72D16000GU and HYS64/72D32020GU are industry standard 184-pin 8-byte Dual in-line Memory
Modules (DIMMs) organized as 16M x 64 and 32M × 64 for non-parity and 16M x 72 and 32M x 72 for ECC main
memory applications. The memory array is designed with 128Mbit Double Data Rate Synchronous DRAMs. A
variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration
data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
HYS64D16000GU-7-A
PC2100-20330-A1
one rank 128 MB DIMM
128 MBit (x8)
HYS72D16000GU-7-A
PC2100-20330-A1
one rank 128 MB ECC-DIMM 128 MBit (x8)
HYS64D32020GU-7-A
PC2100-20330-B1
two ranks 256 MB DIMM
HYS72D32020GU-7-A
PC2100-20330-B1
two ranks 256 MB ECC-DIMM 128 MBit (x8)
HYS64D16000GU-8-A
PC1600-20220-A1
one rank 128 MB DIMM
HYS72D16000GU-8-A
PC1600-20220-A1
one rank 128 MB ECC-DIMM 128 MBit (x8)
HYS64D32020GU-8-A
PC1600-20220-B1
two ranks 256 MB DIMM
HYS72D32020GU-8-A
PC1600-20220-B1
two ranks 256 MB ECC-DIMM 128 MBit (x8)
PC2100 (CL=2):
128 MBit (x8)
PC1600 (CL=2):
128 MBit (x8)
128 MBit (x8)
Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available
on request. Example: HYS 72D32020GU-8-A, indicating Rev.A dies are used for the SDRAM components.
The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the
latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card used
for this module.
Data Sheet
7
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A12
I
Address Inputs
BA0, BA1
I
Bank Selects
DQ0 - DQ63
I/O
Data Input/Output
CB0 - CB7
I/O
Check Bits (×72 organization only)
RAS, CAS, WE
I
Command Inputs
CKE0 - CKE1
I
Clock Enable
DQS0 - DQS8
I/O
SDRAM low data strobes
CK0 - CK2,
I
SDRAM clock (positive lines)
CK0 - CK2
I
SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
I
I/O
SDRAM low data mask/
high data strobes
S0, S1
I
Chip Selects for Rank0 and Rank1
VDD
PWR
Power (+2.5 V)
VSS
GND
Ground
VDDQ
PWR
I/O Driver power supply
VDDID
PWR
VDD Indentification flag
VREF
AI
I/O reference supply
VDDSPD
PWR
Serial EEPROM power supply
SCL
I
Serial bus clock
SDA
I/O
Serial bus data line
SA0 - SA2
I
slave address select
NC
NC
Not Connected
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
Table 4
Pin Configuration
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC /
DM8/DQS17
2
DQ0
49
NC / CB2
94
DQ4
141
A10
3
VSS
50
VSS
95
DQ5
142
NC / CB6
4
DQ1
51
NC / CB3
96
VDDQD
143
VDDQD
5
DQS0
52
BA1
97
DM0/DQS9
144
NC / CB7
6
DQ2
98
DQ6
7
VDD
99
DQ7
8
DQ3
53
DQ32
100
VSS
145
VSS
9
NC
54
VDDQ
101
NC
146
DQ36
10
NC
55
DQ33
102
NC
147
DQ37
11
VSS
56
DQS4
103
NC
148
VDD
12
DQ8
57
DQ34
104
VDDQ
149
DM4/DQS13
Key
Key
13
DQ9
58
VSS
105
DQ12
150
DQ38
14
DQS1
59
BA0
106
DQ13
151
DQ39
15
VDDQ
60
DQ35
107
DM1/DQS10
152
VSS
16
CK1
61
DQ40
108
VDD
153
DQ44
17
CK1
62
VDDQ
109
DQ14
154
RAS
18
VSS
63
WE
110
DQ15
155
DQ45
19
DQ10
64
DQ41
111
CKE1
156
VDDQ
20
DQ11
65
CAS
112
VDDQ
157
S0
21
CKE0
66
VSS
113
NC (BA2)
158
S1
22
VDDQ
67
DQS5
114
DQ20
159
DM5/DQS14
23
DQ16
68
DQ42
115
NC / A12
160
VSS
24
DQ17
69
DQ43
116
VSS
161
DQ46
25
DQS2
70
VDD
117
DQ21
162
DQ47
26
VSS
71
NC
118
A11
163
NC
27
A9
72
DQ48
119
DM2/DQS11
164
VDDQ
28
DQ18
73
DQ49
120
VDD
165
DQ52
29
A7
74
VSS
121
DQ22
166
DQ53
30
VDDQ
75
CK2
122
A8
167
NC (A13)
31
DQ19
76
CK2
123
DQ23
168
VDD
32
A5
77
VDDQ
124
VSS
169
DM6/DQS15
33
DQ24
78
DQS6
125
A6
170
DQ54
34
VSS
79
DQ50
126
DQ28
171
DQ55
35
DQ25
80
DQ51
127
DQ29
172
VDDQ
36
DQS3
81
128
VDDQ
173
NC
37
A4
82
VSS
VDDID
129
DM3/DQS12
174
DQ60
38
VDD
83
DQ56
130
A3
175
DQ61
39
DQ26
84
DQ57
131
DQ30
176
VSS
Data Sheet
9
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
Table 4
Pin Configuration (cont’d)
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
40
DQ27
85
VDD
132
VSS
177
DM7/DQS16
41
A2
86
DQS7
133
DQ31
178
DQ62
42
VSS
87
DQ58
134
NC / CB4
179
DQ63
43
A1
88
DQ59
135
NC / CB5
180
VDDQ
44
NC / CB0
89
VSS
136
VDDQ
181
SA0
45
NC / CB1
90
NC
137
CK0
182
SA1
46
VDD
91
SDA
138
CK0
183
SA2
47
NC / DQS8
92
SCL
139
VSS
184
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on ×64 organised non-ECC
modules.
Table 5
Address Format
Organization
Memory
Banks
SDRAMs
# of
SDRAMs
# of
row/bank/
columns
bits
Refresh
Period
Interval
128 MB
16M × 64
1
16M × 8
8
12/2/10
4K
64 ms
15.6 µs
128 MB
16M × 72
1
16M × 8
9
12/2/10
4K
64 ms
15.6 µs
256 MB
32M × 64
2
16M × 8
16
12/2/10
4K
64 ms
15.6 µs
256 MB
32M × 72
2
16M × 8
18
12/2/10
4K
64 ms
15.6 µs
Density
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC modules.
A12 is used for 256 Mbit based modules only.
Data Sheet
10
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
S
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
S
D1
D4
S
DQS
D5
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
S
DQS
D2
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS
D3
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
S
DQS
D7
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
BA0 - BA1
BA0-BA1: SDRAMs D0 - D7
A0 - A13
A0-A13: SDRAMs D0 - D7
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
VDD SPD
CKE0
CKE: SDRAMs D0 - D7
VDD/VDDQ
D0 - D7
WE
WE: SDRAMs D0 - D7
VREF
D0 - D7
VSS
D0 - D7
SPD
VDDID
Data Sheet
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
Figure 1
S
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%
4. VDDID strap connections
(for memory device VDD , V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ .
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms
+5%
Block Diagram: One Rank 16M × 64 DDR SDRAM DIMM Module HYS64D16000GU using ×8
organized SDRAMs
11
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
VDD SPD
VDD/VDDQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
VSS
D0 - D15
A0 - An
CKE1
RAS
BA0-BA1: SDRAMs D0 - D15
A0-An: SDRAMs D0 - D15
CKE: SDRAMs D8 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
Data Sheet
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
S
DQS
D12
DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D13
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
D7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
Serial PD
SCL
Strap: see Note 4
CAS
Figure 2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0 - D15
D0 - D15
BA0 - BA1
S
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VREF
VDDID
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
SDA
WP
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
Clock
SDRAMs
Input
4 SDRAMs
6 SDRAMs
6 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Block Diagram: Two Rank 32M × 64 DDR SDRAM DIMM Modules HYS64D32020GU using ×8
Organized SDRAMs
12
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DM4
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
S
DQS
D5
S
DQS
D6
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RAS
D4
DQS6
DM6
DQS2
DM2
A0 - A13
DQS
DQS5
DM5
DQS1
DM1
BA0 - BA1
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
SCL
D8
A0-A13: SDRAMs D0 - D8
CAS
CAS: SDRAMs D0 - D8
CKE0
CKE: SDRAMs D0 - D8
WE
WE: SDRAMs D0 - D8
D7
SDA
WP
A0
A1
A2
SA0
SA1
SA2
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
SPD
maintained as shown.
D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
D0 - D8
(for memory device VDD, V DDQ ):
D0 - D8
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ.
Strap: see Note 4
BA0-BA1: SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
DQS
* Clock Wiring
Clock
SDRAMs
Input
Serial PD
DQS
S
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm
+5%
Figure 3
Data Sheet
Block Diagram: One Rank 16M × 72 DDR SDRAM DIMM Module HYS72D16000GU using ×8
organized SDRAMs
13
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
S
DQS
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS
S
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
A0 - A13
CKE1
RAS
CAS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D8
DQS
S
D17
DQS
D7
D0 - D17
D0 - D17
VSS
D0 - D17
VDDID
Strap: see Note 4
A0-A13: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
S
VREF
BA0-BA1: SDRAMs D0 - D17
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VDD/VDDQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
S
DQS
D13
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
DQS7
DM7/DQS16
VDD SPD
DQS8
DM8/DQS17
BA0 - BA1
S
DQS
S
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Serial PD
SCL
CKE0
CKE: SDRAMs D0 - D8
WP
A0
A1
A2
WE
WE: SDRAMs D0 - D17
SA0
SA1
SA2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D16
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
SDA
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Figure 4
Data Sheet
Block Diagram: Two Rank 32M × 72 DDR SDRAM DIMM Modules HYS72D32020GU using ×8
Organized SDRAMs
14
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
6 DRAM Loads
4 DRAM Loads
DR AM 1
DR AM 1
DRAM2
CK
DRAM2
R = 120
R =120
DRAM3
DIMM
Connector
Cap.
DIMM
Connector
CK
DR AM4
Cap.
DR AM5
DR AM5
DR AM6
DRAM6
DR AM 1
2 DRAM Loads
DR AM 1
3 DRAM Loads
Cap.
Cap.
R =120
DIMM
Connector
R =120
DIMM
Connector
DR AM3
Cap.
Cap.
Cap.
DR AM5
DR AM5
Cap.
Cap.
Figure 5
Data Sheet
Clock Net Wiring
15
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
max.
Unit Note/ Test
Condition
–0.5
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Data Sheet
16
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 7
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
VDD
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
Input Reference Voltage
VREF
I/O Termination Voltage
VTT
Device Supply Voltage
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.3
2.5
2.7
V
2)
2.3
2.5
3.6
V
—
0
V
—
0
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
3)
VREF – 0.04
VREF + 0.04 V
4)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
7)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
V
7)5)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
6)
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 7)8)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 7)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 7)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 7)
(System)
7)
7)
1) 0 °C ≤ TA ≤ 70 °C
2) Under all conditions, VDDQ must be less than or equal to VDD.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until VREF stabilizes.
8) Values are shown per component
Data Sheet
17
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3.2
Current Specification and Conditions
Table 8
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
18
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
HYS72D32020GU-7-A
HYS72D32020GU-8-A
HYS64D32020GU-7-A
HYS64D32020GU-8-A
HYS72D16000GU-8-A
HYS72D16000GU-8-A
128MB
128MB
256MB
256MB
×64
×72
×64
×72
1 Rank
1 Rank
2 Ranks
2 Ranks
-8
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS64D16000GU-7-A
IDD Specification and Conditions -8/-7
HYS64D16000GU-8-A
Part Number & Organization
Table 9
-7
-8
max
-7
-8
max
-7
-8
max
Unit
Note 1)2)
-7
max
680
720
765
810
960
1080
1080
1215
mA
3)
800
880
900
990
1080
1240
1215
1395
mA
3)4)
36
40
40.5
45
72
80
81
90
mA
5)
280
360
315
405
560
720
630
810
mA
5)
280
360
315
405
560
720
630
810
mA
5)
120
120
135
135
240
240
270
270
mA
5)
280
360
315
405
560
720
630
810
mA
5)
720
880
810
990
1000
1240
1125
1395
mA
3)4)
760
880
855
990
1040
1240
1170
1395
mA
3)
1440
1520
1620
1710
1720
1880
1935
2115
mA
3)
20
20
22.5
22.5
40
40
45
45
mA
5)
2160
2240
2430
2520
2440
2600
2745
2925
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
19
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3.3
AC Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
–7
DDR200
DDR266A
Unit Note/
Test Condition 1)
Min.
Max.
Min.
Max.
tAC
tDQSCK
tCH
tCL
tHP
tCK2.5
tCK2
tCK1.5
tDH
tDS
tIPW
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
ns
2)3)4)5)
DQ and DM input pulse width (each
input)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
2)3)4)5)
8
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
ns
CL = 2.0 2)3)4)5)
10
12
—
—
ns
CL = 1.5 2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
2.5
—
2.2
—
ns
2)3)4)5)6)
tDIPW
2.0
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Data-out low-impedance time from
CK/CK
tLZ
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.6
—
+0.5
ns
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
1.0
—
0.75
ns
2)3)4)5)
tHP – —
tQHS
tHP –
tQHS
—
ns
2)3)4)5)
tDQSL,H
0.35
—
0.35
—
tCK
2)3)4)5)
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command cycle time
tMRD
tWPRES
tWPST
tWPRE
tIS
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
1.1
—
0.9
—
ns
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ/DQS output hold time
DQS input low (high) pulse width (write
cycle)
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
2)3)4)5)
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Data Sheet
20
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Address and control input hold time
Symbol
tIH
–8
–7
DDR200
DDR266A
Min.
Max.
Min.
Max.
1.1
—
0.9
—
Unit Note/
Test Condition 1)
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
tRPRE
tRPRE1.5
Read preamble setup time
tRPRES
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Read preamble
CL > 1.5 2)3)4)5)
NA
tCK
tCK
—
NA
ns
2)3)4)5)12)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)
50
120E+3
45
120E+3 ns
2)3)4)5)
70
—
65
—
ns
2)3)4)5)
0.9
1.1
0.9
0.9
1.1
1.5
1.1
CL = 1.5 2)3)4)5)11)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
—
75
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)13)
tWTR
tWTR1.5
tXSNR
tXSRD
tREFI
1
—
1
—
CL > 1.5 2)3)4)5)
2
—
—
—
tCK
tCK
80
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)14)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
(twr/tCK) + (trp/tCK)
CL = 1.5 2)3)4)5)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Data Sheet
21
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
22
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
4
SPD Contents
Table 11
SPD Codes for PC1600 Modules -8
Byte#
Description
0
Number of SPD Bytes
128
1
Total Bytes in Serial PD
2
128MB
x64
1rank
–8
128MB
x72
1rank
–8
128MB
x64
2ranks
–8
128MB
x64
2ranks
–8
hex.
hex.
hex.
hex.
80
80
80
80
256
08
08
08
08
Memory Type
DDR-SDRAM
07
07
07
07
3
Number of Row Addresses
12
0C
0C
0C
0C
4
Number of Column
Addresses
10
0A
0A
0A
0A
5
Number of DIMM Banks
1/2
01
01
02
02
6
Module Data Width
×64/×72
40
48
40
48
7
Module Data Width (cont’d)
0
00
00
00
00
8
Module Interface Levels
SSTL_2.5
04
04
04
04
9
SDRAM Cycle Time at
CL = 2.5
8 ns
80
80
80
80
10
Access Time from Clock at
CL = 2.5
0.8 ns
80
80
80
80
11
DIMM config
non-ECC/ECC
00
02
00
02
12
Refresh Rate/Type
Self-Refresh 15.6 ms
80
80
80
80
13
SDRAM Width, Primary
×8
08
08
08
08
14
Error Checking SDRAM Data na/×8
Witdh
00
08
00
08
15
Minimum Clock Delay for
Back-to-Back Random
Column Address
tCCD = 1 CLK
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
17
Number of SDRAM Banks
4
04
04
04
04
18
Supported CAS Latencies
CAS latency = 2 & 2.5
0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
21
SDRAM DIMM Module
Attributes
unbuffered
20
20
20
20
22
SDRAM Device Attributes:
General
–
C0
C0
C0
C0
23
Min. Clock Cycle Time at
CAS Latency = 2
10 ns
A0
A0
A0
A0
24
Access Time from Clock for
CL = 2
0.8 ns
80
80
80
80
25
Minimum Clock Cycle Time
for CL = 1.5
not supported
00
00
00
00
Data Sheet
23
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
Table 11
SPD Codes for PC1600 Modules -8 (cont’d)
Byte#
Description
128MB
x64
1rank
–8
128MB
x72
1rank
–8
128MB
x64
2ranks
–8
128MB
x64
2ranks
–8
hex.
hex.
hex.
hex.
26
Access Time from Clock at
CL = 1.5
not supported
00
00
00
00
27
Minimum Row Precharge
Time
20 ns
50
50
50
50
28
Minimum Row Act. to Row
Act. Delay tRRD
15 ns
3C
3C
3C
3C
29
Minimum RAS to CAS Delay 20 ns
50
50
50
50
50 ns
32
32
32
32
tRCD
30
Minimum RAS Pulse Width
tRAS
31
Module Bank Density (per
Bank)
128 MByte
20
20
20
20
32
Addr. and Command Setup
Time
1.1 ns
B0
B0
B0
B0
33
Addr. and Command Hold 1.1 ns
Time
B0
B0
B0
B0
34
Data Input Setup Time
0.6 ns
60
60
60
60
35
Data Input Hold Time
0.6 ns
60
60
60
60
36 to 40
Superset Information
–
46
46
46
46
41
Minimum Core Cycle Time 70 ns
tRC
42
Min. Auto Refresh
Cycle Time tFRC
Cmd 80 ns
50
50
50
50
43
Maximum Clock Cycle Time 12 ns
30
30
30
30
tCK
44
Max. DQS-DQ Skew tDQSQ 0.6 ns
3C
3C
3C
3C
45
X-Factor tQHS
1.0 ns
A0
A0
A0
A0
46 to 61
Superset Information
–
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
63
Checksum for Bytes 0 - 62
–
84
96
85
97
64
Manufactures
Codes
65 to 71
Manufactures
–
Infineon
Infineon
Infineon
Infineon
72
Module Assembly Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
91 to 92
Module Revision Code
–
–
–
–
–
93 to 94
Module Manufacturing Date
–
–
–
–
–
95 to 98
Module Serial Number
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
–
–
–
–
JEDEC
128 to 255 open for Customer use
Data Sheet
ID –
24
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
Table 12
SPD Codes for PC2100 Modules -7
Byte#
Description
128MB
x64
1rank
–7
128MB
x72
1rank
–7
128MB
x64
2ranks
–7
128MB
x64
2ranks
–7
hex.
hex.
hex.
hex.
0
Number of SPD Bytes
128
80
80
80
80
1
Total Bytes in Serial PD
256
08
08
08
08
2
Memory Type
DDR-SDRAM
07
07
07
07
3
Number of Row Addresses
12
0C
0C
0C
0C
4
Number of Column
Addresses
10
0A
0A
0A
0A
5
Number of DIMM Banks
1/2
01
01
02
02
6
Module Data Width
×64/×72
40
48
40
48
7
Module Data Width (cont’d)
0
00
00
00
00
8
Module Interface Levels
SSTL_2.5
04
04
04
04
9
SDRAM Cycle Time at
CL = 2.5
7 ns
70
70
70
70
10
Access Time from Clock at
CL = 2.5
0.75 ns
75
75
75
75
11
DIMM config
non-ECC/ECC
00
02
00
02
12
Refresh Rate/Type
Self-Refresh 15.6 ms
80
80
80
80
13
SDRAM Width, Primary
×8
08
08
08
08
14
Error Checking SDRAM Data na/×8
Witdh
00
08
00
08
15
Minimum Clock Delay for
Back-to-Back Random
Column Address
tCCD = 1 CLK
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
17
Number of SDRAM Banks
4
04
04
04
04
18
Supported CAS Latencies
CAS latency = 2 & 2.5 0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
21
SDRAM DIMM Module
Attributes
unbuffered
20
20
20
20
22
SDRAM Device Attributes:
General
–
C0
C0
C0
C0
23
Min. Clock Cycle Time at
CAS Latency = 2
7.5 ns
75
75
75
75
24
Access Time from Clock for
CL = 2
0.75 ns
75
75
75
75
25
Minimum Clock Cycle Time
for CL = 1.5
not supported
00
00
00
00
26
Access Time from Clock at
CL = 1.5
not supported
00
00
00
00
Data Sheet
25
01
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
Table 12
SPD Codes for PC2100 Modules -7 (cont’d)
Byte#
Description
128MB
x64
1rank
–7
128MB
x72
1rank
–7
128MB
x64
2ranks
–7
128MB
x64
2ranks
–7
hex.
hex.
hex.
hex.
27
Minimum Row Precharge
Time
20 ns
50
50
50
50
28
Minimum Row Act. to Row
Act. Delay tRRD
15 ns
3C
3C
3C
3C
29
Minimum RAS to CAS Delay 20 ns
50
50
50
50
45 ns
2D
2D
2D
2D
tRCD
30
Minimum RAS Pulse Width
tRAS
31
Module Bank Density (per
Bank)
128 MByte
20
20
20
20
32
Addr. and Command Setup
Time
0.9 ns
90
90
90
90
33
Addr. and Command Hold 0.9 ns
Time
90
90
90
90
34
Data Input Setup Time
0.5 ns
50
50
50
50
35
Data Input Hold Time
0.5 ns
50
50
50
50
36 to 40
Superset Information
–
41
41
41
41
41
Minimum Core Cycle Time 65 ns
tRC
42
Min. Auto Refresh
Cycle Time tFRC
Cmd 75 ns
4B
4B
4B
4B
43
Maximum Clock Cycle Time 12 ns
30
30
30
30
tCK
44
Max. DQS-DQ Skew tDQSQ 0.5 ns
32
32
32
32
45
X-Factor tQHS
0.75 ns
75
75
75
75
46 to 61
Superset Information
–
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
63
Checksum for Bytes 0 - 62
–
8F
8F
8F
8F
64
Manufactures
Codes
ID –
C1
C1
C1
C1
65 to 71
Manufactures
–
Infineon
Infineon
Infineon
Infineon
72
Module Assembly Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
91 to 92
Module Revision Code
–
–
–
–
–
93 to 94
Module Manufacturing Date
–
–
–
–
–
95 to 98
Module Serial Number
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
–
–
–
–
JEDEC
128 to 255 open for Customer use
Data Sheet
26
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
1)
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 6
Data Sheet
DDR-SDRAM DIMM Module Package
27
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 7
Data Sheet
Package Outlines -Raw Card A1 (One Rank Modules)
28
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Package Outlines
DDR-SDRAM DIMM Module Package
two banks modules
133.35 +- 0.15
4.0 max.
4.0
31.75
+
- 0.13
Front View
2.3 typ.
*)
52
pin 1
92
53
64.77
49.53
1.27 +- 0.1
2.3 typ.
6.62
Backside View
144
145
184
2.5D
10.0
17.80
pin 93
*)
3
3
*) on ECC modules only
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 +- 0.15
Detail of Contacts A
3.8 typ.
0.9R
1 +- 0.05
1.27
1.8
2.175
L-DIM-1849d
Figure 8
Data Sheet
Package Outlines - Raw Card B1 (Two Rank Modules)
29
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
http://www.infineon.com
Published by Infineon Technologies AG