LTC4309 Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery DESCRIPTION FEATURES n n n n n n n n n n n n n n n The LTC®4309 hot swappable 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. The LTC4309 provides bidirectional buffering, keeping the backplane and card capacitances isolated. Low offset and high VOL tolerance allows cascading of multiple devices on the clock and data busses. If SDAOUT or SCLOUT are low for 30ms, FAULT will pull low indicating a stuck bus low condition. If DISCEN is tied high, the LTC4309 will automatically break the bus connection and generate up to 16 clock pulses and a stop bit in an attempt to free the bus. A connection will resume if the stuck bus is cleared. If DISCEN is connected to GND, the busses will remain connected with no clock or stop bit generation. ACC input enables rise-time accelerators for high capacitively loaded busses. Bidirectional Buffer Increases Fanout 60mV Buffer Offset Independent of Load Optional Disconnect when Bus is Stuck Low Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Level Shift 2.5V, 3.3V and 5V Busses Compatible with Non-Compliant VOL I2C Devices ±6kV Human Body Model ESD Ruggedness Isolates Input SDA and SCL Lines from Output Compatible with I2C™, I2C Fast-Mode and SMBus READY Open Drain Output FAULT Open Drain Output 1V Precharge on All SDA and SCL Lines Optional Rise Time Accelerators High Impedance SDA, SCL Pins for VCC = 0 Available in Small 12-Pin DFN (4mm x 3mm) and 16-Lead SSOP Packages During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven high, the ENABLE input allows the LTC4309 to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open drain output which indicates that the backplane and card sides are connected. APPLICATIONS n n n n n Live Board Insertion Servers Capacitance Buffer/Bus Extender RAID Systems ATCA L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6356140, 6650174, 7032051. TYPICAL APPLICATION 3.3V Rising Edge from Asserted Low 5V 0.01μF 10k EN 1000 VCC2 VCC ACC ENABLE 2.7k 100k SCLIN SDA1 SDAIN SDAOUT 3.3V 10k FAULT FAULT SDAOUT 5V FAULT 10k SCL2 CARD CONNECTOR SDAOUT 400 SDAIN 200 0 READY GND BACKPLANE CONNECTOR LOW OFFSET SDA2 5V FAULT GND 600 10k DISCEN 10k READY 10k SCLOUT SDAIN 3.3V 10k DISCEN LTC4309 SCLIN SCLOUT 800 ACC ENABLE 2.7k LTC4309 SCL1 0.01μF VCC VCC2 200mV/DIV 10k 0 100 200 300 400 100ns/DIV 500 600 4309 G01 4309 TA01 4309fa 1 LTC4309 ABSOLUTE MAXIMUM RATINGS (Note 1, 6) VCC, VCC2 to GND ............................................–0.3 to 6V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE, FAULT, ACC, DISCEN .......................–0.3 to 6V Maximum Sink Current (SDA, SCL, FAULT, READY) ISINK ......................................................................50mA Operating Temperature LTC4309C ................................................ 0°C to 70°C LTC4309I.............................................. –40°C to 85°C Storage Temperature Range (DE)........... –65°C to 125°C Storage Temperature Range (GN) .......... –65°C to 150°C Lead Temperature (Soldering, 10 sec) GN Package ...................................................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW ENABLE 1 12 VCC DISCEN 2 11 VCC2 SCLOUT 3 SCLIN 4 ACC GND 13 10 SDAOUT 9 SDAIN 5 8 FAULT 6 7 READY DE12 PACKAGE 12-LEAD (4mm × 3mm) PLASTIC DFN ENABLE 1 16 VCC NC 2 15 NC DISCEN 3 14 VCC2 SCLOUT 4 13 SDAOUT SCLIN 5 12 SDAIN ACC 6 11 FAULT NC 7 10 NC GND 8 9 READY GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB CONNECTION TO GND IS OPTIONAL TJMAX = 150°C, θJA = 110°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4309CDE#PBF LTC4309CDE#TRPBF 4309 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C LTC4309IDE#PBF LTC4309IDE#TRPBF 4309 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C LTC4309CGN#PBF LTC4309CGN#TRPBF 4309 16-Lead Plastic SSOP 0°C to 70°C LTC4309IGN#PBF LTC4309IGN#TRPBF 4309I 16-Lead Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4309fa 2 LTC4309 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER VCC Positive Supply Voltage CONDITIONS MIN TYP MAX UNITS VCC2 Input Side Accelerator Supply Voltage ICC VCC Input Supply Current Enabled VCC = VCC2 = 5.5V, VSDAIN = VSCLIN = 0V (Note 2) l ISD VCC Input Supply Current Disabled VCC = VCC2 = 5.5V, SDA = SCL = 5.5V, ENABLE = OV l 900 1400 μA ICC2 VCC2 Input Supply Current Enabled VCC = VCC2 = 5.5V, VSDAIN = VSCLIN = 0V (Note 2) l 190 250 μA ISD2 VCC2 Input Supply Current Disabled VCC = VCC2 = 5.5V, SDA = SCL = 5.5V, ENABLE = OV l 140 180 μA l 2.3 l 1.8 5.5 7 V 5.5 V 11 mA Propagation Delay and Rise Time Accelerators tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, (Note 3, 4), (Figure 1) 85 ns tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, (Note 3, 4), (Figure 1) 10 tRISE SDA/SCL Rise Time 30 300 ns tFALL SDA/SCL Fall Time 30 300 ns IPULLUPAC Transient Boosted Pull-up Current CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 5V VCC2 = 5V, (Note 3, 5), (Figure 1) CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 5V (Note 3, 5), (Figure 1) Positive Transition > 0.8V/μS on SDA, SCL, VCC = 3.3V (Note 7) ns 5 8 mA 0.8 1.0 1.2 V Start-Up Circuitry VPRE Precharge Voltage tIDLE Bus Idle Time VTHR_EN ENABLE Threshold Voltage VTHR_EN(HYST) ENABLE Threshold Voltage Hysteresis SDA, SCL Open ENABLE Rising Edge l l 55 95 175 μs l 0.8 1.4 2 V (Note 3) 100 mV VTHR_CTRL ACC, DISCEN Threshold Voltage ICTRL ENABLE, ACC, DISCEN Input Currents ENABLE, ACC, DISCEN from 0 to VCC tPLH_EN ENABLE Delay Off-On (Figure 1) 95 μs tPHL_EN ENABLE Delay On-Off (Note 3), (Figure 1) 10 ns tPLH_READY READY Delay On-Off (Note 3), (Figure 1) 10 ns tPHL_READY READY Delay Off-On (Note 3), (Figure 1) 10 ns VOL_READY READY Output Low Voltage IREADY = 3mA, VCC = 2.3V l IOFF_READY READY Off Leakage Current VCC = READY = 5.5V l 0.5 l 0.7 1 V 0.1 ±5 μA 0.1 0.4 V ±5 μA Timing Characteristics fI2C, MAX I2C Maximum Operating Frequency (Note 3) tBUF Bus Free Time Between Stop and Start Condition (Note 3) 1.3 μs tHD, STA (Note 3) 100 ns tSU, STA Hold Time After (Repeated) Start Condition Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU, STO Stop Condition Set-Up Time (Note 3) 0 ns tHD, DATI Data Hold Time Input (Note 3) 0 ns tSU, DAT Data Set-Up Time (Note 3) 100 ns 400 600 kHz Input-Output Connection VOS Input-Output Offset Voltage 2.7k to VCC2 on SDA, SCL, Driven SDA, SCL = 0.2V VTHR SDA, SCL Logic Input Threshold Voltage VCC ≥ 2.9V VCC < 2.9V l 20 60 100 mV 1.4 1.1 1.65 1.35 1.9 1.6 V V 4309fa 3 LTC4309 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VTHR(HYST) (Note 3) ILEAK SDA, SCL Logic Input Threshold Voltage Hysteresis Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT Input Leakage Current SDA, SCL, ACC, DISCEN Pins l VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC = VCC2 = 2.7V 2.7k to VCC on SDA, SCL, Driven SDA/SCL = 0.1V, VCC = VCC2 = 3.3V l 0 l 120 CIN VILMAX MIN TYP MAX UNITS 50 (Note 3) 170 l Buffer Input Logic Low Voltage mV 10 pF ±5 μA 0.4 V 205 mV 1.2 V 35 ms 0.4 V ±5 μA Bus Stuck Low Timeout tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = OV l VOL_FAULT FAULT Output Low Voltage IFAULT = 3mA l IOFF_FAULT FAULT Off Leakage Current 25 l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Test performed with connection circuity active. Note 3: Determined by design, not subject to test. Note 4: For larger equivalent bus capacitance, the skew increases, and 30 0.1 setup and hold times must be adjusted accordingly. Please see the Operation Section of the datasheet. Note 5: Measure points are 0.3 • VCC and 0.7 • VCC. Note 6: All currents into pins are positive, all voltages are referenced to GND, unless otherwise specified. Note 7: IPULLUPAC varies with temperature and VCC voltage as shown in the Typical Performance Characteristics section. TIMING DIAGRAMS ENABLE and READY Timing tPHL_READY tPHL_EN tPLH_READY tPLH_EN ENABLE CONNECT READY 4309 TD01 SDA/SCL Propagation Delays, Rise and Fall Times tRISE tPLH tPHL tRISE tFALL tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4309 TD02 Figure 1. Timing Diagrams 4309fa 4 LTC4309 TYPICAL PERFORMANCE CHARACTERISTICS ICC Enabled Current vs Temperature ICC Disabled Current vs Temperature 8 ICC2 Enabled Current vs Temperature 220 20 7 6.5 VCC = 3.3V 6 VCC = 2.3V –25 VCC = 5.5V 12 VCC = 3.3V 8 4 5.5 5 –50 200 16 VCC = 5.5V SUPPLY CURRENT (MA) 7.5 IPULLUPAC (mA) ICC ENABLED CURRENT (mA) TA = 25°C, VCC = 3.3V, VCC2 = 3.3V unless otherwise noted. 0 50 25 TEMPERATURE (oC) 75 –25 25 50 0 TEMPERATURE (°C) 75 4309 G02 130 PROPAGATION DELAY (ns) 110 VCC = 2.3V 120 VCC = 5.5V 110 100 90 VCC = 2.3V 80 Boost Pull-Up Current vs Temperature 0 25 50 TEMPERATURE (oC) 75 100 CIN = 50pF COUT = 1nF 25 RPULLUPIN = RPULLUPOUT = 2.7kΩ 20 VCC = 5.5V 15 10 VCC = 3.3V 5 VCC = 3.3V 60 –50 –25 VCC = 2.3V 50 0 25 TEMPERATURE (°C) 75 100 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4309 G07 4309 G06 4309 G05 Offset Voltage vs Pull-Up Resistance Input-Output High to Low Propagation Delay vs Output Capacitance 160 70 150 66 140 VCC = 5.5V OFFSET VOLTAGE (mV) –25 100 75 25 50 0 TEMPERATURE (oC) 30 CIN = COUT = 50pF RPULLUPIN = RPULLUPOUT = 2.7kΩ 70 PROPAGATION DELAY (ns) SUPPLY CURRENT (MA) 140 VCC = 3.3V –25 4309 G04 BOOST PULL-UP CURRENT (mA) VCC = 5.5V 120 VCC = 2.3V 100 –50 100 140 160 90 –50 140 Input-Output High to Low Propagation Delay vs Temperature 130 VCC = 3.3V 160 4309 G03 ICC2 Disabled Current vs Temperature 100 180 120 0 –50 100 VCC = 5.5V 130 120 110 VCC = 2.3V 100 90 VCC = 3.3V 80 70 0 CIN = 50pF RPULLUPIN = 2.7k7 RPULLUPOUT = 2.7k7 200 400 600 800 OUTPUT CAPACITANCE (pF) 1000 4309 G08 62 58 54 50 VOL = 0.1V CIN = COUT = 50pF RPULLUPIN = 2.7kΩ 0 4 6 8 2 PULL-UP RESISTANCE (kΩ) 10 4309 G09 4309fa 5 LTC4309 PIN FUNCTIONS (DE12/GN16) ENABLE (Pin 1/Pin1): Connection Enable Input. This 1.4V digital threshold input pin enables or disables the LTC4309. For normal operation pull or connect ENABLE high. Driving ENABLE below the 0.8V threshold isolates SDAIN from SDAOUT, SCLIN from SCLOUT, asserts READY low, and prohibits automatic clock and stop bit generation during a fault condition. A rising edge on ENABLE after a fault has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT. Connect to VCC if unused. DISCEN (Pin 2/Pin 3 ): Bus Stuck Low Disconnect Enable Input. This pin, when high, allows the stuck low bus timeout circuitry to disconnect the bus in a fault condition. When connected to GND, this pin disables the circuitry that disconnects the bus under a fault condition; however, the FAULT pin will still go low. SCLOUT (Pin 3/Pin 4): Serial Clock Output. Connect this pin to a SCL bus segment where bus stuck low recovery is desired. If the output rise time accelerators are enabled, a pull-up resistor should be connected between this pin and a bus supply greater than or equal to VCC. Bus supplies can be lower than VCC if the output rise time accelerators are disabled. See Application Information section for detailed bus pull-up supply options. SCLIN (Pin 4/Pin 5): Serial Clock Input. Connect this pin to a SCL bus segment where isolation from bus stuck low issues is desired. If the input rise time accelerator is enabled, a pull-up resistor should be connected between this pin and a bus supply greater than or equal to VCC2. Bus supplies can be lower than VCC2 if the input rise time accelerators are disabled. See Application Information section for detailed bus pull-up supply options. ACC (Pin 5/Pin 6): Rise Time Accelerator Control Input. This nominal 0.7V threshold input pin enables and disables all rise time accelerators on the SDA and SCL pins. Connect ACC to GND to enable all four rise time accelerators or connect ACC to VCC to disable all four rise time accelerators. Connect ACC to VCC2 to GND to enable the accelerators on SDAOUT and SCLOUT only. GND (Pin 6/Pin 8): Device Ground. Connect this pin to a ground plane for best results. READY (Pin 7/Pin 9): Connection Ready Status Output. This open-drain N-channel MOSFET pin pulls low when ENABLE is low, when the start-up and connection sequence described in the Operation section has not been completed, or when the LTC4309 disconnects the input and output pins due to a bus stuck low condition. READY goes high when ENABLE is high and connection is made between the input and output pins. Connect a pull-up resistor, typically 10k, from this pin to the bus pull-up supply. This pin can be left open if unused. FAULT (Pin 8/Pin 11): Bus Stuck Low Timeout Output. This open drain N-channel MOSFET output pulls low after 30ms when there is a bus stuck low condition on the output pins of the LTC4309. In normal operation FAULT is high. Connect a pull-up resistor, typically 10k, from this pin to the bus pull-up supply. This pin can be left open if unused. SDAIN (Pin 9/Pin 12): Serial Clock Input. Connect this pin to a SDA bus segment where isolation from bus stuck low issues is desired. If the input accelerator is enabled, a pull-up resistor should be connected between this pin and a bus supply greater than or equal to VCC2. Bus supplies can be lower than VCC2 if the input rise time accelerators are disabled. See Application Information section for detailed bus pull-up supply options. SDAOUT (Pin 10/Pin 13): Serial Clock Output. Connect this pin to a SCL bus segment where bus stuck low recovery is desired. If the output rise time accelerators are enabled, a pull-up resistor should be connected between this pin and a bus supply greater than or equal to VCC. Bus supplies can be lower than VCC if the output rise time accelerators are disabled. See Application Information section for detailed bus pull-up supply options. VCC2 (Pin 11/Pin 14): Supply Voltage Input for SDAIN and SCLIN Rise Time Accelerator Circuitry. VCC2 supplies the rise time accelerator circuitry on the input side. Bypass this pin to GND with a capacitor of at least 0.01μF and place close to VCC2 for best results. If VCC2 is connected to GND, the input side rise time accelerator circuitry is disabled, regardless of ACC. 4309fa 6 LTC4309 PIN FUNCTIONS (DE12/GN16) VCC (Pin 12/Pin 16): Supply Voltage Input. Bypass this pin to GND with a capacitor of at least 0.01μF and place close to VCC for best results. EXPOSED PAD (Pin 13 DE12 Package Only): Exposed Pad may be left open or connected to device ground. BLOCK DIAGRAM VCC2 VCC VCC2 8mA VCC 8mA CONNECT IBOOSTSDA IBOOSTSDA SDAIN SDAOUT 100k SLEW RATE DETECTOR SLEW RATE DETECTOR 100k PRECHARGE VCC2 VCC PC CONNECT 8mA 100k IBOOSTSCL PC CONNECT 8mA 100k CONNECT IBOOSTSCL SCLIN SCLOUT SLEW RATE DETECTOR SLEW RATE DETECTOR ACC 30ms TIMER + – 1.65V/1.6V 1.35V/1.3V + – 1.65V/1.6V 1.35V/1.3V FAULT DISCEN ENABLE 4309 BD 1.65V/1.6V 1.35V/1.3V + – 1.65V/1.6V 1.35V/1.3V + – 1.4V/1.3V + – LOGIC IBOOSTSCL IBOOSTSDA CONNECT READY PC CONNECT CONNECT GND UVLO 95μs DELAY 4309fa 7 LTC4309 OPERATION Start-Up When the LTC4309 first receives power on its VCC pin, either during power up or live insertion, it starts in an under voltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2V. This ensures the LTC4309 does not try to function until enough supply voltage is present. During this time, the 1V precharge circuitry is actively forcing 1V through 100k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of contact, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4309 exits from UVLO, it monitors both the input and output pins for either a stop bit or a bus idle condition to indicate the completion of data transactions. When both sides are idle or one side has a stop bit while the other is idle, the connection circuitry is activated, joining the SDA and SCL busses on the input side with those on the output side. Rise Time Accelerators Once connection has been established if ACC is connected to ground and VCC2 is powered from a supply voltage greater than or equal to 1.8V, the rise time accelerator circuits on all four SDA and SCL pins are enabled. During positive bus transitions of at least 0.8V/μs, the rise time accelerators provide strong, slew-limited pull-up currents to force the bus voltage to rise at a rate of 100V/μs. Enabling the rise time accelerators allows users to choose larger bus pullup resistors, reducing power consumption and improving logic low noise margins, or design with bus capacitances beyond those specified in the I2C specifications. To ensure the rise time accelerators are properly activated when the rise time accelerators are enabled, users should choose bus pull-up resistors that guarantee the bus will rise on its own at a rate of at least 0.8V/μs. See the Application Information section for determining the correct pull-up resistor size. All four rise time accelerators can be disabled by connecting ACC to VCC. To activate the rise time accelerators on only SDAOUT and SCLOUT, connect both ACC and VCC2 to ground. The rise time accelerators are also internally disabled until the sequence of events described in the start-up section have been completed, as well as during automatic clocking and stop bit generation for a bus stuck low recovery event. Connection Circuitry Once the connection circuitry is activated, the functionality of the input and output bus of the respective SDA or SCL pins are identical. A low forced on either output or input pin at any time results in both pin voltages forced low. The LTC4309 is tolerant of I2C bus DC logic low voltages up to the VIL specification of 0.3 • VCC. When the LTC4309 senses a rising edge on the bus, with a slew rate greater than 0.8V/μs, the internal pull-down device for the respective bus is deactivated at bus voltages as low as 0.48V. This methodology maximizes the effectiveness of the rise time accelerator circuitry and maintains compatibility with other devices in the LTC4300 bus buffer family. Care must be taken to ensure devices participating in clock stretching or arbitration are capable of forcing logic low voltages below 0.48V at the LTC4309’s SDA and SCL pins. A high occurs when all devices on the input and output pins release high. These important features ensures the I2C specification protocols such as clock stretching, clock synchronization, arbitration, and acknowledge function seamlessly in all cases as specified, regardless of how the devices in the system are connected to the LTC4309. Another key feature provided by the connection circuitry is input and output bus capacitance isolation through bidirectional buffering. Because of this isolation, the waveforms on the input busses look slightly different than the corresponding output bus waveforms, as described below. Input to Output Offset Voltage When a logic low voltage is driven on any of the LTC4309’s data or clock pins, the LTC4309 regulates the voltage on the other side of the device to a slightly higher voltage, 4309fa 8 LTC4309 OPERATION OUTPUT SIDE 50pF 1V/DIV INPUT SIDE 150pF 1V/DIV 200ns/DIV INPUT SIDE 150pF 1V/DIV 4307 F01 Figure 2. Input-Output Rising Edge Waveforms typically 60mV. This offset is nearly independent of pull-up current. (See Typical Performance curves.) Propagation Delays During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 2 for VCC and VCC2 = 5.5V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective propagation delay is negative. There is a finite propagation delay through the connection circuitry for falling waveforms. Figure 3 shows the falling edge waveforms for the same pull-up resistors and equivalent capacitance conditions as used in Figure 2. An external N-channel MOSFET device pulls down the voltage on the side with 150pF capacitance; LTC4309 pulls down the voltage on the opposite side, with a delay of 85ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows Propagation Delay as a function of temperature and voltage for 2.7k pull-up resistors and 50pF equivalent capacitance on both sides of the part. Also, the Propagation Delay as a function of Output Capacitance curve shows that larger output capacitances translate to longer delays. Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. OUTPUT SIDE 50pF 1V/DIV 200ns/DIV 4307 F02 Figure 3. Input-Output Falling Edge Waveforms Bus Stuck Low Timeout When SDAOUT or SCLOUT is low, an internal timer is started. The timer is only reset by the respective pin going high. If the bus stuck low does not go high within 30ms (typical), the FAULT pin pulls low indicating a bus stuck low condition. If DISCEN is connected to VCC, the connection circuitry is disabled, breaking the connection between the respective input and output pins. In addition, after at least 40μs, up to 16 clock pulses at 8.5kHz (typical) is generated on the SCLOUT pin by the LTC4309 in an attempt to free the stuck low bus. Once the clock pulses have completed, a stop bit is generated on the SCLOUT and SDAOUT pins to reset all devices on the bus. If the stuck low SDAOUT or SCLOUT recovers to a logic high, the FAULT flag clears, and the LTC4309 waits for either a stop bit or a bus idle condition to activate the connection circuitry to reconnect the input and output busses. If DISCEN is connected to GND, the FAULT pin will pull low, but the connection circuitry will not be disabled, leaving the input and output busses connected. Also, no clock or stop bit is generated. When powering up into a bus stuck low condition, the connection circuitry connecting the SDA and SCL busses on the I/O card with those on the backplane is not activated. 30ms after UVLO, the FAULT pin pulls low indicating a bus stuck low condition and automatic clocking and stop bit generation takes place as described above. READY Digital Output This pin provides a digital flag which is low when either ENABLE is low, the start-up sequence described earlier in this section has not been completed, or the LTC4309 4309fa 9 LTC4309 OPERATION has disconnected the input and output busses due to a bus stuck low condition. READY goes high when ENABLE is high and start-up is complete. The pin is driven by an open drain pull-down device capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor to the bus pull-up supply to provide the pull-up. FAULT Digital Output This pin provides a digital flag which is low when SDA or SCL is low for 30ms (typical). The pin is driven by an open drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor from FAULT to the bus pull-up supply to provide the pull-up. ENABLE When the ENABLE pin is driven below 0.8V with respect to the LTC4309’s ground, the input pin is disconnected from the output pin and the READY pin is internally pulled low. When the pin is driven above 2V, the part waits for data transactions on both the input and output pins to be complete (as described in the Start-Up section) before connecting the two sides. At this time the internal pulldown on READY releases. A rising edge on ENABLE after a fault has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT, even if the bus stuck low conditions has not been cleared. At this time, the 30ms timer is reset, but not disabled. APPLICATIONS INFORMATION Live Insertion and Capacitance Buffering Application Figures 4 and 5 illustrate applications of the LTC4309 that take advantage of the LTC4309’s Hot SwapTM, capacitance buffering and precharge features. If the I/O cards were plugged directly into the backplane without the LTC4309 buffer, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements difficult to meet. Placing an LTC4309 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4309 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4309, which is less than 10pF. Figure 4 shows the LTC4309 used in the typical staggered connector application, where VCC and GND are the longest “early power” pins. The “early power” pins ensure the LTC4309 is initially powered and forcing a 1V precharge voltage on the medium length SDA and SCL pins before they contact to the backplane busses. Coupled with ENABLE as the shortest pin, passively pulled to ground by a resistor, the staggered approach provides additional time for transients associated with live insertion to settle before the LTC4309 can be enabled. Figure 5 shows the LTC4309 in an application where all of the pins have the same length. In this application, a resistor is used to hold the ENABLE pin low during live insertion, until the backplane control circuitry can enable the device. Repeater/Bus Extender Applications Users who wish to connect two 2-wire systems separated by a distance can do so by connecting two LTC4309s backto-back, as shown in Figure 6. The I2C specification allows for 400pF maximum bus capacitance, severely limiting the length of the bus. The SMBus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise time and fall time specifications are to be met. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-toback LTC4309s add together, directly contributing to the same problem. Figure 7 further illustrates a repeater application. In AdvancedTCA applications, the bus pull-up resistance can be quite small. Since there is no effect on the offset due Hot Swap is a trademark of Linear Technology Corporation. 4309fa 10 LTC4309 APPLICATIONS INFORMATION to the pull-up impedance, multiple LTC4309 buffers can be used in a single system. This allows the user to divide the line and device capacitances into more sections with buffering and meet rise and fall times. The LTC4309 disconnects when both bus I/O’s are above 0.48V and rising. In systems with large ground bounce, if many devices are cascaded, the 0.48V threshold can be exceeded, and the transients associated with the ground bounce can appear to be a rising edge. Under this condition, the LTC4309 with inputs above 0.48V may disconnect. Level Shifting Applications Systems requiring different supply voltages for the backplane side and the card side can use the LTC4309 for bidirectional level shifting, as shown in Figure 6. The LTC4309 can level shift between bus pull-up supplies as low as 1.7V, with the accelerators disabled, to as high as 5.5V. Level shifting allows newer designs that require low voltage supplies, such as EEPROMs and microcontrollers, the capability to interface with legacy backplanes which may be operating at higher supply voltages. Systems with Supply Voltage Droop In large 2-wire systems, the supply voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. For proper operation, make sure that the VCC2(LTC4309) is ≥ 1.8V, and VCC(LTC4309) ≥ 2.3V. Additional Pull-Up Supply Options In typical applications, a pull-up resistor connected from the LTC4309’s bus output pins to VCC and bus input pins to VCC2 or VCC, if VCC2 is grounded, is sufficient. However, for unique applications, additional flexibility is available for bus pull-up supplies other than VCC or VCC2. One example is shown in Figure 8. The expanded bus pull-up range is dependent on the user configuration of the rise time accelerators and the supply voltage, VCC. If the rise time accelerators are enabled, the bus pull-up supply can be greater than or equal to VCC for the output busses and accordingly, the input pull-up supply can be greater than or equal to VCC2 for the input busses. This ensures the LTC4309’s rise time accelerators do not source current through the pull-up resistors into the pull-up supply. If the rise time accelerator circuitries are disabled, the bus pull-up supply can be as low as 2V for VCC ≥ 2.9V and for VCC < 2.9V, the bus pull-up supply can be as low as 1.7V. The bound on the lower supply limit exists to ensure the bus signal range exceeds the logic input threshold voltage, VTHR. Resistor Pull-Up Value Selection To guarantee the rise time accelerators are activated during a rising edge, the bus must rise on its own with a positive slew rate of at least 0.8V/μs. To achieve this, choose a maximum resistor value RPULLUP using the formula: RPULLUP (VBUS(MIN) – 0.8V)• 1250 ns V CBUS Where RPULLUP is the pull-up resistor value in kilo ohms, VBUS(MIN) is the minimum bus pull-up supply voltage and CBUS is the equivalent bus capacitance in pico-Farads (pF). To estimate the value of CBUS, use a general rule of 20pF of capacitance per device on the bus (10pF for the device and 10pF for interconnect). In addition, RPULLUP must be strong enough to overcome the precharge voltage and provide logic highs on SDAOUT and SCLOUT for the start-up and connection circuitry to connect the backplane to the card. Regardless of the bus capacitance, always choose RPULLUP VBUS(MAX) – VTHR 100μA 4309fa 11 LTC4309 APPLICATIONS INFORMATION BACKPLANE CONNECTOR BACKPLANE VCC CARD CONNECTORS I/O PERIPHERAL CARD 1 C1 0.01μF C2 0.01μF VCC2 R1 10k R2 10k R3 10k R4 10k VCC2 SDA SDAIN SCL SCLIN FAULT FAULT READY READY ENABLE ENA1 R7 10k VCC LTC4309 R5 10k R6 10k DISCEN SDAOUT CARD 1_SDA SCLOUT CARD 1_SCL ACC GND I/O PERIPHERAL CARD N C3 0.01μF C4 0.01μF VCC2 SDAIN SCLIN VCC LTC4309 R8 10k R9 10k DISCEN SDAOUT CARD N_SDA SCLOUT CARD N_SCL ACC FAULT READY ENABLE ENAN R10 10k GND 4309 F01 Figure 4. The LTC4309 in an Application with a Staggered Connector. 4309fa 12 LTC4309 APPLICATIONS INFORMATION BACKPLANE CONNECTOR CARD CONNECTORS BACKPLANE I/O PERIPHERAL CARD 1 VCC C1 0.01μF C2 0.01μF VCC2 R1 10k R2 10k R3 10k R4 10k VCC VCC2 SDA SDAIN SCL SCLIN FAULT FAULT READY READY R6 10k DISCEN LTC4309 SDAOUT CARD 1_SDA SCLOUT CARD 1_SCL ACC ENABLE ENA1 R5 10k GND R7 10k I/O PERIPHERAL CARD N C3 0.01μF C4 0.01μF VCC VCC2 SDAIN R9 10k DISCEN LTC4309 SCLIN R8 10k SDAOUT CARD N_SDA SCLOUT CARD N_SCL ACC FAULT READY ENABLE ENAN R10 10k GND 4309 F01 Figure 5. The LTC4309 in an Application Where All the Pins Have the Same Length. 2.5V 3.3V 5V R1 10k R2 10k R3 10k R4 10k C1 0.01μF C2 0.01μF VCC VCC2 C3 0.01μF R5 2.7k R6 2.7k VCC2 C4 0.01μF DISCEN ENABLE ENABLE SCL1 SCLOUT ACC R10 10k LTC4309 FAULT SDAOUT R9 10k READY LTC4309 SDA1 R8 10k VCC DISCEN READY R7 10k FAULT SDAIN SDAIN SDAOUT SDA2 SCLIN SCLIN SCLOUT SCL2 GND GND ACC 4309 F04 Figure 6. The LTC4309 in a Level Shifting Repeater/Bus Extender Application. 4309fa 13 LTC4309 APPLICATIONS INFORMATION VCC VCC R1 2.7k R2 2.7k R3 10k R4 10k C1 0.01MF C2 0.01MF C3 0.01MF R5 2.7k VCC VCC2 R6 2.7k C4 0.01MF R7 10k R8 10k R9 2.7k R10 2.7k R11 10k R12 10k C5 0.01MF VCC2 VCC C6 0.01MF DISCEN DISCEN ENABLE ENABLE ENABLE READY READY FAULT FAULT LTC4309 LTC4309 LTC4309 FAULT SDA1 SDAOUT SDAIN SDAIN SDAOUT SDAOUT SDAIN SCL1 SCLOUT SCLIN SCLOUT SCLOUT SCLIN ACC GND R14 2.7k VCC VCC2 DISCEN READY R13 2.7k GND ACC SDA2 SCLIN SCL2 ACC GND 4309 F05 Figure 7. The LTC4309 in a Repeater Application. The LTC4309’s Low Offset Allows Cascading of Multiple Devices. 2.5V 3.3V C2 0.01μF R1 2.7k R2 2.7k VCC2 5V R3 10k R4 10k R5 10k R6 10k VCC DISCEN ENABLE READY LTC4309 FAULT SDA1 SDAIN SDAOUT SCL1 SCLIN SCLOUT GND ACC SDA2 SCL2 4309 F06 Figure 8. The LTC4309 in a level shifting application where the bus supplies are different from VCC. 4309fa 14 LTC4309 PACKAGE DESCRIPTION DE/UE Package 12-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1695) 0.70 p0.05 3.60 p0.05 1.70 p0.05 2.20 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 3.30 p0.05 (2 SIDES) 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 p0.10 (2 SIDES) 7 0.40 p 0.10 R = 0.115 TYP 12 R = 0.05 TYP 3.00 p0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 1.70 p 0.05 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER 6 0.25 p 0.05 0.75 p0.05 0.200 REF 1 3.30 p0.05 (2 SIDES) 0.00 – 0.05 (UE12/DE12) DFN 0905 REV C 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 p.005 .009 (0.229) REF 16 15 14 13 12 11 10 9 .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .0165 p.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 p .004 s 45o (0.38 p 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 .0532 – .0688 (1.35 – 1.75) 7 8 .004 – .0098 (0.102 – 0.249) 0o – 8o TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 4309fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC4309 TYPICAL APPLICATION 5V to 3.3V Level Translator 3.3V 5V C1 0.01MF R1 10k C2 0.01MF R2 10k VCC2 R3 10k R4 10k R5 10k R6 10k VCC DISCEN ENABLE READY LTC4309 FAULT SDA1 SDAIN SDAOUT SCL1 SCLIN SCLOUT GND ACC SDA2 SCL2 4309 F07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog MUX with SMBus Interface Low RON: 35Ω Single Ended/70Ω Differential, Expandable to 32 Single or 16 Differential Channels LTC1427-50 Micropower, 10-Bit Current Output DAC with SMBus Interface Precision 50uA+/–2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16 Channel Capability LTC1663 SMBus Interface 10-Bit Rail to Rail Micropower DAC DNL < 0.75 LSB Max, 5-Lead SOT-23 Package LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices LTC1695 SMBus/I2C Fan Speed Controller in ThinSOT™ 0.75Ω PMOS 180mA Regulator, 6-Bit DAC LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Configurations LTC1840 Dual I2C Fan Speed Controller Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO LTC4300A-1/ LTC4300A-2/ LTC4300A-3 Hot Swappable 2-Wire Bus Buffers –1: Bus Buffer with READY, ACC and ENABLE –2: Dual Supply Bus Buffer with READY and ACC –3: Dual Supply Bus Buffer with READY and ENABLE LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent LTC4301L Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN LTC4302-1/ LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled LTC4303 LTC4304 Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery Provides Automatic Clocking to Free Stuck I2C Busses LTC4305 LTC4306 2 or 4-Channel, 2 Wire Bus Multiplexers with Capacitance Buffering 2 or 4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time Accelerators, Fault Reporting, ± 10kV HBM ESD Tolerance LTC4307 Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery 60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators, ± 5kV HBM ESD Tolerance LTC4307-1 High Definition Multimedia Interface (HDMI) Level Shifting 60mV Buffer Offset, 3.3V to 5V Level Shifting, 2-Wire Bus Buffer ± 5kV HBM ESD Tolerance ThinSOT is a trademark of Linear Technology Corporation 4309fa 16 Linear Technology Corporation LT 0108 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006