Freescale MPC823 Ac electrical specification Datasheet

Freescale Semiconductor
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MPC823ELE/D
Revision 1
MPC823 AC Electrical Specifications
Freescale Semiconductor, Inc...
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC823.
Note: Visit our website at www.motorola.com if you are using a frequency other than
25, 40, or 50MHz. Our website contains a spreadsheet that you can use to
calculate the timing for your specific system frequency.
This device contains circuitry protecting against damage from high-static voltage or electrical
fields. However, it is advised that precautions be taken to avoid application of any voltages
higher than the maximum-rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC).
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale Semiconductor, Inc.
MAXIMUM RATINGS (GND = 0V)
RATING
SYMBOL
VALUE
UNIT
VDDH
-0.3 to 4.0
V
VDD
-0.3 to 4.0
V
KAPWR
-0.3 to 4.0
V
VDDSYN
-0.3 to 4.0
V
Input Voltage (JTAG and GPIO)
VIN
-0.3 to 5.8
V
Input Voltage (All other pins)
VIN
-0.3 to 3.3
V
Operating Temperature
TA
0 to 70û
or
-40û to 85û
ûC
TSTG
-55 to +150
ûC
Freescale Semiconductor, Inc...
Supply Voltage
Storage Temperature Range
NOTES:
1.
Functional operating conditions are given in DC Electrical Characteristics (VCC = 3.0 - 3.6
V). Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause
permanent damage to the device.
2.
CAUTION: The JTAG and GPIO input voltages cannot be more than 2.5 V greater than
supply voltage, this restriction applies also on Òpower-onÓ as well as on normal operation.
3.
5 Volt friendly inputs are inputs that tolerate 5 volts for JTAG and GPIO pins.
4.
If you are using Mask Revision Base #F98S (Revision 0), all pins except EXTAL and CLK4IN
are 5V tolerant inputs.
THERMAL CHARACTERISTICS
CHARACTERISTIC
Thermal Resistance for BGA
SYMBOL
VALUE
UNIT
qJc
~30
°C/W
MPC823 ELECTRICAL SPECIFICATIONS
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POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can be obtained from
TJ = TA + (PD ¥ qJA)
(1)
where
Freescale Semiconductor, Inc...
TA =
qJA =
PD =
PINT =
PI/O =
Ambient Temperature, ¥C
Package Thermal Resistance, Junction to Ambient, ¥C/W
PINT + PI/O
IDD x VDD, WattsÑChip Internal Power
Power Dissipation on Input and Output PinsÑUser Determined
For most applications PI/O < 0.3 ¥ PINT and can be neglected. If PI/O is neglected, an approximate
relationship between PD and TJ is:
PD =
K Õ (TJ + 273¥C)
(2)
Solving equations (1) and (2) for K gives
K=
PD ¥ (TA + 273¥C) + qJA ¥ PD
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
can be obtained by solving equations (1) and (2) iteratively for any value of TA.
Layout Practices
Each VCC pin on the MPC823 should be provided with a low-impedance path to the boardÕs
supply. Each GND pin should be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to
ground using at least four 0.1 mF bypass capacitors located as close as possible to the four
sides of the package. The capacitor leads and associated printed circuit traces connecting to
chip VCC and GND should be kept to less than half an inch per capacitor lead. A four-layer
board that employs two inner layers as VCC and GND planes should be used.
All output pins on the MPC823 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections
caused by these fast output switching times. This recommendation particularly applies to the
address and data busses. Maximum PC trace lengths of six inches are recommended.
Capacitance calculations should consider all device loads as well as parasitic capacitances
due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents
in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
MPC823 ELECTRICAL SPECIFICATIONS
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DC ELECTRICAL CHARACTERISTICS (VCC = 3.0 - 3.6 V)
CHARACTERISTIC
SYMBOL
MIN
MAX
UNIT
Input High Voltage (for JTAG and GPIO)
VIH
2.0
5.5
V
Input High Voltage (all other pins)
VIH
2.0
3.6
V
Input Low Voltage
VIL
GND
0.8
V
VIHC
0.7*(VCC)
VCC+0.3
V
Input Leakage Current, VIN = 5.5 V
IIN
Ñ
±10
µA
Hi-z (Off State) Leakage Current, VIN = 3.5V
IOZ
Ñ
±10
µA
Freescale Semiconductor, Inc...
EXTAL and EXTCLK Input High Voltage
Signal Low Input Current, VIL = 0.8 V
IL
±10
µA
Signal High Input Current, VIH = 2.0 V
IH
±10
µA
Output High Voltage, IOH = Ð2.0 mA, VDDH = 3.0V
Except XTAL, XFC, and Open-Drain Pins
VOH
2.4
Ñ
V
Output Low Voltage
IOL = 2.0 mA CLKOUT
IOL = 3.2 mAA[6:31], TSIZ0/REG, TSIZ1, D(0:31), DP[0:3]/IRQ[3:6],
RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/
IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/
VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, USBRXD/PA15, RXD2/
PA13, SMRXD2/L1TXDA/PA9, SMTXD2/L1RXDA/PA8, IRQ4/KR/
SPKROUT, TIN1/L1RCLKA/BRGO1/CLK1/PA7, TIN3/TOUT1/
CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TIN4/TOUT2/CLK4/
PA4, LCD_A/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29,
BRGO3/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/
PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23,
SMSYN2/SDACK2/PB22, LCD_B/L1ST1/PB19, L1ST2/RTS2/
PB18, LCD_C/L1ST3/PB17, L1ST4/L1RQA/PB16, L1ST5/DREQ1/
PC15, L1ST6/RTS2/DREQ2/PC14, L1ST7/PC13, L1ST8/L1RQA/
PC12, USBRXP/PC11, USBRXN/TGATE1/PC10, CTS2/PC9,
TGATE1/CD2/PC8, USBTXP/PC7, USBTXN/PC6, SDACK1/
L1TSYNCA/PC5, L1RSYNCA/PC4, LD8/VD7/PD15, LD7/VD6/
PD14, LD6/VD5/PD13, LD5/VD4/PD12, LD4/VD3/PD11, LD3/VD2/
PD10, LD2/VD1/PD9, LD1/VD0/PD8, FRAME/VSYNC/PD5,
LCD_AC/LOE/BLANK/PD6, LD0/FIELD/PD7, LOAD/HSYNC/PD4,
SHIFT/CLK/PD3
VOL
Ñ
0.5
V
IOL = 5.3 mABDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/
CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,
WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/
GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/
GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,
OP2/MODCK1/STS, OP3/MODCK2/DSDO
IOL = 7.0 mA USBOE/PA14, TXD2/PA12
IOL = 8.9 mATS, TA, TEA, BI, BB, HRESET, SRESET
NOTE: Input pin voltage specifications are VCC = +4 V or 5.8 V, whichever is less.
AC timings are based on a 50 p¦ load.
If you are using Mask Revision Base #F98S, all pins except EXTAL and CLK4IN are 5V tolerant inputs.
MPC823 ELECTRICAL SPECIFICATIONS
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AC ELECTRICAL CHARACTERISTICS
2.0V
2.0V
CLKOUT
0.8V
0.8V
A
B
Freescale Semiconductor, Inc...
OUTPUTS
2.0V
2.0V
0.8V
0.8V
A
B
OUTPUTS
2.0V
2.0V
0.8V
0.8V
C
D
2.0V
2.0V
0.8V
0.8V
INPUTS
C
D
2.0V
2.0V
0.8V
0.8V
INPUTS
A = MAXIMUM OUTPUT DELAY SPECIFICATION
B = MINIMUM OUTPUT HOLD TIME
C = MINIMUM INPUT SETUP TIME SPECIFICATION
D = MINIMUM INPUT HOLD TIME SPECIFICATION
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EXTERNAL BUS ELECTRICAL CHARACTERISTICS
Table 1. Bus Operation Timing
25MHz
Freescale Semiconductor, Inc...
NUM
40MHz
50MHz
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
40
Ñ
25
Ñ
20
Ñ
ns
B1
CLKOUT Period
B1a
EXTCLK to CLKOUT Phase Skew (EXTCLK>15MHz and
MF £ 2)
-0.9
0.9
-0.9
0.9
-0.9
0.9
ns
B1b
EXTCLK to CLKOUT Phase Skew (EXTCLK>10MHz and
MF £ 10)
-2.3
2.3
-2.3
2.3
-2.3
2.3
ns
B1c
CLKOUT Phase Jitter (EXTCLK>15MHz and MF£2)
-0.6
0.6
-0.6
0.6
-0.6
0.6
ns
B1d
CLKOUT Phase Jitter (EXTCLK>10MHz and MF£10)
-2
2
-2
2
-2
2
ns
B1e
CLKOUT Frequency Jitter (MF<10)
Ñ
0.5
Ñ
0.5
Ñ
0.5
%
B1f
CLKOUT Frequency Jitter (10<MF<500)
Ñ
2
Ñ
2
Ñ
2
%
B1g
CLKOUT Frequency Jitter (MF>500)
Ñ
3
Ñ
3
Ñ
3
%
B1h
Frequency Jitter on EXTCLK
Ñ
0.5
Ñ
0.5
Ñ
0.5
%
B2
Clock Pulse Width Low
16
Ñ
10
Ñ
8
Ñ
ns
B3
Clock Pulse Width High
16
Ñ
10
Ñ
8
Ñ
ns
B4
CLKOUT Rise Time
Ñ
4
Ñ
4
Ñ
4
ns
B5
CLKOUT Fall Time
Ñ
4
Ñ
4
Ñ
4
ns
B6
N/A (Used on Interactive Spreadsheet)
B7
CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3)
Invalid
10
Ñ
5
Ñ
5
Ñ
ns
B7a
CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3),BDIP, PTR Invalid
10
Ñ
5
Ñ
5
Ñ
ns
B7b
CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2),
LWP(0:1), STS Invalid
10
Ñ
5
Ñ
5
Ñ
ns
B8
CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3) Valid
10
19
5
13
5
12
ns
B8a
CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3), BDIP, PTR Valid
10
19
5
13
5
12
ns
B8b
CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ,
LWP(0:1), STS Valid
10
19
5
13
5
12
ns
B9
CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1),REG, RSV, AT(0:3), PTR Hi Z
10
19
5
13
5
12
ns
B10
N/A
B11
CLKOUT to TS, BB Assertion
10
19
5
12.25
5
12.25
ns
2.5
11
2.5
9.25
2.5
9.25
ns
10
19
5
13
5
12
ns
2.5
11
2.5
11
2.5
11
ns
10
24
5
21
5
19
ns
to TA, BI Assertion (when driven by the
B11a CLKOUT
Memory Controller or PCMCIA Interface)
B12
CLKOUT to TS, BB Negation
to TA, BI Negation (when driven by the
B12a CLKOUT
Memory Controller or PCMCIA Interface)
B13
CLKOUT to TS, BB Hi Z
MPC823 ELECTRICAL SPECIFICATIONS
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Table 1. Bus Operation Timing (Continued)
25MHz
NUM
to TA, BI Hi Z (When Driven by the Memory
B13a CLKOUT
Controller or PCMCIA Interface)
Freescale Semiconductor, Inc...
40MHz
50MHz
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
2.5
15
2.5
15
2.5
16
ns
B14
CLKOUT to TEA Assertion
2.5
11
2.5
11
2.5
10
ns
B15
CLKOUT to TEA Hi Z
2.5
15
2.5
15
2.5
15
ns
B16
TA, BI Valid to CLKOUT (Setup Time)
9.75
Ñ
9.75
Ñ
9.75
Ñ
ns
B16a TEA, KR, RETRY Valid to CLKOUT (Setup Time)
11
Ñ
10
Ñ
10
Ñ
ns
B16b BB, BG, BR Valid to CLKOUT (Setup Time)
8.5
Ñ
8.5
Ñ
8.5
Ñ
ns
1
Ñ
1
Ñ
1
Ñ
ns
B17a CLKOUT to KR, RETRY Valid (Hold Time)
2
Ñ
2
Ñ
2
Ñ
ns
B18
D(0:31), DP(0:3) Valid to CLKOUT Rising Edge (Setup Time)
6
Ñ
6
Ñ
6
Ñ
ns
B19
CLKOUT Rising Edge to D(0:31), DP(0:3) Valid (Hold Time)
2
Ñ
2
Ñ
2
Ñ
ns
B20
D(0:31), DP(0:3) Valid to CLKOUT Falling Edge (Setup Time)
4
Ñ
4
Ñ
4
Ñ
ns
B21
CLKOUT Falling Edge to D(0:31), DP(0:3) Valid (Hold Time)
2
Ñ
2
Ñ
2
Ñ
ns
B22
CLKOUT Rising Edge to CS Asserted -GPCM- ACS = 00
10
20
5
13
5
13
ns
Falling Edge to CS Asserted -GPCM- ACS = 10,
B22a CLKOUT
TRLX = 0
Ñ
10
Ñ
8
Ñ
8
ns
Falling Edge to CS Asserted -GPCM- ACS = 11,
B22b CLKOUT
TRLX = 0, EBDF = 0
10
20
5
13
5
13
ns
B22c
CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11,
TRLX = 0, EBDF = 1
14
25
7
16
7
16
ns
B23
CLKOUT Rising Edge to CS Negated -GPCM-Read Access GPCM-Write Access, ACS=00, TRLX=0, CSNT=0
3
10
2
8
2
8
ns
B24
A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 0
8
Ñ
3
Ñ
3
Ñ
ns
B24a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 0
18
Ñ
8
Ñ
8
Ñ
ns
B25
CLKOUT Rising Edge to OE, WE(0:3) Asserted
Ñ
11
Ñ
9
Ñ
9
ns
B26
CLKOUT Rising Edge to OE Negated
3
11
2
9
2
9
ns
B27
A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 1
48
Ñ
23
Ñ
23
Ñ
ns
B27a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 1
58
Ñ
28
Ñ
28
Ñ
ns
CLKOUT Rising Edge to WE(0:3) Negated -GPCM-Write
Access CSNT = Ô0Ô
Ñ
11
Ñ
9
Ñ
9
ns
Falling Edge to WE(0:3) Negated -GPCM-Write
B28a CLKOUT
Access TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF=0
10
20
5
13
5
13
ns
Falling Edge to CS Negated -GPCM-Write Access
B28b CLKOUT
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0
Ñ
20
Ñ
13
Ñ
13
ns
B17
B28
CLKOUT to TA, TEA, BI , BB, BG, BR Valid (Hold Time)
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Table 1. Bus Operation Timing (Continued)
25MHz
NUM
50MHz
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
14
25
7
16
7
16
ns
Ñ
25
Ñ
16
Ñ
16
ns
WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, CSNT = Ô0Õ
8
Ñ
3
Ñ
3
Ñ
ns
Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
B29a WE(0:3)
Access, TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF = 0
18
Ñ
8
Ñ
8
Ñ
ns
Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
B29b CS
ACS = Ô00Õ, TRLX = Ô0Õ & CSNT = Ô0Õ
8
Ñ
3
Ñ
3
Ñ
ns
CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0
18
Ñ
8
Ñ
8
Ñ
ns
WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
B29d Access,
TRLX = Ô1Õ, CSNT = Ô1Õ, EBDF = 0
58
Ñ
28
Ñ
28
Ñ
ns
Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
B29e CS
TRLX = Ô1Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0
58
Ñ
28
Ñ
28
Ñ
ns
12
Ñ
5
Ñ
5
Ñ
ns
Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
B29g CS
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 1
12
Ñ
5
Ñ
5
Ñ
ns
WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
B29h Access,
TRLX = Ô1Õ, CSNT = Ô1Õ, EBDF = 1
52
Ñ
24
Ñ
24
Ñ
ns
ns
B28c
CLKOUT Falling Edge to WE(0:3) Negated -GPCM-Write
Access TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF=1
Falling Edge to CS Negated -GPCM-Write Access
B28d CLKOUT
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 1
B29
Freescale Semiconductor, Inc...
40MHz
CHARACTERISTIC
B29c
B29f
WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF = 1
B29i
CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô1Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF =1
52
Ñ
24
Ñ
24
Ñ
B30
CS, WE(0:3) Negated to A(6:31) invalid -GPCM- Write
Access.
8
Ñ
3
Ñ
3
Ñ
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCMB30a TRLX=Õ0Õ,
Write Access, TRLX=Õ0Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 0
18
Ñ
8
Ñ
8
Ñ
ns
WE(0:3) Negated to A(6:31)Invalid -GPCM- Write Access,
CSNT = '1Õ. CS Negated to A(6:31)Invalid -GPCMB30b TRLX=Õ1Õ,
Write Access, TRLX=Õ1Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 0
58
Ñ
28
Ñ
28
Ñ
ns
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
TRLX=Õ0Õ, CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCMWrite Access, TRLX=Õ0Õ, CSNT = '1Õ, ACS = 10 ,ACS = =Õ11Õ,
EBDF = 1
12
Ñ
4
Ñ
4
Ñ
ns
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCMB30d TRLX=Õ1Õ,
Write Access, TRLX=Õ1Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 1
52
Ñ
24
Ñ
24
Ñ
ns
1.5
10
1.5
8
1.5
8
ns
B30c
B31
CLKOUT Falling Edge to CS valid as requested by CST4 in
the corresponding word of the UPM
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Table 1. Bus Operation Timing (Continued)
25MHz
NUM
50MHz
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Falling Edge to CS valid as requested by CST1 in
B31a CLKOUT
the corresponding word of the UPM, EBDF = 0
10
20
5
13
5
13
ns
CLKOUT Rising Edge to CS valid as requested by CST2 in
B31b the
corresponding word of the UPM
1.5
10
1.5
8
1.5
8
ns
CLKOUT Rising Edge to CS valid as requested by CST3 in
the corresponding word of the UPM
10
20
5
13
5
13
ns
Falling Edge to CS valid as requested by CST1 in
B31d CLKOUT
the corresponding word of the UPM, EBDF = 1
10
25
5
16
5
16
ns
CLKOUT Falling Edge to BS valid as requested by BST4 in
the corresponding word of the UPM
1.5
10
1.5
8
1.5
8
ns
Falling Edge to BS valid as requested by BST1 in
B32a CLKOUT
the corresponding word of the UPM, EBDF = 0
10
20
5
13
5
13
ns
CLKOUT Rising Edge to BS valid as requested by BST2 in the
B32b corresponding
word of the UPM
1.5
10
1.5
8
1.5
8
ns
CLKOUT Rising Edge to BS valid as requested by BST3 in the
corresponding word of the UPM
10
20
5
13
5
13
ns
10
25
5
16
5
16
ns
CLKOUT Falling Edge to GPL valid as requested by GxT4 in
the corresponding word of the UPM
1.5
10
1.5
8
1.5
8
ns
Rising Edge to GPL valid as requested by GxT3 in
B33a CLKOUT
the corresponding word of the UPM
10
20
5
13
5
13
ns
A(6:31) and D(0:31) to CS valid as requested by CST4 in the
corresponding word of the UPM
8
Ñ
3
Ñ
3
Ñ
ns
and D(0:31) to CS valid as requested by CST1 in the
B34a A(6:31)
corresponding word of the UPM
18
Ñ
8
Ñ
8
Ñ
ns
and D(0:31) to CS valid as requested by CST2 in the
B34b A(6:31)
corresponding word of the UPM
28
Ñ
13
Ñ
13
Ñ
ns
A(6:31) and D(0:31) to BS valid as requested by BST4 in the
corresponding word of the UPM
8
Ñ
3
Ñ
3
Ñ
ns
and D(0:31) to BS valid as requested by BST1 in the
B35a A(6:31)
corresponding word of the UPM
18
Ñ
8
Ñ
8
Ñ
ns
and D(0:31) to BS valid as requested by BST2 in the
B35b A(6:31)
corresponding word of the UPM
28
Ñ
13
Ñ
13
Ñ
ns
B36
A(6:31) and D(0:31) to GPL valid as requested by GxT4 in the
corresponding word of the UPM
8
Ñ
3
Ñ
3
Ñ
ns
B37
UPWAIT Valid to CLKOUT Falling Edge
6
Ñ
6
Ñ
6
Ñ
ns
B38
CLKOUT Falling Edge to UPWAIT Valid
1
Ñ
1
Ñ
1
Ñ
ns
B39
AS Valid to CLKOUT Rising Edge
9
Ñ
7
Ñ
7
Ñ
ns
B31c
Freescale Semiconductor, Inc...
40MHz
CHARACTERISTIC
B32
B32c
Falling Edge to BS valid as requested by BST1 in
B32d CLKOUT
the corresponding word of the UPM, EBDF = 1
B33
B34
B35
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Table 1. Bus Operation Timing (Continued)
25MHz
NUM
40MHz
50MHz
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
B40
A(6:31), TSIZ(0:1), RD/WR, BURST, Valid to CLKOUT Rising
Edge
9
Ñ
7
Ñ
7
Ñ
ns
B41
TS Valid to CLKOUT Rising Edge (Setup Time)
9
Ñ
7
Ñ
7
Ñ
ns
B42
CLKOUT Rising Edge to TS Valid (Hold Time)
2
Ñ
2
Ñ
2
Ñ
ns
B43
AS Negation to Memory Controller Signals Negation
Ñ
13
Ñ
13
Ñ
13
ns
Freescale Semiconductor, Inc...
NOTES:
1.
The timing for BR output is relevant when the MPC823 is selected to work with the external bus arbiter.
The timing for BG output is relevant when the MPC823 is selected to work with the internal bus arbiter.
2.
The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device
(and not when the memory controller or the PCMCIA interface drive them).
3.
The timing required for BR input is relevant when the MPC823 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC823 is selected to work with the external bus arbiter.
4.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA
input signal is asserted.
5.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is
valid only under control of the UPM in the memory controller.
6.
The timing B30 refers to CS when ACS = Ô00Õ and to WE(0:3) when CSNT = Ô0Õ.
7.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings
speciÞed in B37 and B38 are speciÞed to enable the freeze of the UPM output signals.
8.
The AS signal is considered asynchronous to the CLKOUT signal.
CLKOUT
B1
B3
B2
B1
B4
B5
Figure 1. External Clock Timing Diagram
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CLKOUT
B8
B9
B7
Freescale Semiconductor, Inc...
OUTPUT
SIGNALS
B8a
B9
B7a
OUTPUT
SIGNALS
B8b
B7b
OUTPUT
SIGNALS
Figure 2. Synchronous Output Signals Timing Diagram
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CLKOUT
B13
B11
B12
TS, BB
Freescale Semiconductor, Inc...
B13a
B11a
B12a
TA, BI
B14
B15
TEA
Figure 3. Synchronous Active Pull-Up and Open-Drain
Outputs Signals Timing Diagram
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CLKOUT
B16
Freescale Semiconductor, Inc...
B17
TA, BI, TEA
B16a
B17a
TEA, RETRY, KR
B16b
B17
BB, BG, BR
Figure 4. Synchronous Input Signals Timing Diagram
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Freescale Semiconductor, Inc.
CLKOUT
B16
B17
Freescale Semiconductor, Inc...
TA
B18
B19
D(0:31),
DP(0:3)
Figure 5. Input Data In Normal Case Timing Diagram
CLKOUT
TA
B20
B21
D(0:31),
DP(0:3)
Figure 6. Input Data When Controlled by the UPM Timing Diagram
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CLKOUT
B11
B12
TS
B8
A(6:31)
B23
B22a
Freescale Semiconductor, Inc...
CSx
B26
B25
OE
B28
WE(0:3)
B18
D(0:31),
DP(0:3)
B19
Figure 7. External Bus Read Timing Diagram (GPCM ControlledÐACS = Ô00Õ)
CLKOUT
B11
B12
TS
B8
A(6:31)
B22b
B23
B22c
CSx
B24a
B25
B26
OE
B18
D(0:31),
DP(0:3)
B19
Figure 8. External Bus Read Timing Diagram (GPCM ControlledÐTRLX = Ô0Õ, ACS = Ô10Õ)
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Freescale Semiconductor, Inc.
CLKOUT
B11
B12
TS
B8
A(6:31)
Freescale Semiconductor, Inc...
B22b
B23
B22c
CSx
B24a
B26
B25
OE
B18
D(0:31),
DP(0:3)
B19
Figure 9. External Bus Read Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, ACS = Ô11Õ)
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CLKOUT
B11
B12
TS
B8
A(6:31)
B22a
Freescale Semiconductor, Inc...
CSx
B23
B27
B26
B27a
OE
B18
B22b
D(0:31),
DP(0:3)
B22c
B19
Figure 10. External Bus Read Timing Diagram
(GPCM ControlledÐTRLX = Ô1Õ, ACS = Ô10Õ, ACS = Ô11Õ)
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CLKOUT
B11
B12
TS
B8
B30
A(6:31)
B23
Freescale Semiconductor, Inc...
B22
B29b
CSx
B25
B28
WE(0:3)
B26
OE
B29
B8
D(0:31),
DP(0:3)
B9
Figure 11. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, CSNT = Ô0Õ)
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CLKOUT
B11
B12
TS
B30
B30a
Freescale Semiconductor, Inc...
B8
A(6:31)
B23
B22
B28b
CSx
B28d
B25
B29c
B29g
WE(0:3)
B26
B29f
B29a
B28a
OE
B28c
B8
D(0:31),
DP(0:3)
B9
Figure 12. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, CSNT = Ô1Õ)
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Freescale Semiconductor, Inc.
CLKOUT
B11
B12
TS
B30d
B8
B30b
A(6:31)
Freescale Semiconductor, Inc...
B28d
B22
B23
CSx
B28b
B25
B29f
B29e
B29h
B29d
WE(0:3)
B26
B28a
OE
B29b
B8
B28c
D(0:31),
DP(0:3)
B9
Figure 13. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô1Õ, CSNT = Ô1Õ)
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CLKOUT
B8
A(6:31)
B31d
Freescale Semiconductor, Inc...
B31a
B31
B31c
B31b
CSx
B34
B34a
B34b
B32d
B32c
B32a
B32
B32b
BS_AB(0:3)
B35
B35a
B35b
B33a
B33
GPLA(0:5),
GPLB(0:5)
B36
Figure 14. External Bus Timing Diagram (UPM-Controlled Signals)
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CLKOUT
B37
B38
UPWAIT
Freescale Semiconductor, Inc...
CSx
BS_AB(0:3)
GPLA(0:5),
GPLB(0:5)
Figure 15. Asynchronous UPWAIT Asserted Detection in UPM
Handled Cycles Timing Diagram
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CLKOUT
B37
B38
UPWAIT
Freescale Semiconductor, Inc...
CSx
BS_AB(0:3)
GPLA(0:5),
GPLB(0:5)
Figure 16. Asynchronous UPWAIT Negated Detection in UPM
Handled Cycles Timing Diagram
CLKOUT
B42
B41
TS
B40
A(6:31), TSIZ(0:1),
RD/WR, BURST
B22
CSx
Figure 17. Synchronous External Master Access Timing Diagram
(GPCM HandledÐACS = Ô00Õ)
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CLKOUT
B39
AS
B40
Freescale Semiconductor, Inc...
A(6:31),
TSIZ(0:1),
RD/WR
B22
CSx
Figure 18. Asynchronous External Master Memory Access Timing Diagram
(GPCM ControlledÐACS = Õ00Õ)
AS
B43
CSx,
WE(0:3),
BS(0:3),
OE, GPLx,
Figure 19. Asynchronous External Master Timing Diagram
(Control Signals Negation Time)
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Table 2. Interrupt Timing
25MHZ
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
I39
IRQx valid to CLKOUT rising edge (setup time)
6
Ñ
6/6
Ñ
6/6
Ñ
ns
I40
IRQx hold time after CLKOUT
2
Ñ
2/2
Ñ
2/2
Ñ
ns
I41
IRQx pulse width low
3
Ñ
3/3
Ñ
3/3
Ñ
ns
I42
IRQx pulse width high
3
Ñ
3/3
Ñ
3/3
Ñ
ns
I43
IRQx edge to edge time
160
Ñ
80/80
Ñ
80/80
Ñ
ns
Freescale Semiconductor, Inc...
NOTES:
1.
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with
reference to the CLKOUT.
2.
The timings I41 and I42 are speciÞed to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC823 can support.
CLKOUT
I39
I40
IRQx
Figure 20. Interrupt Detection Timing Diagram
for External Level-Sensitive Lines
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CLKOUT
I39
IRQx
I43
Freescale Semiconductor, Inc...
I41
I42
I43
Figure 21. Interrupt Detection Timing Diagram
for External Edge-Sensitive Lines
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Table 3. PCMCIA Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
P44
A(6:31), REG valid to PCMCIA strobe asserted
28
Ñ
13
Ñ
13
Ñ
ns
P45
A(6:31), REG valid to ALE negation
38
Ñ
18
Ñ
18
Ñ
ns
P46
CLKOUT to REG valid
10
19
5
13
5
13
ns
P47
CLKOUT to REG invalid
11
Ñ
6
Ñ
6
Ñ
ns
P48
CLKOUT to CE1, CE2 asserted
10
19
5
13
5
13
ns
P49
CLKOUT to CE1, CE2 negated
10
19
5
13
5
13
ns
P50
CLKOUT to PCOE, IORD, PCWE, IOWR assert
time
Ñ
12
Ñ
11
Ñ
11
ns
P51
CLKOUT to PCOE, IORD, PCWE, IOWR negate
time
3
12
2
11
2
11
ns
P52
CLKOUT to ALE assert time
10
19
5
13
5
13
ns
P53
CLKOUT to ALE negate time
Ñ
19
Ñ
13
Ñ
13
ns
P54
PCWE, IOWR negated to D(0:31) invalid
8
Ñ
3
Ñ
3
Ñ
ns
P55
WAIT_B valid to CLKOUT rising edge
8
Ñ
8
Ñ
8
Ñ
ns
P56
CLKOUT rising edge to WAIT_B invalid
2
Ñ
2
Ñ
2
Ñ
ns
NOTES:
1.
PSST = 1. Otherwise, add PSST times cycle time.
2.
PSHT = 0. Otherwise, add PSHT times cycle time.
3.
These synchronous timings deÞne when the WAIT_B signal is detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAIT_B assertion will be effective only if it is detected two cycles before the PSL
timer expiration.
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CLKOUT
TS
Freescale Semiconductor, Inc...
P44
A(0:31)
P45
P46
P47
REG
CE[1:2]
P49
P50
P48
P51
PCOE,
PCOE,
IORD
P52
P53
P52
ALE
B18
D(0:31)
B19
Figure 22. PCMCIA Access Cycles Timing Diagram (External Bus Read)
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CLKOUT
TS
Freescale Semiconductor, Inc...
P44
A[0:31]
P45
P46
P47
REG
CE[1:2]
P50
P49
P48
P51
PCOE,
IORD
P52
P53
P52
ALE
P54
D[0:31]
B8
B9
Figure 23. PCMCIA Access Cycles Timing Diagram (External Bus Write)
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CLKOUT
P55
Freescale Semiconductor, Inc...
P56
WAITx
Figure 24. PCMCIA Wait Signals Detection Timing Diagram
CLKOUT
P55
P56
WAITx
Figure 25. PCMCIA Wait Signals Detection Timing Diagram
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Table 4. PCMCIA Port Timing
25MHZ
NUM
50MHZ
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
P57
CLKOUT to OPx Valid
Ñ
25
Ñ
19
Ñ
19
ns
P58
HRESET negated to OPx drive
30
Ñ
18
Ñ
18
Ñ
ns
P59
IP_Bx valid to CLKOUT Rising Edge
6
Ñ
5
Ñ
5
Ñ
ns
P60
CLKOUT Rising Edge to IP_Bx invalid
2
Ñ
1
Ñ
1
Ñ
ns
NOTE:
Freescale Semiconductor, Inc...
40MHZ
CHARACTERISTIC
*OP2 and OP3 only.
CLKOUT
P57
OUTPUT
SIGNALS
HRESET
P58
OP2, OP3
Figure 26. PCMCIA Output Port Timing Diagram
CLKOUT
P59
P60
INPUT
SIGNALS
Figure 27. PCMCIA Input Port Timing Diagram
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Table 5. Debug Port Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
D61
DSCK cycle time
120
Ñ
60
Ñ
60
Ñ
ns
D62
DSCK clock pulse width
50
Ñ
25
Ñ
25
Ñ
ns
D63
DSCK rise and fall times
0
3
0
3
0
3
ns
D64
DSDI input data setup time
8
Ñ
8
Ñ
8
Ñ
ns
D65
DSDI data hold time
5
Ñ
5
Ñ
5
Ñ
ns
D66
DSCK low to DSDO data valid
0
15
0
15
0
15
ns
D67
DSCK low to DSDO invalid
0
2
0
2
0
2
ns
CLKOUT
D61
D63
D62
D61
D62
D63
Figure 28. Debug Port Clock Input Timing Diagram
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DSCK
D64
D65
Freescale Semiconductor, Inc...
DSDI
D66
D67
DSDO
Figure 29. Debug Port Timing Diagram
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Table 6. Reset Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
R68
CLKOUT to HRESET high impedance
Ñ
20
Ñ
20
Ñ
20
ns
R69
CLKOUT to SRESET high impedance
Ñ
20
Ñ
20
Ñ
20
ns
R70
RSTCONF pulse width
680
Ñ
425
Ñ
340
Ñ
ns
R71
N/A
R72
Configuration data to HRESET rising edge setup
time
650
Ñ
425
Ñ
350
Ñ
ns
R73
Configuration data to RSTCONF rising edge setup
time
650
Ñ
425
Ñ
350
Ñ
ns
R74
Configuration data hold time after RSTCONF
negation
0
Ñ
0
Ñ
0
Ñ
ns
R75
Configuration data hold time after HRESET negation
0
Ñ
0
Ñ
0
Ñ
ns
R76
HRESET and RSTCONF asserted to data out drive
Ñ
25
Ñ
25
Ñ
25
ns
R77
RSTCONF negated to data out high impedance
Ñ
25
Ñ
25
Ñ
25
ns
R78
CLKOUT of last rising edge before chip three-states
HRESET to data out high impedance
Ñ
25
Ñ
25
Ñ
25
ns
R79
DSDI and DSCK setup
120
Ñ
75
Ñ
60
Ñ
ns
R80
DSDI and DSCK hold time
0
Ñ
0
Ñ
0
Ñ
ns
R81
SRESET negated to CLKOUT rising edge for DSDI
and DSCK sample
320
Ñ
200
Ñ
160
Ñ
ns
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HRESET
R71
RSTCONF
Freescale Semiconductor, Inc...
R76
R73
R75
D(0:31) (IN)
R74
Figure 30. Reset Timing Diagram (Configuration from Data Bus)
CLKOUT
R69
HRESET
RSTCONF
R78
R77
R79
D(0:31) (OUT)
(WEAK)
Figure 31. Reset Timing DiagramÐMPC823 Data Bus Weak Drive During Configuration
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CLKOUT
R70
Freescale Semiconductor, Inc...
R82
SRESET
R80
R80
R81
R81
DSCK, DSDI
Figure 32. Reset Timing DiagramÐDebug Port Configuration
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Table 7. JTAG Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
J82
TCK cycle time
100
Ñ
100
Ñ
100
Ñ
ns
J83
TCK clock pulse width measured at 1.5V
40
Ñ
40
Ñ
40
Ñ
ns
J84
TCK rise and fall times
0
10
0
10
0
10
ns
J85
TMS, TDI data setup time
5
Ñ
5
Ñ
5
Ñ
ns
J86
TMS, TDI data hold time
25
Ñ
25
Ñ
25
Ñ
ns
J87
TCK low to TDO data valid
Ñ
27
Ñ
27
Ñ
27
ns
J88
TCK low to TDO data invalid
0
Ñ
0
Ñ
0
Ñ
ns
J89
TCK low to TDO high impedance
Ñ
20
Ñ
20
Ñ
20
ns
J90
TRST assert time
100
Ñ
100
Ñ
100
Ñ
ns
J91
TRST setup time to TCK low
40
Ñ
40
Ñ
40
Ñ
ns
J92
TCK falling edge to output valid
Ñ
50
Ñ
50
Ñ
50
ns
J93
TCK falling edge to ouput valid out of high impedance
Ñ
50
Ñ
50
Ñ
50
ns
J94
TCK falling edge to output high impedance
Ñ
50
Ñ
50
Ñ
50
ns
J95
Boundary scan input valid to TCK rising edge
50
Ñ
50
Ñ
50
Ñ
ns
J96
TCK rising edge to boundary scan input invalid
50
Ñ
50
Ñ
50
Ñ
ns
TCK
J84
J82
J84
J83
J83
J82
Figure 33. JTAG Test Clock Input Timing Diagram
MPC823 ELECTRICAL SPECIFICATIONS
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37
Freescale Semiconductor, Inc.
TCK
J85
J86
Freescale Semiconductor, Inc...
TMS, TDI
J87
J89
J88
TDO
Figure 34. JTAGÐTest Access Port Timing Diagram
TCK
J91
J90
TRST
Figure 35. JTAGÐTRST Timing Diagram
MPC823 ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
TCK
J92
J94
Freescale Semiconductor, Inc...
OUTPUT
SIGNALS
J93
OUTPUT
SIGNALS
J96
J95
OUTPUT
SIGNALS
Figure 36. Boundary Scan (JTAG) Timing Diagram
MPC823 ELECTRICAL SPECIFICATIONS
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39
Freescale Semiconductor, Inc.
COMMUNICATION ELECTRICAL CHARACTERISTICS
Table 8. Parallel Input/Output Port Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
29
Data-in setup time to clock high
20
Ñ
15
Ñ
15
Ñ
ns
30
Data-in hold time from clock high
10
Ñ
7.5
Ñ
7.5
Ñ
ns
31
Clock high to data-out valid (CPU writes
data, control, or direction)
Ñ
25
Ñ
25
Ñ
25
ns
CLKOUT
29
30
DATA IN
31
DATA OUT
Figure 37. Parallel Input/Output Data-In/Data-Out Timing Diagram
MPC823 ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
Table 9. IDMA Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
40
DREQ setup time to clock high
12
Ñ
7
Ñ
7
Ñ
nsec
41
DREQ hold time from clock high
5
Ñ
3
Ñ
3
Ñ
nsec
42
SDACK assertion delay from clock high
Ñ
20
Ñ
12
Ñ
12
nsec
43
SDACK negation delay from clock low
Ñ
20
Ñ
12
Ñ
12
nsec
44
SDACK negation delay from TA low
Ñ
25
Ñ
20
Ñ
20
nsec
45
SDACK negation delay from clock high
Ñ
20
Ñ
15
Ñ
15
nsec
46
TA assertion to falling edge of the clock
setup time
12
Ñ
7
Ñ
7
Ñ
nsec
NOTE: Applies to external TA.
CLKOUT
(OUTPUT)
41
DREQ
(INPUT)
40
Figure 38. IDMA External Requests Timing Diagram
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41
Freescale Semiconductor, Inc.
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
42
43
Freescale Semiconductor, Inc...
DATA
46
TA
(OUTPUT)
SDACK
Figure 39. SDACK Timing DiagramÐPeripheral Write, TA Sampled Low
at the Falling Edge of the Clock
MPC823 ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
42
44
Freescale Semiconductor, Inc...
DATA
TA
(OUTPUT)
SDACK
Figure 40. SDACK Timing DiagramÐPeripheral Write, TA Sampled High
at the Falling Edge of the Clock
MPC823 ELECTRICAL SPECIFICATIONS
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43
Freescale Semiconductor, Inc.
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
42
Freescale Semiconductor, Inc...
DATA
TA
(OUTPUT)
SDACK
Figure 41. SDACK Timing DiagramÐPeripheral Read
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Freescale Semiconductor, Inc.
Table 10. Baud Rate Generator Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
UNIT
CHARACTERISTIC
MIN
MAX
MIN
MAX
MIN
MAX
50
BRGO rise and fall times
Ñ
10
Ñ
10
Ñ
10
ns
51
BRGO duty cycle
40
60
40
60
40
60
%
52
BRGO cycle
40
Ñ
40
Ñ
40
Ñ
ns
50
50
BRGOx
51
51
52
Figure 42. Baud Rate Generator Timing Diagram
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Freescale Semiconductor, Inc.
Table 11. General-Purpose Timers Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
61
TIN/TGATE rise and fall times
12
10
7
10
7
10
ns
62
TIN/TGATE low time
5
1
3
1
3
1
clk
63
TIN/TGATE high time
Ñ
20
Ñ
12
Ñ
12
clk
64
TIN/TGATE cycle time
Ñ
20
Ñ
12
Ñ
12
clk
65
CLKO low to TOUT valid
Ñ
25
Ñ
20
Ñ
20
ns
60
CLKOUT
61
63
62
TIN / TGATE
(INPUT)
61
64
TOUT
(OUTPUT)
65
Figure 43. General-Purpose Timers Timing Diagram
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Freescale Semiconductor, Inc.
Table 12. Serial Interface Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Ñ
10
Ñ
10
Ñ
10
MHz
70
L1RCLK and L1TCLK frequency (DSC=0)1,3
71
L1RCLK and L1TCLK width low (DSC=0)3
P+10
Ñ
P+10
Ñ
P+10
Ñ
ns
71a
L1RCLK and L1TCLK width high (DSC=0)2
P+10
Ñ
P+10
Ñ
P+10
Ñ
ns
72
L1TXD, L1ST(1Ð8), L1RQ, L1CLKO rise and fall
times
Ñ
15
Ñ
15
Ñ
15
ns
73
L1RSYNC, L1TSYNC valid to L1CLK edge
(SYNC setup time)
20
Ñ
20
Ñ
20
Ñ
ns
74
L1CLK edge to L1RSYNC and L1TSYNC invalid
(SYNC hold time)
35
Ñ
35
Ñ
35
Ñ
ns
75
L1RSYNC and L1TSYNC rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
76
L1RXD valid to L1CLK edge (L1RXD setup time)
42
Ñ
42
Ñ
42
Ñ
ns
77
L1CLK edge to L1RXD invalid (L1RXD hold time)
35
Ñ
35
Ñ
35
Ñ
ns
78
L1CLK edge to L1ST(1Ð8) valid
10
45
10
45
10
45
ns
78a
L1SYNC valid to L1ST(1Ð8) valid4
10
45
10
45
10
45
ns
79
L1CLK edge to L1ST(1Ð8) invalid
10
45
10
45
10
45
ns
80
L1CLK edge to L1TXD valid
10
65
10
65
10
65
ns
80a
L1TSYNC valid to L1TXD valid4
10
65
10
65
10
65
ns
81
L1CLK edge to L1TXD high impedance
0
42
0
42
0
42
ns
82
L1RCLK and L1TCLK frequency (DSC=1)
Ñ
12.5
Ñ
16
Ñ
16
MHz
83
L1RCLK and L1TCLK width low (DSC=1)
P+10
Ñ
P+10
Ñ
P+10
Ñ
ns
83a
L1RCLK and L1TCLK width high (DSC=1)2
P+10
Ñ
P+10
Ñ
P+10
Ñ
ns
84
L1CLK edge to L1CLKO valid (DSC=1)
Ñ
30
Ñ
30
Ñ
30
ns
85
L1RQ valid before falling edge of L1TSYNC3
1
Ñ
1
Ñ
1
Ñ
L1TCLK
86
L1GR setup time3
42
Ñ
42
Ñ
42
Ñ
ns
87
L1GR hold time3
42
Ñ
42
Ñ
42
Ñ
ns
88
L1CLK edge to L1SYNC valid
(FSD = 00, CNT = 0000, BYT = 0, DSC=0)
Ñ
0
Ñ
0
Ñ
0
ns
NOTES:
1.
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2.
Where P=1/CLKO1. For a 25MHz CLKO1 rate, P=40ns.
3.
These electrical speciÞcations are only valid for IDL mode.
4.
The strobes and TXD2 on the Þrst bit of the frame becomes valid after L1CLK edge or L1SYNC, whichever
is later.
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Freescale Semiconductor, Inc.
70
71
L1RCLK
(FE=0, CE=0)
(INPUT)
72
L1RCLK
(FE=1, CE=1)
(INPUT)
75
RFCD=1
Freescale Semiconductor, Inc...
L1RSYNC
(INPUT)
77
73
74
L1RXD
(INPUT)
BIT0
76
L1ST(1-4)
(OUTPUT)
78
79
Figure 44. Serial Interface Receive Timing Diagram With Normal Clocking (DSC =0)
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Freescale Semiconductor, Inc.
70
71
L1TCLK
(FE=0, CE=0)
(INPUT)
72
L1TCLK
(FE=1, CE=1)
(INPUT)
73
75
Freescale Semiconductor, Inc...
L1TSYNC
(INPUT)
74
TFCD=0
81
80a
L1TXD
(OUTPUT)
BIT0
80
79
78a
L1ST(1-4)
(OUTPUT)
78
Figure 45. Serial Interface Transmit Timing Diagram
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Freescale Semiconductor, Inc.
Table 13. Serial Communication Controller in NMSI External Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
100
RCLK1 and TCLK1 width high1
CLKOUT
F
Ñ
CLKOUT
F
Ñ
CLKOUT
F
Ñ
MHz
101
RCLK1 and TCLK1 width low
CLKOUT
+5ns
Ñ
CLKOUT
+5ns
Ñ
CLKOUT
+5ns
Ñ
ns
102
RCLK1 and TCLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
103
TXD2 active delay (from TCLK1 falling
edge)
0
50
0
50
0
50
ns
104
RTS1 active/inactive delay (from TCLK1
falling edge)
0
50
0
50
0
50
ns
105
CTS1 setup time to TCLK1 rising edge
5
Ñ
5
Ñ
5
Ñ
ns
106
RXD2 setup time to RCLK1 rising edge
5
Ñ
5
Ñ
5
Ñ
ns
107
RXD2 hold time from RCLK1 rising
edge2
5
Ñ
5
Ñ
5
Ñ
ns
108
CD1 setup time to RCLK1 rising edge
5
Ñ
5
Ñ
5
Ñ
ns
NOTES:
1.
The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2.
Applies to CD and CTS hold time when they are used as external sync signals.
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Table 14. Serial Communication Controller in NMSI Internal Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
100
RCLK1 and TCLK1 frequency1
0
8.3
0
13
0
16
MHz
102
RCLK1 and TCLK1 rise and all times
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
ns
103
TXD2 active delay (from TCLK1 falling
edge)
0
30
0
30
0
30
ns
104
RTS1 active/inactive delay (from TCLK1
falling edge)
0
30
0
30
0
30
ns
105
CTS1 setup time to TCLK1 rising edge
40
Ñ
40
Ñ
40
Ñ
ns
106
RXD2 setup time to RCLK1 rising edge
40
Ñ
40
Ñ
40
Ñ
ns
107
RXD2 hold time from RCLK1 rising edge2
0
Ñ
0
Ñ
0
Ñ
ns
108
CD1 setup time to RCLK1 rising edge
40
Ñ
40
Ñ
40
Ñ
ns
NOTES:
1.
The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1.
2.
Applies to CD and CTS hold time when they are used as external sync signals.
101
102
102
RCLK1
100
106
RXD2
(INPUT)
107
108
CD1
(INPUT)
107
CD1
(SYNC
INPUT)
Figure 46. SCC NMSI Receive Timing Diagram
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Freescale Semiconductor, Inc.
102
101
TCLK1
102
100
103
TXD2
(OUTPUT)
105
Freescale Semiconductor, Inc...
RTS1
(OUTPUT)
104
104
CTS1
(INPUT)
107
CTS1
(SYNC
INPUT)
Figure 47. SCC NMSI Transmit Timing Diagram
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Freescale Semiconductor, Inc.
102
101
TCLK1
100
102
103
TXD2
(OUTPUT)
104
Freescale Semiconductor, Inc...
RTS1
(OUTPUT)
107
105
104
CTS1
(ECHO
INPUT)
Figure 48. HDLC Bus Timing Diagram
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Freescale Semiconductor, Inc.
Table 15. Ethernet Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
120
CLSN (CTS2) width high
40
Ñ
40
Ñ
40
Ñ
ns
121
RCLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
122
RCLK1 width low
40
Ñ
40
Ñ
40
Ñ
ns
123
RCLK1 clock period1
80
120
80
120
80
120
ns
124
RXD2 setup time
20
Ñ
20
Ñ
20
Ñ
ns
125
RXD2 hold time
5
Ñ
5
Ñ
5
Ñ
ns
126
RENA (CD2) active delay (from RCLK1
rising edge of the last data bit)
10
Ñ
10
Ñ
10
Ñ
ns
127
RENA (CD2) width low
100
Ñ
100
Ñ
100
Ñ
ns
128
TCLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
129
TCLK1 width low
40
Ñ
40
Ñ
40
Ñ
ns
130
TCLK1 clock period1
99
101
99
101
99
101
ns
131
TXD2 active delay (from TCLK1 rising edge)
10
50
10
50
10
50
ns
132
TXD2 inactive delay (from TCLK1 rising
edge)
10
50
10
50
10
50
ns
133
TENA (RTS2) active delay (from TCLK1
rising edge)
10
50
10
50
10
50
ns
134
TENA (RTS2) inactive delay (from TCLK1
rising edge)
10
50
10
50
10
50
ns
135
N/A
136
N/A
137
N/A
138
CLKx low to SDACK asserted2
Ñ
20
Ñ
20
Ñ
20
ns
139
CLKx low to SDACK negated3
Ñ
20
Ñ
20
Ñ
20
ns
NOTES:
1.
The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2.
SDACK is asserted when the SDMA writes the incoming frame DA into memory.
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CLSN (CTS1)
(INPUT)
120
Figure 49. Ethernet Collision Timing Diagram
121
Freescale Semiconductor, Inc...
121
RCLK1
124
123
RXD2
(INPUT)
LAST BIT
125
127
RENA (CD1)
(INPUT)
126
Figure 50. Ethernet Receive Timing Diagram
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Freescale Semiconductor, Inc.
128
128
129
TCLK1
121
131
132
TXD2
(OUTPUT)
134
133
Freescale Semiconductor, Inc...
TENA (RTS1)
(INPUT)
RENA (CD1)
(INPUT)
(NOTE 2)
NOTES: 1. TRANSMIT CLOCK INVERT (TCI) BIT IN THE GSMR IS SET.
2. IF RENA IS DEASSERTED BEFORE TENA, OR RENA IS NOT ASSERTED AT ALL DURING
TRANSMIT, THEN THE CSL BIT IS SET IN THE BUFFER DESCRIPTOR AT THE END OF FRAME TRANSMISSION.
Figure 51. Ethernet Transmit Timing Diagram
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Table 16. Serial Peripheral Interface Master Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
160
Master cycle time
4
1,024
4
1,024
4
1,024
tcyc
161
Master clock (SCK) high or low time
2
512
2
512
2
512
tcyc
162
Master data setup time (inputs)
50
Ñ
50
Ñ
50
Ñ
ns
163
Master data hold time (inputs)
0
Ñ
0
Ñ
0
Ñ
ns
164
Master data valid (after SCK edge)
Ñ
20
Ñ
20
Ñ
20
ns
165
Master data hold time (outputs)
0
Ñ
0
Ñ
0
Ñ
ns
166
Rise time output
Ñ
15
Ñ
15
Ñ
15
ns
167
Fall time output
Ñ
15
Ñ
15
Ñ
15
ns
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
160
161
166
167
161
SPICLK
CI=0
(OUTPUT)
167
163
SPICLK
CI=1
(OUTPUT)
166
162
SPIMISO
(INPUT)
DATA
MSB IN
LSB IN
MSB IN
164
165
SPIMOSI
(OUTPUT)
MSB OUT
DATA
LSB OUT
MSB OUT
166
167
Figure 52. SPI Master (CP=0) Timing Diagram
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Freescale Semiconductor, Inc.
160
161
166
167
161
SPICLK
CI=0
(OUTPUT)
163
167
SPICLK
CI=1
(OUTPUT)
166
Freescale Semiconductor, Inc...
162
SPIMISO
(INPUT)
MSB IN
DATA
LSB IN
MSB IN
164
165
SPIMOSI
(OUTPUT)
MSB OUT
DATA
LSB OUT
167
MSB OUT
166
Figure 53. SPI Master (CP=1) Timing Diagram
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Freescale Semiconductor, Inc.
Table 17. Serial Peripheral Interface Slave Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
170
Slave cycle time
2
Ñ
2
Ñ
2
Ñ
tcyc
171
Slave enable lead time
15
Ñ
15
Ñ
15
Ñ
ns
172
Slave enable lag time
15
Ñ
15
Ñ
15
Ñ
ns
173
Slave clock (SPICLK) high or low time
1
Ñ
1
Ñ
1
Ñ
tcyc
174
Slave sequential transfer delay (does not
require deselect)
1
Ñ
1
Ñ
1
Ñ
tcyc
175
Slave data setup time (inputs)
20
Ñ
20
Ñ
20
Ñ
ns
176
Slave data hold time (inputs)
20
Ñ
20
Ñ
20
Ñ
ns
177
Slave access time
Ñ
50
Ñ
50
Ñ
50
ns
178
Slave SPI MISO disable time
Ñ
50
Ñ
50
Ñ
50
ns
179
Slave data valid (after SPICLK edge)
Ñ
50
Ñ
50
Ñ
50
ns
180
Slave data hold time (outputs)
0
Ñ
0
Ñ
0
Ñ
ns
181
Rise time (input)
Ñ
15
Ñ
15
Ñ
15
ns
182
Fall time (input)
Ñ
15
Ñ
15
Ñ
15
ns
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Freescale Semiconductor, Inc.
171
172
SPISEL
(INPUT)
170
173
174
181
182
173
SPICLK
CI=0
(INPUT)
Freescale Semiconductor, Inc...
SPICLK
CI=1
(INPUT)
177
178
181
182
180
SPIMISO
(OUTPUT)
MSB OUT
DATA
175
LSB OUT
UNDEF
MSB OUT
179
176
SPIMOSI
(INPUT)
MSB IN
DATA
182
LSB IN
181
Figure 54. SPI Slave (CP=0) Timing Diagram
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MSB IN
Freescale Semiconductor, Inc.
172
SPISEL
(INPUT)
170
173
174
182
173
SPICLK
CI=0
(INPUT)
181
171
181
Freescale Semiconductor, Inc...
SPICLK
CI=1
(INPUT)
182
177
SPIMISO
(OUTPUT)
178
180
UNDEF
MSB OUT
DATA
LSB OUT
DATA
LSB IN
MSB OUT
179
175
176
SPIMOSI
(INPUT)
MSB IN
182
MSB IN
181
Figure 55. SPI Slave (CP=1) Timing Diagram
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Table 18. I2C TimingÑSCL < 100 kHz
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
0
100
0
100
0
100
kHz
200
SCL clock frequency (slave)
200
SCL clock frequency (master)
1.5
100
1.5
100
1.5
100
kHz
202
Bus free time between transmissions
4.7
Ñ
4.7
Ñ
4.7
Ñ
ms
203
Low period of SCL
4.7
Ñ
4.7
Ñ
4.7
Ñ
ms
204
High period of SCL
4.0
Ñ
4.0
Ñ
4.0
Ñ
ms
205
Start condition setup time
4.7
Ñ
4.7
Ñ
4.7
Ñ
ms
206
Start condition hold time
4.0
Ñ
4.0
Ñ
4.0
Ñ
ms
207
Data hold time
0
Ñ
0
Ñ
0
Ñ
ms
208
Data setup time
250
Ñ
250
Ñ
250
Ñ
ns
209
SDL/SCL rise time
Ñ
1
Ñ
1
Ñ
1
ms
210
SDL/SCL fall time
Ñ
300
Ñ
300
Ñ
300
ns
211
STOP condition setup time
4.7
Ñ
4.7
Ñ
4.7
Ñ
ms
NOTE: SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) * pre_scaler * 2 ).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
Table 19. I2C TimingÑSCL > 100 kHz
NUM
CHARACTERISTIC
MINIMUM
MAXIMUM
UNIT
0
BRGCLK/48
Hz
BRGCLK/16512
BRGCLK/48
Hz
200
SCL clock frequency (slave)
200
SCL clock frequency (master)
202
Bus free time between transmissions
1/(2.2 * fSCL)
Ñ
sec
203
Low period of SCL
1/(2.2 * fSCL)
Ñ
sec
204
High period of SCL
1/(2.2 * fSCL)
Ñ
sec
205
Start condition setup time
1/(2.2 * fSCL)
Ñ
sec
206
Start condition hold time
1/(2.2 * fSCL)
Ñ
sec
207
Data hold time
0
Ñ
sec
208
Data setup time
1/(40 * fSCL)
Ñ
sec
209
SDL/SCL rise time
Ñ
1/(10 * fSCL)
sec
210
SDL/SCL fall time
Ñ
1/(33 * fSCL)
sec
211
Stop condition setup time
1/(2.2 * fSCL)
Ñ
sec
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SDA
202
203
204
207
205
208
SCL
209
210
211
Freescale Semiconductor, Inc...
206
Figure 56. I2C Bus Timing Diagram
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Table 20. Serial Management Controller Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
150
CLK1 clock period
100
Ñ
100
Ñ
100
Ñ
ns
151
CLK1 width low
50
Ñ
50
Ñ
50
Ñ
ns
151A
CLK1 width high
50
Ñ
50
Ñ
50
Ñ
ns
152
CLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
153
SMTXDx active delay (from CLK1 falling
edge)
10
50
10
50
10
50
ns
154
SMRXDx/SYNC1 setup time
20
Ñ
20
Ñ
20
Ñ
ns
155
SMRXDx/SYNC1 hold time
5
Ñ
5
Ñ
5
Ñ
ns
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
152
152
151
161a
SMCLK
150
SMTXDX
(OUTPUT)
154
*
153
155
SYNC1
154
155
SMRXDX
(INPUT)
NOTE: * THIS DELAY IS EQUAL TO AN INTEGER NUMBER OF ÒCHARACTER LENGTHÓ CLOCKS.
Figure 57. SMC Transparent Timing Diagram
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Table 21. LCD Controller Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
220
Shift clock cycle time
40
Ñ
40
Ñ
40
Ñ
nsec
221
Shift clock high time
20
Ñ
20
Ñ
20
Ñ
nsec
223
CLOCK/HSYNC/VSYNC/OE rise and fall
times
Ñ
10
Ñ
10
Ñ
10
nsec
224
Data valid delay from shift clock high
Ñ
15
Ñ
15
Ñ
15
nsec
225
VSYNC to HSYNC setup time1
5
Ñ
5
Ñ
5
Ñ
T
226
VSYNC hold time
1
Ñ
1
Ñ
1
Ñ
T
227
HSYNC pulse width
4
Ñ
4
Ñ
4
Ñ
T
228
Time from clock falling edge to HSYNC
rising edge
4.5
Ñ
4.5
Ñ
4.5
Ñ
T
229
Time from HSYNC falling edge to clock
rising edge2
4
Ñ
4
Ñ
4
Ñ
T
230
AC active delay
Ñ
25
Ñ
25
Ñ
25
nsec
231
VSYNC pulse width (TFT)
1
16
1
16
1
16
Line
232
HSYNC to OE delay3
4
Ñ
4
Ñ
4
Ñ
T
233
OE to HSYNC delay
4
Ñ
4
Ñ
4
Ñ
T
234
VSYNC to OE delay (TFT)
0
1,023
0
1,023
0
1,023
T
235
VSYNC/HSYNC/OE active delay (TFT)
Ñ
15
Ñ
15
Ñ
15
nsec
236
Wait between frames4
WBF
Ñ
WBF
Ñ
WBF
Ñ
Line
NOTES:
1.
T = shift clock cycle (220).
2.
This number is given for wbl(wait between lines) £ 2. For wbl=n {n>2} the timing will be (n+2)T.
3.
This number is given for wbl(wait between lines) £ 2. For wbl=n {n>2} the timing will be (n+2)T.
4.
Wait Between Frames (WBF) is a programmable parameter.
Tcyc is the cycle time of the LCD clock (shift clock). Tdelay is a circuit delay that is specified in
the AC electrical specifications. 1Ð16 lines is a time period that can vary between one scan line
and 16, depending on how the LCD controller is programmed in the VPW field of the LCVCR.
0Ð1,023 lines is a time period that can vary between 0 and 1,023 scan lines in the WBF field of
the LCVCR.
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220
223
221
223
224
SHIFT CLOCK
DATA
228
227
229
Freescale Semiconductor, Inc...
225
SHIFT CLOCK
226
HSYNC
VSYNC
LCD_AC
230
NTH LINE
236
FIRST LINE
SECOND LINE
VSYNC
HSYNC
SHIFT CLOCK
Figure 58. Passive Panel Timing Diagram
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233
227
235
224
SHIFT
DATA
Freescale Semiconductor, Inc...
235
OE
232
231
234
HSYNC
VSYNC
225
OE
NTH LINE
235
FIRST LINE
VSYNC
HSYNC
OE
Figure 59. TFT Panel Timing Diagram
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Table 22. Video Controller Timing
25MHZ
Freescale Semiconductor, Inc...
NUM
40MHZ
50MHZ
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
240
Clock cycle time
32
Ñ
32
Ñ
32
Ñ
nsec
241
Clock high time
13
Ñ
13
Ñ
13
Ñ
nsec
242
CLK/HSYNC/VSYNC/BLANK/FIELD
rise and fall times
Ñ
10
Ñ
10
Ñ
10
nsec
243
Clock high to data valid
10
25
10
25
10
25
nsec
242
240
242
243
241
CLK
DATA
HSYNC
VSYNC
FIELD
BLANK
Figure 60. Video Controller Timing
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Freescale Semiconductor, Inc.
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