ICHAUS IC-LNB 18-bit opto encoder with spi and ser/par interface Datasheet

preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 1/35
FEATURES
APPLICATIONS
♦ System-on-chip design for excellent reliability
♦ Leading/trailing sampling of 10 binary tracks pitched at 400 µm
♦ Analog sine/cosine scanning with enlarged photodiodes,
signal conditioning and fast 8-bit vector-tracking interpolation
♦ Absolute singleturn resolution of up to 18 bit
♦ Unique FlexCount® circuit: freely selectable resolution for
absolute and incremental data
♦ Incremental quadrature outputs with 1 to 65,536 CPR and
programmable index signal
♦ LED illumination control by 50 mA high-side current source
(sin2 +cos2 or sum control modes)
♦ Alarm indication for configuration or illumination error
♦ Permanent RAM monitoring by parity bits
♦ 3.3 V-compatible SPI and I/O ports for configuration and data
♦ Serial data readout in 1 µs cycles at 16 MHz clock frequency
♦ Parallel position data output for 16 bit
♦ Operation at 4 V to 5.5 V within -40 °C to 110 °C
♦ 30-pin optoBGA or 38-pin optoQFN package for SMT
♦ Illumination: iC-SN85 BLCC SN1C (850 nm encoder LED)
♦ Code discs: LNB1S 42-1024 (1024 PPR, ∅ 42 mm/18 mm),
LNB4S 26-1024 (1024 PPR, ∅ 26.0 mm/9.6 mm)
♦
♦
♦
♦
Optical position sensors
Linear scales
Absolute rotary encoders
Programmable incremental
encoders
♦ Motor feedback systems
PACKAGES
30-pin optoBGA
7.6 mm x 7.1 mm x 1.6 mm
38-pin optoQFN
7.0 mm x 5.0 mm x 0.9 mm
BLOCK DIAGRAM
+3 V ... 5.5 V
C1
+4 V ... 5.5 V
VDDA
VDD
iC-LNB
GND
SCK
LED
LED Control
sin2+cos2, sum
MOSI
MISO
C2
GNDA
ERR
Error
D1
SPI
LED
iC-SN85
CS
Calibration
R1
R2
PSIN
DIR
Cosine
NSL
NSIN
Sine
P
DIN
SER
DOUT
N
PCOS
NCOS
CLK
INCA
INCB
INC
sin
dig
GA
XJD
Copyright © 2013 iC-Haus
TPC
TNC
INCZ
GB
Interpolation
6/7/8 bit
TNS
PAR
P0...15
TPS
Power-On
POK
http://www.ichaus.com
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 2/35
DESCRIPTION
iC-LNB is an optoelectronic encoder IC for absolute
linear and angle measuring systems, such as glass
scales and encoders. Photodiodes, amplifiers, and
comparators, the entire signal conditioning unit, and
interfaces for position data output have been monolithically integrated into the device.
An integrated LED current control with a driver stage
allows a transmitting LED to be directly connected
(e.g. iC-SN85). The optical receive power is kept
constant by the control unit, regardless of temperature and aging effects. The receive power setpoint
can be programmed. Should the LED current control
exceed its operating range, this is indicated at the error message output (end-of-life alarm at pin ERR).
The photocurrent offset and photocurrent amplitude
of the analog sine/cosine signals can be calibrated.
These calibrated voltage signals are lead out to pins
PSIN, NSIN, PCOS, and NCOS and are used by the
integrated 8-bit vector-tracking interpolation circuit.
iC-LNB synchronizes the interpolator and singleturn
data to form a contiguous Gray-coded position data
word. 16 parallel ports, a scalable shift-register, the
SPI interface, as well as incremental A/B/Z signals
are available for data output. By help of the unique
’FlexCount’ circuit any angle resolution between 4 to
218 angle steps per revolution can be preset for the
incremental signals and the absolute position value.
After startup iC-LNB is configured using the SPI interface. To make connection to a 3.3 V microcontroller
easier, all digital I/O ports, including the SPI, can be
run on 3.3 V.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 3/35
CONTENTS
PACKAGING INFORMATION
PIN CONFIGURATION
oBGA LNB2C
(7.6 mm x 7.1 mm x 1.6 mm) . . . .
PIN CONFIGURATION
oQFN38-7x5
(7.0 mm x 5.0 mm x 0.9 mm)
(in qualification) . . . . . . . . . . .
PAD LAYOUT . . . . . . . . . . . . . .
PACKAGE DIMENSIONS oQFN38-7x5
4
Radial adjustment to code disc . . . . . . . .
SIGNAL CONDITIONING
. . .
. . .
. . .
. . .
4
5
6
7
ABSOLUTE MAXIMUM RATINGS
8
THERMAL DATA
8
ELECTRICAL CHARACTERISTICS
24
25
Gain . . . . . . . . . . . . . . . . . . . . . . .
25
Sine calibration . . . . . . . . . . . . . . . . .
25
Cosine calibration . . . . . . . . . . . . . . .
25
Square control . . . . . . . . . . . . . . . . .
26
LED POWER CONTROL
Error monitoring . . . . . . . . . . . . . . . .
INTERPOLATOR
27
27
27
Interpolator resolution . . . . . . . . . . . . .
27
Interpolator filter . . . . . . . . . . . . . . . .
27
9
FLEXCOUNT®
OPERATING CONDITIONS: SPI Interface
14
OPERATING CONDITIONS: Shift Register
15
28
Enable/disable . . . . . . . . . . . . . . . . .
28
Resolution . . . . . . . . . . . . . . . . . . . .
28
Reset . . . . . . . . . . . . . . . . . . . . . .
28
Hysteresis . . . . . . . . . . . . . . . . . . . .
29
CONFIGURATION PARAMETERS
16
PROGRAMMING iC-LNB
Address range . . . . . . . . .
RAM monitoring (parity check)
Reset values . . . . . . . . . .
Programming sequence . . . .
17
17
17
18
18
INCREMENTAL OUTPUT
OPERATING MODES
19
SHIFT REGISTER OUTPUT
30
SPI INTERFACE
General protocol description . . . . . . . . .
OPCODE description . . . . . . . . . . . . .
20
20
20
PARALLEL ENCODER MODE
31
ALARM OUTPUT
32
GRAY-CODE OUTPUTS
23
OSCILLATOR
32
ADJUSTMENT
Tilt angle . . . . . . . . . . . . . . . . . . . .
Example: LNB1S 42-1024 . . . . . . . . . . .
23
23
23
TEST FUNCTIONS
33
DESIGN REVIEW: Notes On Chip Functions
34
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.
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.
.
.
.
.
.
Incremental outputs . . . . . . . . . . . . . .
29
Position offset . . . . . . . . . . . . . . . . . .
29
30
Selecting the output . . . . . . . . . . . . . .
30
Tristate . . . . . . . . . . . . . . . . . . . . .
30
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 4/35
PACKAGING INFORMATION
PIN CONFIGURATION
oBGA LNB2C
(7.6 mm x 7.1 mm x 1.6 mm)
1
2
3
4
5
6
A
B
C
D
E
PIN FUNCTIONS
No. Name Function
A1 SCK SPI Clock Input
A2 VDD + 3 V ... +5.5 V I/O Ports Supply Voltage
A3 GND I/O Ports Ground
A4 LED LED Highside Current Source
A5 VDDA + 4 V ... +5.5 V Supply Voltage
A6 GNDA Ground
B1 CS
SPI Chip Select Input
B2 MISO SPI Data Output
B3 MOSI SPI Data Input
B4 PCOS Analog Voltage Output PCOS
B5 NSIN Analog Voltage Output NSIN
B6 PSIN Analog Voltage Output PSIN
PIN FUNCTIONS
No. Name Function
C1 DIR
Code Inversion Input /
Parallel Output Bit 13
C2 TNS Test Input NSIN /
Parallel Output Bit 14
C3 TNC Test Input NCOS /
Parallel Output Bit 15
C4 TPS
Test Input PSIN /
Parallel Output Bit 1
C5 TPC Test Input PCOS /
Parallel Output Bit 0
C6 NCOS Analog Voltage Output NCOS
D1 DOUT Shift Register Data Output /
Parallel Output Bit 10
D2 DIN
Shift Register Data Input /
Parallel Output Bit 11
D3 NSL
Shift Register Load Input (low active) /
Parallel Output Bit 12
D4 INCB Incremental Output B /
Parallel Output Bit 3
D5 INCA Incremental Output A /
Parallel Output Bit 2
D6 ERR Error Message Output (high active)
E1 GB
Gray-code Output B (MSB-1) /
Parallel Output Bit 7
E2 GA
Gray-code Output A (MSB) /
Parallel Output Bit 8
E3 CLK
Shift Register Clock Input /
Parallel Output Bit 9
E4 XJD
Adjustment Signal /
Parallel Output Bit 6
E5 POK Power Ok Indication/
Parallel Output Bit 5
E6 INCZ Incremental Output Z /
Parallel Output Bit 4
Wiring unused input pins can be recommended, especially for pins DIR, TPS, TNS, TPC, TNC (e.g. via 10 kΩ to
GNDA).
For dimensional specifications refer to the package datasheet iC-LNB oBGA LNB2C, available separately.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 5/35
PIN CONFIGURATION
oQFN38-7x5 (7.0 mm x 5.0 mm x 0.9 mm)
(in qualification)
38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19
PIN FUNCTIONS
No. Name Function
1 GNDA Ground
2-6 n.c.
7 GND I/O Ports Ground
8 VDD + 3 V ... +5.5 V I/O Ports Supply Voltage
9 SCK SPI Clock Input
10 MOSI SPI Data Input
11 MISO SPI Data Output
12 CS
SPI Chip Select Input
13 TNC Test Input NCOS /
Parallel Output Bit 15
14 TNS Test Input NSIN /
Parallel Output Bit 14
15 DIR
Code Inversion Input /
Parallel Output Bit 13
PIN FUNCTIONS
No.
Name Function
16 NSL
Shift Register Load Input (low active) /
Parallel Output Bit 12
17 DIN
Shift Register Data Input /
Parallel Output Bit 11
18 DOUT Shift Register Data Output /
Parallel Output Bit 10
19 CLK
Shift Register Clock Input /
Parallel Output Bit 9
20 GB
Gray-code Output B (MSB-1) /
Parallel Output Bit 7
21 GA
Gray-code Output A (MSB) /
Parallel Output Bit 8
22-24 n.c.
25 POK Power Ok Indication/
Parallel Output Bit 5
26 XJD
Adjustment Signal /
Parallel Output Bit 6
27 INCZ Incremental Output Z /
Parallel Output Bit 4
28 INCB Incremental Output B /
Parallel Output Bit 3
29 INCA Incremental Output A /
Parallel Output Bit 2
30 ERR Error Message Output (high active)
31 TPS
Test Input PSIN /
Parallel Output Bit 1
32 TPC Test Input PCOS /
Parallel Output Bit 0
33 NCOS Analog Voltage Output NCOS
34 PCOS Analog Voltage Output PCOS
35 NSIN Analog Voltage Output NSIN
36 PSIN Analog Voltage Output PSIN
37 LED
LED Highside Current Source
38 VDDA + 4 V ... +5.5 V Supply Voltage
n.c.
pin not connected
Wiring unused input pins can be recommended, especially for pins DIR, TPS, TNS, TPC, TNC (e.g. via 10 kΩ to
GNDA).
The thermal pad of the optoQFN package (bottom side) should be joined to an extended copper area which must
have GNDA potential.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 6/35
PAD LAYOUT
PAD FUNCTIONS
No. Name Function
1
2
3
4
5
6
7
3310
DA4V
DA4N
DA3V
DA3N
DA2V
DA2N
DA1VP
DA1NP
GND
VDD
SCK
MOSI
MISO
CS
TNC
8 TNS
9 DIR
200
DA1VN
DA1NN
10 NSL
80
300
500
250
DPSIN
DPCOS
DNCOS
DNSIN
11 DIN
80
5480
12 DOUT
40
13 CLK
350
200
DA5V
DA5N
14 GA
DA6V
DA6N
15 GB
DA7V
DA7N
16 XJD
DA8V
DA8N
17 POK
DA9V
DA9N
110
18 INCZ
110
19 INCB
DA10V
DA10N
20 INCA
1810
21 ERR
22 TPS
23 TPC
24
25
26
27
28
29
30
NCOS
PCOS
NSIN
PSIN
LED
VDDA
GNDA
I/O Ports Ground
+ 3 V ... +5.5 V I/O Ports Supply Voltage
SPI Clock Input
SPI Data Input
SPI Data Output
SPI Chip Select Input
Test Input NCOS /
Parallel Output Bit 15
Test Input NSIN /
Parallel Output Bit 14
Code Inversion Input /
Parallel Output Bit 13
Shift Register Load Input (low active) /
Parallel Output Bit 12
Shift Register Data Input /
Parallel Output Bit 11
Shift Register Data Output /
Parallel Output Bit 10
Shift Register Clock Input /
Parallel Output Bit 9
Gray-code Output A (MSB) /
Parallel Output Bit 8
Gray-code Output B (MSB-1) /
Parallel Output Bit 7
Adjustment Signal /
Parallel Output Bit 6
Power Ok Indication/
Parallel Output Bit 5
Incremental Output Z /
Parallel Output Bit 4
Incremental Output B /
Parallel Output Bit 3
Incremental Output A /
Parallel Output Bit 2
Error Message Output
Test Input PSIN /
Parallel Output Bit 1
Test Input PCOS /
Parallel Output Bit 0
Analog Voltage Output NCOS
Analog Voltage Output PCOS
Analog Voltage Output NSIN
Analog Voltage Output PSIN
LED Highside Current Source
+ 4 V ... +5.5 V Supply Voltage
Ground
Wiring unused input pads can be recommended, especially for pins DIR, TPS, TNS, TPC, TNC (e.g. via 10 kΩ
to GNDA).
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 7/35
PACKAGE DIMENSIONS oQFN38-7x5
RECOMMENDED PCB-FOOTPRINT
6.90
5.65
0.50
0.30
4.90
0.70
3.65
0.90 ±0.10
SIDE
15
R0.
BOTTOM
TOP
7
5.65
5.38
3.65
0.50
0.23
All dimensions given in mm. Tolerances of form and position according to JEDEC MO-220.
Positional tolerance of reticle pattern: ±90μm / ±1.5° (with respect to backside pad).
G4: radius of chip center (refer to the relevant encoder disc and code description).
Maximum molding excess +20μm / -75μm versus surface of glass/reticle.
0.40
5
1.93
G4
drc_lnb-oqfn38-1_pack_1, 8:1
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 8/35
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply permissible operating conditions; functional operation is not guaranteed.
Exceeding these ratings may damage the device.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VDDA
Voltage at VDDA
-0.3
6
V
G002 VDD
Voltage at VDD
-0.3
VDDA+0.3
V
G003 V(GND)
Voltage at GND
-0.3
0.3
V
G004 V()
Voltage at LED, PCOS, NCOS, PSIN,
NSIN, TPC, TNC, TPS, TNS
-0.3
VDDA+0.3
V
G005 V()
Voltage at INCA, INCB, INCZ, ERR,
DIR, CLK, DOUT, DIN, NSL, NCS,
MOSI, MISO, SCK, POK, XJD, GA, GB
-0.3
VDD+0.3
V
G006 I(VDDA)
Current in VDDA
-100
100
mA
G007 I(VDD)
Current in VDD
-50
50
mA
G008 I(GND)
Current in GND
-20
20
mA
G009 I(LED)
Current in LED
-100
20
mA
G010 I()
Current in INCA, INCB, INCZ, ERR,
DIR, CLK, DOUT, DIN, NSL, NCS,
MOSI, MISO, SCK, POK, XJD, GA,
GB, TPC, TNC, TPS, TNS
-35
35
mA
G011 I()
Current in PCOS, NCOS, PSIN, NSIN
-35
35
mA
G012 Vd()
ESD Susceptibility at all pins
2
kV
G013 Tj
Junction Temperature
-40
125
°C
G014 Ts
Chip Storage Temperature
-40
125
°C
HBM 100pF discharged through 1.5 kΩ
THERMAL DATA
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND
Item
No.
T01
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Ta
Operating Ambient Temperature Range packages oBGA LNB2C, oQFN38-7x5
-40
110
°C
T02
Ts
Permissible Storage Temperature
Range
packages oBGA LNB2C, oQFN38-7x5
-40
110
°C
T03
Tpk
Soldering Peak Temperature
package oBGA LSH2C
245
230
°C
°C
245
230
°C
°C
tpk < 20 s, convection reflow
tpk < 20 s, vapor phase soldering
TOL (time on label) 8 h;
Please refer to customer information file No. 7
for details.
T04
Tpk
Soldering Peak Temperature
package oQFN38-7x5
tpk < 20 s, convection reflow
tpk < 20 s, vapor phase soldering
MSL 5A (max. floor life 24 h at 30 °C and
60% RH);
Please refer to customer information file No. 7
for details.
All voltages are referenced to ground (GNDA) unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 9/35
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
4
5
5.5
3
5
5.5
Total Device
001
VDDA
Permissible Supply Voltage
002
VDD
Permissible I/O Supply Voltage
VDD ≤ VDDA
V
003
VDDA,
VDD
Permissible Supply Voltage Ripple
at 150 kHz
10
004
I(VDDA),
I(VDD)
Supply Current in VDDA and
VDD (sum)
without currents I(LED) and I(ERR), Tj = 27 °C
25
005
Vcz()hi
Clamp Voltage hi at all Pins
I() = 4 mA
006
Vc()hi
Clamp Voltage hi at
CLK, DIN, NSL, INCA, INCB,
INCZ, ERR, DIR, MISO, DOUT,
POK, XJD, GA, GB, TPS, TNS,
TPC, TNC
Vc()hi = V() − V(VDD),
I() = 4 mA
0.3
007
Vc()hi
Clamp Voltage hi at
CS, MOSI, SCK
Vc()hi = V() − V(VDD),
I() = 4 mA
1.2
2.2
V
008
Vc()lo
Clamp Voltage lo at all Pins
I() = -4 mA
-1.2
-0.3
V
400
V
mV
40
mA
11
V
1.2
V
Photodiodes
101
102
Se(λ)
Spectral Application Range
Se(λ) = 0.25 x S(λ)max
S(λ)max
Spectral Sensitivity
λ = 690 nm
λ = 850 nm
0.45
0.30
950
A/W
A/W
nm
103
Aph()
Radiant Sensitive Area DPSIN,
DNSIN, DPCOS, DNCOS
0.5 mm x 0.25 mm
0.125
mm²
104
Aph()
Radiant Sensitive Area Digital
0.35 mm x 0.2 mm
DA1VP, DA1VN, DA1NP, DA1NN,
DA2V ... DA10V, DA2N ... DA10N
0.07
mm²
Photocurrent Amplifier
201
Iph()
Permissible Photocurrent
Operating Range
0
202
Z()
Equivalent Transimpedance Gain Z() = Vout() / Iph()
1.8
203
∆Z()pn
Transimpedance Gain Matching
of an Amplifier Pair
P-channel versus corresponding N-channel
-0.2
204
fhc()
Upper Cut-off Frequency (-3 dB)
without LED current control
120
VR() =
Vcomp
VA1VP + VA1VN + VA1NP + VA1NN
3.0
300
200
nA
4.2
MΩ
0.2
%
500
kHz
25
mV
1
V
205
VR()
Ratio of Reference Voltage Digital Tracks (Vcomp) to Sum of
Digital Track 1
0.25
206
207
Hys()
Hysteresis Digital Tracks
GR()
Coarse Gain Range Analog Track GR = 0x00
GR = 0x01
GR = 0x02
GR = 0x03
208
Vref
Reference Voltage of Photocurrent Amplifiers
0.6
209
∆Vd()sc
Analog Track Dark Signal Voltage ∆Vd()sc = V() - Vref
versus Vref
-20
20
mV
210
∆Vd()dig
Digital Tracks Dark Signal Voltage versus Vref
-35
35
mV
0.5
LSB
5
∆Vd()dig = V() - Vref
15
1
1.33
1.6
2
0.8
Signal Conditioning Sin/Cos
301
Gmin
Adjustable Minimum Gain
GS, GC = 0x00
302
Gmax
Adjustable Maximum Gain
GS, GC = 0x3F
1
303
∆Gdiff
Differential Gain Calibration
Accuracy
calibration range 6 bit
304
Omin
Offset Calibration Min
OSP, OSN, OCP, OCN = 0x00
43
45
47
%VDDA
305
Omax
Offset Calibration Max
OSP, OSN, OCP, OCN = 0x7F
53
55
57
%VDDA
306
∆Odiff
Differential Offset Calibration
Accuracy
calibration range 7 bit
0.02
0.08
0.12
%VDDA
2
-0.5
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 10/35
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Output Voltage PSIN, NSIN, PCOS, NCOS
401
Vdc()
DC-Voltage at all Outputs
Offset adjusted to VDDAH
402
Vpk()
Permissible Signal Amplitude
DC level = VDDA/2
403
I()mx
Permissible Output Current
404
Ri()
Output Resistor
47
50
53
0.5
0.6
V
1
mA
200
Ω
-100
0
mA
-50
-1
mA
-1
I() = -1 . . . 1 mA
75
%VDDA
LED Power Control LED, Error Message ERR
501
Imx()
Permissible LED Current at LED
502
Iop()
LED Current Control Range
ERRS (internal) = 0, V(LED) > Vs(LED)
503
Vs()
Saturation Voltage at LED
Vs() = VDDA - V(LED); I() = -50 mA
504
tr()
Rise Time LED Current
I(LED): 0 % → 90 %
0.8
505
tset()
Settling Time of LED Control
Loop
amplitude at PSIN, NSIN, PCOS and NCOS
from 50 % to 100 % of setpoint
300
506
Vs()hi
Saturation Voltage hi at ERR
Vs()hi = VDD - V(ERR);
VDD = 3 . . . 4 V, I() = 1.5 mA
VDD = 4 . . . 5.5 V, I() = 2.5 mA
507
508
Isc()hi
Short-Circuit Current hi at ERR
Vs()lo
Saturation Voltage lo at ERR
509
Isc()lo
Short-Circuit Current lo at ERR
Interpolator
701 AAabs
702
703
AArel
AAhys
-100
VDD = 3 . . . 4 V, l() = 1.5 mA
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
Absolute Angular Position
Accuracy
referenced to a Sin/Cos signal period
RESIPO = 10 (6 bit interpolation)
RESIPO = 01 (7 bit interpolation)
RESIPO = 00 (8 bit interpolation)
Relative Angular Error
Angular Hysteresis
1
V
1.5
ms
µs
400
mV
-1.5
mA
400
mV
100
mA
2.8
1.4
0.7
DEG
DEG
DEG
referenced to output period T, see Figure 1
RESIPO = 10 (6 bit interpolation)
RESIPO = 01 (7 bit interpolation)
RESIPO = 00 (8 bit interpolation)
1
2
4
%
%
%
referenced to output period T, see Figure 1
RESIPO = 10 (6 bit interpolation)
RESIPO = 01 (7 bit interpolation)
RESIPO = 00 (8 bit interpolation)
2.8
1.4
0.7
DEG
DEG
DEG
704
tw()hi
Duty Cycle
referenced to output period T, see Figure 1
RESIPO 6= 11 (interpolation active)
50
%
705
tAB
Phase Shift A versus B
referenced to output period T, see Figure 1
RESIPO 6= 11 (interpolation active)
25
%
706
fmax
Maximum Permissible Sin/Cos
Frequency
RESIPO = 10 (6 bit interpolation)
RESIPO = 01 (7 bit interpolation)
RESIPO = 00 (8 bit interpolation)
foipo /64
foipo /128
foipo /256
kHz
kHz
kHz
FlexCount
801 AArel
Flex
Additional Relative Angular Error referenced to output period T, see Figure 1
all resolutions
of FlexCount
all binary resolutions
maximum resolution - 4
0
for RESIPO = 00 (8 bit interpolation):
RESSUB = 0x01387 (resolution 5 000)
RESSUB = 0x04E1F (resolution 20 000)
RESSUB = 0x09C3F (resolution 40 000)
RESSUB = 0x3FFFB (resolution 218 - 4)
802
803
tpFlex ()
Propagation Delay FlexCount
fmax
Maximum Permissible Sin/Cos
Frequency
25
0
25
%
%
%
0.48
1.92
3.85
25
%
%
%
%
1/foflex
RESIPO = 10 (6 bit interpolation)
RESIPO = 01 (7 bit interpolation)
RESIPO = 00 (8 bit interpolation)
foflex /64
foflex /128
foflex /256
kHz
kHz
kHz
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 11/35
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Incremental Outputs INCA, INCB, INCZ
901 Vs()hi
Saturation Voltage hi
Typ.
Vs()hi = VDD - V();
VDD = 3 . . . 4 V, I() = 1.5 mA
VDD = 4 . . . 5.5 V, I() = 2.5 mA
400
mV
-1.5
mA
400
mV
100
mA
902
903
Isc()hi
Short-Circuit Current hi
Vs()lo
Saturation Voltage lo
904
Isc()lo
Short-Circuit Current lo
905
tr()
Rise Time
CL = 30 pF, V(): 10% → 90% VDD
30
ns
906
tf()
Fall Time
CL = 30 pF, V(): 90% → 10% VDD
30
ns
Vs()hi = VDD - V();
VDD = 3 . . . 4 V, I() = 1.5 mA
VDD = 4 . . . 5.5 V, I() = 2.5 mA
400
mV
-1.5
mA
400
mV
SPI Interface SCK, CS, MISO, MOSI
A01 Vs()hi
Saturation Voltage hi at MISO
-100
Max.
VDD = 3 . . . 4 V, l() = 1.5 mA
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
A02
A03
Isc()hi
Short-Circuit Current hi at MISO
Vs()lo
Saturation Voltage lo at MISO
-100
A04
Isc()lo
Short-Circuit Current lo at MISO
100
mA
A05
fin()
Permissible Clock Frequency at
SCK
10
MHz
A06
Vt()hi
Threshold Voltage hi at SCK, CS,
MOSI
2
V
A07
Vt()lo
Threshold Voltage lo at SCK, CS,
MOSI
A08
A09
Vt()hys
Hysteresis at SCK, CS, MOSI
Vt()hys = Vt()hi - Vt()lo
Ipu()
Pull-Up Current at SCK, MOSI
V() = 0 . . . VDD - 1 V;
VDD = 3 . . . 4 V
VDD = 4 . . . 5.5 V
VDD = 3 . . . 4 V, l() = 1.5 mA
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
0.8
A10
Vpu()
Pull-Up Voltage at SCK, MOSI
Vpu() = VDD - V();
VDD = 3 . . . 4 V, I() = -3 µA
VDD = 4 . . . 5.5 V, I() = -5 µA
A11
Ipd()
Pull-Down Current at CS
V() = 1 V . . . VDD;
VDD = 3 . . . 4 V
VDD = 4 . . . 5.5 V
V
40
100
-65
-120
-25
-60
5
8
25
60
mV
-5
-10
µA
µA
400
mV
80
150
µA
µA
400
mV
A12
Vpd()
Pull-Down Voltage at CS
VDD = 3 . . . 4 V, I() = 3 µA
VDD = 4 . . . 5.5 V, I() = 5 µA
A13
tp1()
Propagation Delay: MISO hi
after Falling Edge CS
see Figure 2
30
ns
A14
tp2()
Propagation Delay: MISO Stable see Figure 2
after Clock Edge SCK
30
ns
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 12/35
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Shift Register CLK, NSL, DOUT, DIN
B01 Vs()hi
Saturation Voltage hi at DOUT
Typ.
Vs()hi = VDD - V();
VDD = 3 . . . 4 V, I() = 1.5 mA
VDD = 4 . . . 5.5 V, I() = 2.5 mA
-100
Max.
400
mV
-1.5
mA
400
mV
100
mA
B02
B03
Isc()hi
Short-Circuit Current hi at DOUT
Vs()lo
Saturation Voltage lo at DOUT
B04
Isc()lo
Short-Circuit Current lo at DOUT
B05
fin()
Permissible Clock Frequency at
CLK
16
MHz
B06
Vt()hi
Threshold Voltage hi at CLK,
NSL, DIN
2
V
B07
Vt()lo
Threshold Voltage lo at CLK,
NSL, DIN
B08
B09
Vt()hys
Hysteresis at CLK, NSL, DIN
Vt()hys = Vt()hi - Vt()lo
Ipu()
Pull-Up Current at CLK, NSL
V() = 0 . . . VDD - 1 V;
VDD = 3 . . . 4 V
VDD = 4 . . . 5.5 V
VDD = 3 . . . 4 V, l() = 1.5 mA
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
0.8
B10
Vpu()
Pull-Up Voltage at CLK, NSL
Vpu() = VDD - V();
VDD = 3 . . . 4 V, I() = -3 µA
VDD = 4 . . . 5.5 V, I() = -5 µA
B11
Ipd()
Pull-Down Current at DIN
V() = 1 V . . . VDD;
VDD = 3 . . . 4 V
VDD = 4 . . . 5.5 V
V
40
100
-65
-120
-25
-60
5
8
25
60
mV
-5
-10
µA
µA
400
mV
80
150
µA
µA
400
mV
B12
Vpd()
Pull-Down Voltage at DIN
VDD = 3 . . . 4 V, I() = 3 µA
VDD = 4 . . . 5.5 V, I() = 5 µA
B13
tp3()
Propagation Delay: DOUT Idle
State after Falling Edge NSL
see Figure 3
20
ns
B14
tp4()
Propagation Delay: DOUT stable see Figure 3
after Clock Edge CLK
20
ns
Parallel Outputs Bit 0 . . . 15 (parameter EPG = 0x1)
Pins: TNC, TNS, DIR, NSL, DIN, DOUT, CLK, GA, GB, XJD, POK, INCZ, INCB, INCA, TPS, TPC
C01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V();
VDD = 3 . . . 4 V, I() = 1.5 mA,
VDD = 4 . . . 5.5 V, I() = 2.5 mA
mV
-1.5
mA
400
mV
C02 Isc()hi
C03 Vs()lo
Short-Circuit Current hi
C04 Isc()lo
Short-Circuit Current lo
100
mA
C05 tr()
Rise Time
CL = 30 pF, V(): 10% → 90% VDD
30
ns
C06 tf()
Fall Time
CL = 30 pF, V(): 90% → 10% VDD
30
ns
Vs()hi = VDD - V();
VDD = 3 . . . 4 V, I() = 1.5 mA,
VDD = 4 . . . 5.5 V, I() = 2.5 mA
400
mV
-1.5
mA
400
mV
Saturation Voltage lo
Power-On-Reset POK
D01 Vs()hi
Saturation Voltage hi
-100
400
VDD = 3 . . . 4 V, l() = 1.5 mA,
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
D02 Isc()hi
D03 Vs()lo
Short-Circuit Current hi
D04 Isc()lo
D05 VDDAon
Short-Circuit Current lo
100
mA
Turn-on Threshold VDDA,
Power-on-release
increasing voltage at VDDA;
POK: lo → hi
3.6
3.8
4.0
V
D06 VDDAoff
Turn-off Threshold VDDA,
Power-down-reset
decreasing voltage at VDDA;
EPG = 0, POK: hi → lo
3.3
3.5
3.7
V
D07 VDDAhys
Hysteresis
VDDAhys = VDDAon - VDDAoff
0.2
0.3
Saturation Voltage lo
-100
VDD = 3 . . . 4 V, l() = 1.5 mA,
VDD = 4 . . . 5.5 V, l() = 2.5 mA
1.5
V
Code Inversion Input DIR
E01
Vt()hi
Threshold Voltage hi
2
V
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 13/35
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
E02
Vt()lo
Threshold Voltage lo
E03
E04
Vt()hys
Hysteresis
Vt()hys = Vt()hi - Vt()lo
40
100
Ipd()
Pull-Down Current
V() = 1 V . . . VDD;
VDD = 3 . . . 4 V
VDD = 4 . . . 5.5 V
5
8
25
60
E05
Vpd()
Oscillator
F01 foipo
F02
foflex
Max.
0.8
Pull-Down Voltage
V
VDD = 3 . . . 4 V, I() = 3 µA
VDD = 4 . . . 5.5 V, I() = 5 µA
mV
80
150
µA
µA
400
mV
Interpolator Oscillator Frequency OSZC = 0x00
OSZC = 0x01
OSZC = 0x10
OSZC = 0x11
12.8
13.8
14.4
14.6
MHz
MHz
MHz
MHz
FlexCount Oscillator Frequency
12.8
13.8
14.4
14.6
MHz
MHz
MHz
MHz
OSZC = 0x00
OSZC = 0x01
OSZC = 0x10
OSZC = 0x11
tAB
twhi
AArel
AArel
T
Figure 1: Definition of relative angle error
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 14/35
OPERATING CONDITIONS: SPI Interface
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
I001 TSCK
Permissible Clock Period
I002 tCS
Setup Time:
CS hi before SCK hi → lo
I003 tp1
Propagation Delay:
MISO hi after CS hi → lo
I004 tIS
Setup Time:
MOSI stable before SCK lo → hi
50
ns
I005 tSI
Hold Time:
MOSI stable after SCK lo → hi
50
ns
I006 tp2
Propagation Delay:
MISO stable after clock edge SCK
I007 tCC
Wait Time:
between CS hi → lo and CS lo → hi
CS
tCS
tIS
see Elec. Char. No.: A05
Max.
1/fin()
50
ns
Elec. Char. No.: A13
tSI
Elec. Char. No.: A14
500
TSCK
tCC
SCK
MOSI
tp2
tp1
MISO
Figure 2: SPI timing
ns
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 15/35
OPERATING CONDITIONS: Shift Register
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
see Elec. Char. No.: B05
Max.
I101 TCLK
Permissible Clock Period
I102 tlo
Hold Time Load Signal:
NSL low before NSL edge lo → hi
1/fin()
I103 tp3
Propagation Delay:
DOUT (idle state) after NSL lo → hi
Elec. Char. No.: B13
I104 tp4
Propagation Delay:
DOUT stable after clock edge CLK
Elec. Char. No.: B14
I105 tIC
Setup Time:
DIN stable before CLK lo → hi
30
ns
I106 tCI
Hold Time:
DIN stable after CLK lo → hi
30
ns
I107 thi
Preparation Time:
NSL high before request of position
data (CLK hi → lo)
30
ns
30
ns
NSL
thi
tlo
CLK
TCLK
DOUT
tp4
tIC tCI
DIN
Figure 3: Shift register timing
tp3
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 16/35
CONFIGURATION PARAMETERS
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
EPG:
Operating mode
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20
OPCODE:
SPI instructions
RACTIVE:
Register communication activation
PACTIVE:
Sensor data channel activation
SVALID:
Sensor data channel valid indication
STATUS:
SPI status information
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 25
GR:
Gain range
GS:
SIN gain
OSP:
PSIN offset
OSN:
NSIN offset
GC:
COS gain
OCP:
PCOS offset
OCN:
NCOS offset
LED Power Control . . . . . . . . . . . . . . . . . . . . . . . . Page 27
LCMOD:
LED Power control mode
LCTYP:
LED Power control type
LCSET(5:0): LED Power control setpoint
Interpolator
RESIPO:
ENIPO:
NENF:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 27
Interpolator resolution
Interpolator enable
Interpolator filter
Incremental output . . . . . . . . . . . . . . . . . . . . . . . . Page 30
INC:
Incremental output options
TRIABZ:
Incremental output tristate
FlexCount® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 28
NENFLEX: Enable/Disable
SELABS:
Absolute output options
(SPI, SER, PAR)
RESSUB:
Resolution - 1
STOPFLEX: Stop/Reset FlexCount
POSOK:
Position valid
NOUTLO:
Setting FlexCount outputs to low
HYS:
Hysteresis
INVA:
Output inversion INCA
INVB:
Output inversion INCB
INVZ:
Output inversion INCZ
ZPOS:
Position offset (binary)
Z90:
Z pulse width
Shift Register Output . . . . . . . . . . . . . . . . . . . . . . Page 30
NGRAY:
Shift register output data format
RNF:
Shift register idle output
SRC:
Shift register length
DIR:
Code inversion
Parallel Encoder Mode . . . . . . . . . . . . . . . . . . . . .Page 31
EPG:
Operating mode
Alarm Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 32
ERRS:
LED range error (internal)
ERRP:
Parity error (internal)
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 32
OSZC:
Oscillator adjustment
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 33
TA:
Test modes
TMUX:
Test signal multiplexer
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 17/35
PROGRAMMING iC-LNB
REGISTER MAP (RAM)
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal calibration
0x00
P00
0
GS(5:0)
0x01
P01
LCMOD
GC(5:0)
0x02
P02
OSP(6:0)
0x03
P03
OSN(6:0)
0x04
P04
OCP(6:0)
0x05
P05
OCN(6:0)
LED power control
0x06
P06
LCTYP
LCSET(5:0)
Output configuration
0x07
P07
0x08
P08
NGRAY
DIR
EPG
INC(2:0)
OSZC(1:0)
GR(1:0)
RNF
SRC(2:0)
Test functions
0x09
P09
NENF
TA(1:0)
TMUX(3:0)
FlexCount
0x0A
P0A
0x0B
P0B
HYS(6:0)
0x0C
P0C
ZPOS(6:0)
0x0D
P0D
ZPOS(13:7)
0x0E
P0E
0x0F
P0F
RESSUB(6:0)
0x10
P10
RESSUB(13:7)
0x11
P11
INVA
INVB
INVZ
RESIPO(1:0)
TRIABZ
Z90
NOUTLO
STOPFLEX
ENIPO
0
0
0
SELABS
NENFLEX
HYS(7)
ZPOS(17:14)
RESSUB(17:14)
Status (read only)
0x12
0
0
ERRP
ERRS
POSOK
Table 6: Register layout
Address range
The addresses of iC-LNB available through the SPI interface range from addresses 0x00 to 0x12. As only
the lower five bits of the address byte are evaluated,
with addresses that are greater than 0x1F the device
returns to address range 0x00-0x12.
RAM monitoring (parity check)
The configuration registers in the internal RAM are
constantly monitored by a parity check. Bit 7 of each
address is the parity bit (P00-P11) and is supplemented to an even number of ones. The unused bits
are also monitored. A parity error (internal ERRP) is
signaled at pin ERR (see the alarm output section).
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 18/35
Reset values
After power-on the registers are initialized as follows:
Address
Reset
Value
Description
0x00-0x01
0xA0
Gain (GS, GC) = 1.408
LED control behaivor (LCMOD) = 0
0x02-0x05
0xC0
Offset (OSP, OSN, OCP, OCN) =
0.5004*VDDA
0x06
0x60
LED control mode (LCTYP) = sum
control, Set point (LCSET) = 0.23 V
0x07
0x09
Shift register output format
(NGRAY) = GRAY,
Direction (DIR) = CW,
EPG = interface mode,
Oscillator (OSZC) = 14.4MHz,
Gain range (GR) = 1.33
0x08
0x18
Interpolator factor (INC) = x2,
Idle state DOUT (RNF) = ’1’,
Shift register (SRC) = 18 bit
0x09-0x0A
0x00
Test functions = 0,
Hysteresis (HYS) = 0°
0x0B
0x8E
ABZ outputs (INVA/B/Z) = not
inverted,
ABZ outputs (TRIABZ) = tri-state,
Shift register (SELABS) = max.
resolution,
FlexCount (NENFLEX) = disabled
0x0C-0x10
0x00
FlexCount parameters = 0
0x11
0xA0
FlexCount:
Outputs (NOUTLO) = low,
Reset (STOPFLEX) = stopped,
Interpolator (ENIPO) = disabled
Table 7: Register reset values (RAM)
Programming sequence
Following iC-LNB’s system reset (POK lo → hi) the internal RAM must be configured to through the SPI interface. A microcontroller with an integrated EEPROM
and SPI master is usually used for this purpose. Depending on the required function the parameters must
be written in a certain order (Figure 4).
If iC-LNB is to be used without FlexCount, only the required interpolator resolution is set (RESIPO) and en-
abled (ENIPO). The drivers at the A/B/Z outputs are
then switched from tristate to push-pull state.
If the device is to be operated with FlexCount, the user
then decides whether to leave the A/B/Z outputs in
low or switch these to tristate (TRIABZ). After configuring all parameters, FlexCount is enabled (STOPFLEX
1 → 0). After the current position has been found
(POSOK), the A/B/Z outputs can be enabled (TRIABZ
or NOUTLO).
Power On
(POK = 1)
write addresses 0x00 - 0x09
Yes
No
enable
Flexcount?
low
INCA, INCB, INCZ
tristate or low?
tristate
write addresses 0x0A – 0x10
0x0B: TRIABZ = 1
write addresses 0x0A – 0x10
0x0B: TRIABZ = 0
write address 0x0E
RESIPO
write address 0x11
NOUTLO = 1, ENIPO = 1,
RESSUB
write address 0x11
NOUTLO = 0, ENIPO = 1,
RESSUB
write address 0x11
ENIPO = 1
write address 0x11
STOPFLEX = 0
write address 0x11
STOPFLEX = 0
write address 0x0B
TRIABZ = 0
read address 0x12
POSOK = 1?
Yes
write address 0x0B
TRIABZ = 0
No
read address 0x12
POSOK = 1?
No
Yes
write address 0x11
NOUTLO = 1
configuration
finished
Figure 4: Example of a typical configuration sequence
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 19/35
OPERATING MODES
Device iC-LNB has two operating modes which are selected using register bit EPG.
EPG
Code
Addr. 0x07; bit 4
Description
0
1
Interface mode
Parallel mode
Table 8: Operating mode
In interface mode a shift register is provided for sensor data readout, with an incremental interface including an index signal (FlexCount active) for the output
of encoder quadrature signals with a configurable resolution. A power-on signal at pin POK indicates that
the system is enabled. Regardless of the FlexCount
resolution digital signals in Gray code are available at
outputs GA and GB. These can be used for example to
count the number of revolutions. A mechanical tilt angle of the scanner can be adjusted using output signal
XJD.
In parallel encoder mode the sensor data is output as
a 16-bit, parallel data word in Gray code. For this purpose all the relevant pins are reconfigured as outputs.
Table 9 shows the pin functions for the respective operating mode (also see the parallel encoder mode section on page 31).
The SPI interface for device configuration can also be
used for position data readout and is available in both
operating modes.
PAD FUNCTIONS
Pad
Interface mode
Parallel mode
GND
I/O Ports Ground
I/O Ports Ground
VDD
+ 3V to +5.5 V I/O Ports Supply Voltage
+ 3V to +5.5 V I/O Ports Supply Voltage
SCK
SPI Clock Input
SPI Clock Input
MOSI
SPI Data Input
SPI Data Input
MISO
SPI Data Output
SPI Data Output
CS
SPI Chip Select Input
SPI Chip Select Input
TNC
Test Input NCOS
Parallel Output Bit 15
TNS
Test Input NSIN
Parallel Output Bit 14
DIR
Code Inversion Input
Parallel Output Bit 13
NSL
Shift Register Load Input
Parallel Output Bit 12
DIN
Shift Register Data Input
Parallel Output Bit 11
DOUT
Shift Register Data Output
Parallel Output Bit 10
CLK
Shift Register Clock Input
Parallel Output Bit 9
GA
Graycode Output A (MSB)
Parallel Output Bit 8
GB
Graycode Output B (MSB-1)
Parallel Output Bit 7
XJD
Adjustment Signal
Parallel Output Bit 6
POK
Power OK Indication
Parallel Output Bit 5
INCZ
Incremental Output Z
Parallel Output Bit 4
INCB
Incremental Output B
Parallel Output Bit 3
INCA
Incremental Output A
Parallel Output Bit 2
ERR
Error Message Output
Error Message Output
TPS
Test Input PSIN
Parallel Output Bit 1
TPC
Test Input PCOS
Parallel Output Bit 0
NCOS
Analog Voltage Output NCOS
Analog Voltage Output NCOS
PCOS
Analog Voltage Output PCOS
Analog Voltage Output PCOS
NSIN
Analog Voltage Output NSIN
Analog Voltage Output NSIN
PSIN
Analog Voltage Output PSIN
Analog Voltage Output PSIN
LED
LED High Side Current Source
LED High Side Current Source
VDDA
+ 4V to +5.5V Supply Voltage
+ 4V to +5.5V Supply Voltage
GNDA
Ground
Ground
Table 9: Pad functions according to operating mode
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 20/35
SPI INTERFACE
CS
SCLK
MOSI
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
MISO
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 5: SPI transmission, taking the read OPCODE REGISTER as an example (continuous)
General protocol description
iC-LNB’s SPI interface is implemented as an SPI slave
and supports SPI modes 0 and 3, meaning the idle
time at SCK can be 0 or 1. Data is always accepted on
a rising edge at SCK. The idle state of the MISO line is
1; on a rising edge at CS the MOSI signal is switched
through to the MISO signal. Data is sent byte by byte
with the MSB (most significant bit) first.
Each data transmission starts when a 1-byte OPCODE
is sent by the SPI master (Table 10). This OPCODE
selects whether the iC-LNB configuration data (REGISTER) or position data (SDAD) should be accessed,
for instance.
OPCODE description
ACTIVATE
iC-LNB’s register and sensor data channels can be
switched on and off using the ACTIVATE command.
The command causes all slaves to zero their RACTIVE
and PACTIVE registers and to loop this register data
into the data stream between the MOSI and MISO. The
register and sensor or actuator data channels can be
switched on and off using the following data bytes.
After a power-on iC-LNB’s sensor data channel is disabled (PACTIVE = 0) and register communication enabled (RACTIVE = 1).
CS
OPCODE
Code
Command
0xB0
0xA6
0xF5
0x8A
0xCF
0xAD
ACTIVATE
Sensor data (SDAD) transmission
Sensor data (SDAD) status
REGISTER read (continuous)
REGISTER write (continuous)
REGISTER status/data
Table 10: SPI Instructions / OPCODES
SPI data transmission takes place as follows:
(Figure 5):
1. The master initializes a transmission on a rising
edge at CS.
2. iC-LNB transfers the level from MOSI to MISO.
3. The master transmits the OPCODE and address
ADR through MOSI; iC-LNB immediately outputs
OPCODE and ADR through MISO.
4. iC-LNB transmits the data requested according
to the address.
5. The master ends the command with a falling
edge at CS.
6. iC-LNB switches its MISO output to 1.
SCLK
MOSI
OP
MISO
OP
RAPA 0-3
RAPA 4-7
...
8 cycles
Figure 6: Setting ACTIVATE: RACTIVE/PACTIVE
(several slaves)
Bytes FAIL, VALID, BUSY, and DISMISS in the STATUS byte are reset by the ACTIVATE command (Table
14).
RACTIVE
Code
Description
0
1
Register communication deactivated
Register communication activated
Table 11: Register com. activation
If RACTIVE is not set, on commands Read REGISTER (cont.), Write to REGISTER (cont.), and REGISTER status/data the ERROR bit is set in the SPI
interface STATUS byte (Table 14), indicating that the
command has not been carried out. The slave immediately outputs the data at MISO which has been sent
by the master through MOSI.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 21/35
PACTIVE
Code
Description
0
1
Sensor data channel deactivated
Sensor data channel activated
CS
REQ
SCLK
Table 12: Sensor data activation
If PACTIVE is not set, on commands Sensor data status or Sensor data transmission the ERROR bit is
set in the STATUS byte (Table 14), indicating that the
command has not been carried out. The slave immediately outputs the data at MISO which has been sent
by the master through MOSI.
If only one slave is connected up with one register and
one sensor data channel, it must be ensured that the
RACTIVE and PACTIVE bits are last in the data byte
(Figure 7).
MOSI
OP
MISO
OP
SD1
SD2
SD3
8 cycles
Figure 8: SDAD transmission: read SD
With command Sensor data transmission the master
can not only read sensor data (SD) out from the slave;
at the same time it can also transmit actuator data (AD)
to the slave. iC-LNB ignores the transmitted actuator
data.
CS
REQ
SCLK
NB: daisy chain
If the slaves are connected in a chain (full duplex
chain), with this command the master can determine
the number of connected register and sensor data
channels. To this end it can send a 1 after the OPCODE, which is repeated at MISO after the number
of register and sensor data channels (see Figure 7).
CS
SCLK
MOSI
OP
1
0
0
0
0
0
RA
PA
MISO
OP
0
0
1
0
0
0
0
0
8 cycles
RACTIVE / PACTIVE vector
If invalid data is sampled in the shift register, the
ERROR bit is set in the STATUS byte (Tab. 14) and
zeroes are output as the data word.
OP
AD1
AD2
AD3
MISO
OP
SD1
SD2
SD3
8 cycles
Figure 9: SDAD transmission: read SD, write AD
Sensor data status
Should the master not know the processing time, it can
request sensor data using the command Sensor data
status. iC-LNB does not need any processing time;
therefore, SVALID is always valid.
The command causes
1. all slaves activated with PACTIVE to switch their
SVALID register between MOSI and MISO.
Figure 7: Setting ACTIVATE: RACTIVE/PACTIVE
(one slave)
Sensor data transmission
iC-LNB latches its position data on the first rising edge
at SCLK if CS is switched to 1 (REQ). The sensor data
shift register is switched between signals MOSI and
MISO for SPI communication and can then be clocked
out. The size of the sensor data shift register must
be set to 18 bits (see section on shift register output,
page 30). The position data is output with the MSB
first. Byte SD3 (Figure 8) is then filled with zeroes.
MOSI
2. The next request for sensor data, triggered on
the first rising edge at SCLK when CS has again
been set to 1, is ignored by the slave.
The end of conversion is signaled by SVALID (SV).
With this command the master can poll to the end of
conversion. The sensor data is readout on the command SDAD transmission.
SVALID
Code
Description
0
Sensor data channel invalid
1
Sensor data channel valid
Table 13: Sensor data valid indication
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 22/35
REQ
CS
and a DATA byte. The DATA byte is not available in
iC-LNB and is thus not defined.
SCLK
MOSI
OP
MISO
OP
CS
SV 0-7 SV 8-15
SCLK
...
8 cycles
MOSI
OP
MISO
OP
Figure 10: SDAD status
8 cycles
If only one slave is connected, the relevant SVALID bit
is placed at bit position 7 in the SVALID byte (SV0,
Figure 11).
CS
REQ
SCLK
MOSI
OP
0
0
0
0
0
0
0
0
MISO
OP
SV 0
0
0
0
0
0
0
0
8 cycles
STATUS DATA
Figure 12: REGISTER status/data
Read REGISTER (continuous)
The master transmits the OPCODE Read REGISTER
(cont.). Start address ADR, from which point data is to
be read, is transmitted in the 2nd byte. The slave immediately outputs the OPCODE and address and then
transmits DATA1. The internal address counter is incremented after each data package.
SVALID vector
Figure 11: SDAD status (one slave)
REGISTER status/data
The status of the last REGISTER communication or
the last data transmission can be queried using the
REGISTER status/data command. The STATUS byte
contains the information summarized in Table 14.
STATUS
Bit
Name
Description of the status
report
7
ERROR
OPCODE invalid.
Sensor data was invalid
on readout
6..4
3
2
1
DISMISS
FAIL
BUSY
0
VALID
Reserved
Address refused
Data request has failed
Slave is busy with a
request
DATA is valid
NB
Display logic: 1 = true, 0 = false
Table 14: SPI status information
All status bits are updated with each register access.
The ERROR bit is the exception to the rule; this bit
signals whether an error occurred during the last communication with the SPI interface or not.
The master transmits the OPCODE REGISTER status/data. iC-LNB immediately passes the OPCODE
on to MISO. iC-LNB then transmits the STATUS byte
If an error occurs during register readout in continuous mode, i.e. the address is invalid, the requested
data was not valid on data byte clocking, etc., the internal address counter is incremented no further and
the FAIL error bit is set in the status byte (Table 14).
CS
SCLK
MOSI
OP
ADR
MISO
OP
ADR
DATA1
DATA2
...
8 cycles
Figure 13: Read REGISTER (cont.)
Write to REGISTER (continuous)
The master transmits the OPCODE Write to REGISTER (cont.). Start address ADR, from which point successive data DATA1-DATAn is to be written, is transmitted in the 2nd byte. The slave immediately outputs the
OPCODE, address, and data at MISO. The slave increments its internal address counter after each DATAn
data package.
If an error occurs during a write to register in continuous mode, i.e. the address is invalid, writing of the
last address data has not finished, etc., the internal address counter is incremented no further and the FAIL
error bit is set in the status byte (Table 14).
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 23/35
CS
SCLK
MOSI
OP
ADR
DATA1
DATA2
...
MISO
OP
ADR
DATA1
DATA2
...
8 cycles
Figure 14: Write to REGISTER (cont.)
GRAY-CODE OUTPUTS
In interface mode the outputs GA, GB provide two
90° shifted digital signals with 1 PPR each (Figure 15). The signals are independent of the FlexCount resolution (RESSUB) or the zero position
(ZPOS), but pin DIR or register bit DIR can be
applied to invert the signal GA (code inversion).
Thereby GA and GB can be used for instance to
trigger an external multiturn to count the revolutions.
0°
90°
180°
270°
360°
GA (MSB)
GB (MSB-1)
V10 (DA10V)
N10 (DA10N)
V9 (DA9V)
N9 (DA9N)
One revolution
Figure 15: Phase of GA, GB without code inversion
ADJUSTMENT
iC-LNB is adjusted in relation to the code disc with the
help of an electronic alignment aid.
Tilt angle
In interface mode (EPG = 0) an EXORed signal from
tracks DA4V and DA10V (differential signal of the leading track 4 and track 10 diodes) is output at pin XJD.
By tilting iC-LNB output signal XJD can be given a minimum spike length at 0° and 180°.
The falling or rising edge of signal GA (MSB bit in interface mode) marks the 0° and 180° positions.
The maximum tilt angle tolerated by the system is stipulated by the resolution and the diameter of the code
disc. Table 15 shows the allocation of the maximum tilt
to the relevant code disc.
Code disc
tilt angle max.
LNB1S 42-1024
LNB4S 26-1024
1.8°
1.0°
Table 15: Maximum tilt angle referenced to the chip’s
center
Example: LNB1S 42-1024
The scan ratio for the adjustment signal at XJD can
be derived from the maximum tilt. At a tilt angle of
1.8° photodiode DA4V is approximately 74 µm from
the ideal position; with an average radius of 19.89 mm
for track DA4 there is an edge shift of 0.06%. The
edge shift for photodiode DA10V is contradirectional
and about the same size. A spike length of t/T = 0.12%
is thus accrued for a maximum tilt angle of 1.8°. If we
were to take half of the maximum tilt angle as a target
alignment, i.e. 0.9°, the device must be aligned to a
spike length of (t/T) < 0.06%.
Spike length t can be computed dependent on the
speed. Under optimum conditions the maximum spike
length is t = 0.0006 / revs per second. Due to imperfect
light levels, code disc tolerances, etc. a spike length
of about half this maximum value should be aimed for
(e.g. of less than 60 µs for a speed of 300 rpm).
The maximum spike length must be adhered to for both
spikes (at 0° and 180°); ideally, both spikes should be
the same length.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 24/35
T/2
GA (MSB)
XJD
t
t
0°
180°
Figure 16: EXOR signal at XJD in interface mode
Radial adjustment to code disc
The digital tracks’ distance determines the maximum
tolerable offset from the radial ideal position. Starting
from an offset of > 100 µm a crosstalk of the nearby
digital track occurs. This can cause an incorrect absolute position.
A radial offset causes amongst others an alteration
in the phase contact between sine/cosine signals.
Thereby with minimizing the phase error the radial po-
sition can be adjusted in a range of about ±150 µm.
Table 16 illustrates the phase error at a radial offset of
100 µm.
Code disc
Phase error
LNB1S 42-1024
LNB4S 26-1024
0.65°
1.6°
Table 16: Phase error at a radial offset of 100 µm
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 25/35
SIGNAL CONDITIONING
iC-LNB has various parameters for signal conditioning.
Gain
The gain of the analog sine/cosine track can be set using parameter GR. A gain factor of 1.33 (GR = 0x01)
can be used for most applications.
GR
Code
Addr. 0x07; bit 1:0
Gain factor
00
01
10
11
1.0
1.33
1.6
2.0
GS
Code
Addr. 0x00; bit 5:0
Gain factor
0x00
0x01
...
1.0
1.01
0x3F
2.0
1+GS·0.0053
1−GS·0.0053
Table 18: PSIN and NSIN gain
The PSIN and NSIN offsets can be calibrated separately using parameters OSP and OSN. The offset
of signal PSIN must be calibrated to reference signal
VDDAH. This signal is available in test mode at pin
NCOS. The offset of signal NSIN must then be calibrated to the calibrated offset of signal PSIN.
Table 17: Gain range for the sine/cosine track
The sine/cosine signals can be calibrated in amplitude
and offset (Figure 17). To this end the LED power control must be programmed to sum control (LCTYP = 1)
and the internal calibration signals switched to analog outputs PSIN, NSIN, PCOS, and NCOS (TA = 0x1,
page 33).
The optical power of the LED can be adjusted to the
approximate target amplitude (VPx/VNx) with parameter LCSET(5:0). The amplitude and offset parameters
should be set to reasonable start values for this purpose (see register reset values in Table 7).
OSP
Code
Addr. 0x02; bit 6:0
Offset values
0x00
0x01
...
0x7F
0.45 · VDDA
0.4508 · VDDA
(0.45 + OSP·0.1
) · VDDA
127
0.55 · VDDA
Table 19: PSIN offset
OSN
Addr. 0x03; bit 6:0
Code
Offset values
0x00
0x01
0.45 · VDDA
0.4508 · VDDA
...
0x7F
(0.45 + OSN·0.1
) · VDDA
127
0.55 · VDDA
Table 20: NSIN offset
TA = 0x1
TMUX = 0x0D
or
TMUX = 0x0E
PSIN
VPx
NSIN
VNx
VPx
PCOS
VDDAH
VNx
Cosine calibration
To calibrate the cosine signals TMUX must be programmed to 0x0E. The amplitude of signals PCOS and
NCOS can then be calibrated to the same amplitude as
that of the sine signals using parameter GS.
NCOS
VDDAH
GNDA
(x = S, C)
Figure 17: Sine/cosine signal calibration
Sine calibration
To calibrate the sine signals TMUX must be programmed to 0x0D (page 33). The amplitude of signals
PSIN and NSIN can then be calibrated using parameter GS. The target amplitude (VPx/VNx) is 500 mVp.
GC
Code
Addr. 0x01; bit 5:0
Gain factors
0x00
0x01
...
1.0
1.01
0x3F
2.0
1+GC·0.0053
1−GC·0.0053
Table 21: PCOS and NCOS gain
The PCOS and NCOS offsets can be calibrated separately using parameters OCP and OCN. The offset
of signal PCOS must be calibrated to reference signal
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 26/35
VDDAH. This signal is available in test mode at pin
NCOS. The offset of signal NCOS must then be calibrated to the calibrated offset of signal PCOS.
OCP
Code
Addr. 0x04; bit 6:0
Offset values
0x00
0x01
...
0.45 · VDDA
0.4508 · VDDA
(0.45 + OCP·0.1
) · VDDA
127
0x7F
0.55 · VDDA
The signal path of the Sin/Cos tracks is shown in Figure 18 with the conditioning unit.
DPSIN
Vref
3Meg
GS
+
+
-
VPSI
-
NSIN
+
GS
GR
+
-
Vref
VDDA
OSN
VREFNS
Table 22: PCOS offset
VREFPS
OCN
Addr. 0x05; bit 6:0
Code
Offset values
0x00
0x01
0.45 · VDDA
0.4508 · VDDA
...
0x7F
) · VDDA
(0.45 + OCN·0.1
127
0.55 · VDDA
DNSIN
Vref
+
VNSI
-
GS
GR
OSP
PSIN
-
Vref
DPCOS
Vref
3Meg
GC
+
+
-
VPCO
-
NCOS
+
GC
GR
Square control
After all parameters (gain and offset) have been calibrated, it is recommended that the square control function in the LED power control be enabled (see the LED
power control section on page 27) in order to keep the
optical receive power of the sine/cosine sensors constant, regardless of temperature and LED ageing effects. To this end the device is switched to normal
mode (TA = 0x0) and square control enabled (LCTYP =
0). The LED power control setpoint is adjusted to the
set target amplitude with parameter LCSET(5:0).
-
VDDA
GS
+
+
-
Table 23: NCOS offset
3Meg
+
+
-
Vref
VDDA
OCN
VREFNC
VREFPC
DNCOS
Vref
3Meg
-
VDDA
OCP
GC
+
+
+
GR
+
VNCO
GC
-
Vref
Figure 18: Sin/Cos signal path
PCOS
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 27/35
LED POWER CONTROL
The optical receive power of the sine/cosine sensors
is kept constant by an integrated LED control unit, regardless of the temperature and ageing effects of the
LED. The mode of control can be selected using parameter LCTYP, the possible options being sum control
or square control. So that the internal interpolator is
always optimally controlled in all operating conditions,
square control should be used. Sum control should be
used for signal conditioning.
LCTYP
Code
Addr. 0x06; bit 6
Control type
0
square control (sin2 +cos2 )
1
sum control (DC controlled prop. to VR())
Table 24: LED power control type
The setpoint for the control can be configured using
parameter LCSET(5:0).
LCSET(5:0)
Addr. 0x06; bit 5:0
Code
Square control
Sum control
LCTYP = 0
LCTYP = 1
0x00
0x01
...
0.240 Vp
0.243 Vp
0.140 V
0.142 V
0.24 Vp
1−i·0.0125
0.14 V
1−i·0.0125
0x3F
1.1 Vp
0.640 V
Table 25: LED power control setpoint
LCMOD
Code
Adr 0x01, bit 6
Control mode (LCTYP = 0 or 1)
0
continuous control
1
deadband control (approx. 5 % of setpoint)
Table 26: LED power control mode
Error monitoring
iC-LNB’s LED power control is monitored. Should the
LED current exceed its control range, internal error
ERRS (status register) is set to 1. This error signal
is linked to iC-LNB’s ERRP alarm (parity check) and
output at error output ERR (see the alarm output section).
INTERPOLATOR
Interpolator resolution
The resolution of the internal interpolator is set using RESIPO. The maximum permissible Sin/Cos signal
frequency (RPM speed) is dependent on the selected
resolution. Before changing the interpolator resolution,
the interpolator must be disabled (ENIPO = 0). During
the interpolator is disabled 0 is output as the interpolated position value. Once changes have been made,
the interpolator can be re-enabled (ENIPO = 1).
RESIPO
Code
Addr. 0x0E; bit 6:5
Interpolator resolution
Max. sin/cos frequency
00
01
10
11
8 bit
7 bit
6 bit
Interpolator deactivated
50 kHz
100 kHz
200 kHz
-
Table 27: Interpolator resolution
ENIPO
Addr. 0x11; bit 4
Code
Description
0
1
Interpolator disabled
Interpolator enabled
Table 28: Interpolator enable
Interpolator filter
The interpolator input signals can be filtered by a lowpass filter. This filter can be enabled by NENF. The filter has been designed so that it can be applied across
the entire speed range.
NENF
Addr. 0x07; bit 6
Code
Description
0
1
Filter enabled (recommended)
Filter disabled
Table 29: Interpolator filter
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 28/35
FLEXCOUNT®
When FlexCount is enabled in iC-LNB, the resolution
can be freely programmed and is output through the
incremental signals. Another option is to output the set
resolution through the SPI interface and the shift register, or, in parallel encoder mode, to the parallel IO
ports. FlexCount operates in real time and does not
introduce any significant latency to the signal path.
Enable/disable
FlexCount can be enabled using register bit NENFLEX. SELABS determines whether the FlexCount
resolution or iC-LNB’s maximum internal resolution
(dependent on RESIPO) is output for the absolute data
output (parallel encoder mode, shift register or SPI).
NENFLEX
Code
Addr. 0x0B; bit 1
Description
0
1
FlexCount enabled
FlexCount disabled
Table 30: FlexCount disable
SELABS
Addr. 0x0B; bit 2
Code
SER/PAR/SPI interface
0
1
FlexCount resolution
Maximum resolution*
*16 bit, 17 bit, 18 bit dependent on RESIPO
RESSUB
Code
Addr. 0x0F; 0x10; 0x11 bit 3:0
Resolution (edges per revolution)
0x3
0x7
...
0x0FFFF
...
0x1FFFF
4
8
RESSUB + 1
65536
... (only with 7/8 bit interpolation)
131072 (only with 7/8 bit interpolation)
...
0x3FFFF
... (only with 8 bit interpolation)
262144 (only with 8 bit interpolation)
NB: RESSUB = resolution - 1
Table 32: FlexCount resolution
Reset
FlexCount must be stopped before the resolution or direction of rotation are reprogrammed (pin DIR or register bit DIR). This is done using register bit STOPFLEX.
This freezes the FlexCount outputs and FlexCount
goes into its reset state. After STOPFLEX has been
reset the outputs are enabled and FlexCount moves to
the current position.
STOPFLEX
Addr. 0x11; bit 5
Code
Description
0
Normal operation
1
FlexCount stopped
FlexCount reset: STOPFLEX 1 → 0
Table 33: FlexCount reset
Table 31: SPI, SER, PAR absolute output options
Resolution
Parameter RESSUB defines the FlexCount resolution.
The binary value in RESSUB is equivalent to the required resolution minus 1; for instance, RESSUB must
be programmed to 0x0FFFF (binary value for 65,535)
for a resolution of 65,536 steps (a 16-bit resolution).
The required resolution must be divisible by four and
the maximum resolution is limited by the set interpolator resolution. At an interpolation of 6 bits FlexCount
may have a maximum resolution of 65,536 (RESSUB =
0x0FFFF); at 7-bit interpolation this maximum rises
to 131,072 (RESSUB = 0x1FFFF), and at 8 bits to a
full resolution of 262,144 (RESSUB = 0X3FFFF). FlexCount is always output in Gray code for all settable resolutions. With non-binary resolutions the Gray code is
capped symmetrically to 0. This retains the required
single-step transitions of the Gray code.
Following a reset (STOPFLEX 1 → 0) FlexCount
searches for the current position. During this position
signals/data are not valid. Attainment of the current
position and thus valid output signals are indicated in
the status register with POSOK.
POSOK
Code
Addr. 0x12; bit 0
Description
0
1
Position invalid
Position valid
Table 34: Position valid
The FlexCount output signals can be set to low using
register bit NOUTLO; FlexCount itself continues to run.
This function should be used after FlexCount has been
reset to prevent the device ’running’ to the current position in the output signals.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 29/35
NOUTLO
Code
Addr. 0x11; bit 6
Internal FlexCount outputs
INVZ
Code
Addr. 0x0B; bit 4
Incremental output INCZ
0
1
low
Normal operation
0
1
not inverted
inverted
Table 35: Setting FlexCount outputs to low
Hysteresis
A hysteresis can be programmed for FlexCount. The
size of the hysteresis can be set as a multiple of the
interpolator LSB step size using parameter HYS. This
means that the resolution of the interpolator influences
the selectable hysteresis.
HYS
Code
Addr. 0x0B, bit 0; Addr. 0x0A, bit 6:0
RESIPO = 0x0 RESIPO = 0x1 RESIPO = 0x2
8-bit interp.
7-bit interp.
6-bit interp.
0x0
No hysteresis
No hysteresis
No hysteresis
0x1
0x2
0x3
0x4
...
0xFC
±1 LSB
±2 LSB
±3 LSB
±4 LSB
No hysteresis
±1 LSB
±1 LSB
±2 LSB
No hysteresis
No hysteresis
No hysteresis
±1 LSB
±252 LSB
±126 LSB
±63 LSB
Table 39: Output inversion INCZ
Position offset
iC-LNB’s FlexCount permits a programmable position
offset. This offset can be set as a binary value of
the maximum internal resolution (which is dependent
on interpolator resolution RESIPO) using parameter
ZPOS (not in the selected FlexCount resolution). All
values from 0 to 262,143 can be selected at 8 bits; at
7 bits the LSB must remained fixed at 0, and at 6 bits
the last two LSBs must be 0. If no position offset is set
(ZPOS = 0x0), the zero position is symmetrical with the
falling edge of the MSB (in interface operation: signal
at pin GA, Figure 19).
ZPOS = 0x0
GA (MSB)
INCZ
INCA
INCB
Figure 19: Zero position for ZPOS = 0x0
Table 36: FlexCount hysteresis
Incremental outputs
When FlexCount is enabled, incremental outputs
A/B/Z can be inverted as required using register bits
INVA, INVB, and INVZ. If the A/B/Z outputs are not
generated by FlexCount (INC 6= 0x07), inversion will
not function.
INVA
Code
Addr. 0x0B; bit 6
Incremental output INCA
0
1
not inverted
inverted
Table 37: Output inversion INCA
ZPOS
Code
Addr. 0x0C; 0x0D; 0x0E bit 3:0
Positions offset (binary)
0x0
0x1
0x2
...
0x7FFF
0
1 (only with 8 bit interpolation)
2 (only with 7/8 bit interpolation)
ZPOS
32767 (only with 8 bit interpolation)
...
0x10000
...
0x3FFFF
ZPOS
65536
ZPOS
262143 (only with 8 bit interpolation)
Table 40: Position offset
The length of the Z pulse can be selected using parameter Z90. It can be set to a width of 90◦ or 180◦
.
INVB
Code
Adr 0x0B, bit 5
Incremental output INCB
Z90
Code
Addr. 0x0E; bit 4
Index width
Index gating
0
1
not inverted
inverted
0
1
180◦
90◦
A
A&B
Table 38: Output inversion INCB
Table 41: Z pulse width
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 30/35
INCREMENTAL OUTPUT
Selecting the output
At pins INCA and INCB incremental signals are output
with either various interpolation factors or FlexCount
resolutions. Selection is made using parameter INC.
INC
Code
Addr. 0x08; bit 6:4
Function
0x00
0x01
0x02
0x03
0x04
Interpolation factor x1
Interpolation factor x2
Interpolation factor x4
Interpolation factor x8
Interpolation factor x16
0x05
0x06
0x07
iC-Haus digital test
iC-Haus test
FlexCount
A valid Z pulse is only output at pin INCZ when FlexCount is enabled (INC = 0x07).
Output in digital test and iC-Haus test modes is described in the section on test functions on page 33.
Tristate
The incremental signal pins (INCA/INCB/INCZ) can be
switched to tristate using register bit TRIABZ. After a
power-on TRIABZ is initialized with a 1.
Table 42: Incremental output options
TRIABZ
Code
Addr. 0x0B; bit 3
Pin function of INCA, INCB, INCZ
0
1
Push-pull (incremental signals)
Tristate
Table 43: Incremental output tristate
SHIFT REGISTER OUTPUT
RNF = 0
NSL
Latch
CLK
DOUT
MSB
MSB-1
LSB
DIN
MSB-1
LSB
DIN
RNF = 1
NSL
Latch
CLK
DOUT
MSB
Figure 20: Shift register output
iC-LNB has a shift register for position data readout. In
order to enable this shift register the sensor data channel for the SPI interface must be disabled by command
ACTIVATE (table 12). After power-on the shift register
in iC-LNB is active and the sensor data channel of the
SPI interface is deactivated.
The position data is output in Gray code or binary code
(depending on parameter NGRAY), with the MSB first.
If pin NSL = 1, the position data is loaded into the shift
register on the first falling edge at pin CLK. Following
this, the data is clocked out on each rising edge at pin
CLK, regardless of the level at pin NSL.
The shift register returns to its idle state on a rising
edge at NSL. This means that the falling edge at NSL
can occur during data transmission and is not time critical.
RNF is used to select an output level at pin DOUT for
idle state - either idle 1 (high) or the MSB bit in real
time. External data can be read into iC-LNB through
shift register input pin DIN. This is output after the position data. The position data readout process is shown
in Figure 20.
The length of the shift register and the number of data
bits used can be selected using parameter SRC.
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 31/35
NGRAY
Code
Addr. 0x07; bit 6
Data format
0
1
Gray
binary
The MSB of the position data can be inverted by parameter DIR or pin DIR (code inversion). Parameter
DIR and pin DIR are exor gated; for instance, no code
inversion occurs if the level at pin DIR is high and parameter DIR = 1.
Table 44: Shift register output data format
If binary output is enabled (NGRAY = 1) , DIN must be
switched to 0, i.e. no external data can be read into the
shift register (as in ring operation, for example).
RNF
Addr. 0x08; bit 3
Code
Output pin DOUT
0
1
MSB bit
High
NB:
If FlexCount is enabled, after changing the direction
of rotation FlexCount must be reset (Table 33).
DIR
Code
Addr. 0x07; bit 5
Description
0
1
CW (no inversion)
CCW (inversion)
Table 47: Code inversion
Table 45: Shift register idle output
SRC
Code
Addr. 0x08; bit 2:0
Shift register length
Number of used bits
000
18-bit
18
001
17-bit
17
010
011
100
101
16-bit
16-bit
16-bit
16-bit
16
15
14
13
110
111
14-bit
14-bit
13
12
Table 46: Shift register length
PARALLEL ENCODER MODE
Depending on SELABS, in parallel encoder mode 16
bits of position data (10 bits from the digital tracks and
6 bits from the interpolator) are output in parallel, or
FlexCount outputs the top 16 bits in parallel with the
set RESSUB resolution.
Parallel encoder mode is enabled by parameter
EPG = 1.
The interpolator resolution can be set to 6 bits (RESIPO = 0b10) to permit the maximum input frequency.
Programming the interpolator resolution to 7 and 8 bits
allows an extra 17 or 18 bits of position data to be read
in through the SPI interface.
EPG
Code
Addr. 0x07; bit 4
Description
0
1
Interface mode
Parallel mode
Table 48: Selecting the operating mode
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 32/35
ALARM OUTPUT
iC-LNB has an alarm or error output to indicate existing errors. If an error occurs, pin ERR is set to 1.
ERROR MESSAGE
iC-LNB’s LED power control range is monitored.
Should the LED power control exceed its control range,
internal error ERRS (status register, table 6) is set to 1.
ERRS
ERRP
If the parity check signals an error in the RAM area,
internal error ERRP (status register, table 6) is set to 1.
VDD
ERR
³1
GND
Figure 21: Alarm output
OSCILLATOR
iC-LNB has two internal oscillators for the interpolator
and FlexCount. The frequency of these oscillators can
be finely adjusted using register OSZC; this frequency
limits iC-LNB’s permissible Sin/Cos frequency.
In Table 49 fb is a basic frequency of typically
12.8 MHz.
OSZC
Code
Addr. 0x07; bit 3:2
Description
Oscillator frequency (typ.)
00
01
10
11
1.000 · fb
1.078 · fb
1.125 · fb
1.140 · fb
12.8 MHz
13.8 MHz
14.4 MHz
14.6 MHz
Table 49: Oscillator adjustment
preliminary
iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 33/35
TEST FUNCTIONS
TA
Code
Addr. 0x09; bit 5:4
Output at PSIN, NSIN, PCOS, NCOS
TMUX
Code
Addr. 0x09; bit 3:0
Pin INCA
Pin INCB
Pin INCZ
00
01
10
11
Normal operation
Test signals (s. Tab. 51)
iC-Haus test
iC-Haus test
0x00
NENOS
NLOCK
I7
0x01
V1
N1
I7
0x02
V1
N1
I7
0x03
V2
N2
I7
0x04
V3
N3
I7
0x05
V4
N4
I7
0x06
V5
N5
I7
0x07
V6
N6
I7
Table 50: Test modes
TMUX
Code
Addr. 0x09; bit 3:0
Pin PSIN
Pin NSIN
Pin PCOS
Pin NCOS
0x08
V7
N7
I7
0x00
VPSI
VNSI
VPCI
VNCI
0x09
V8
N8
I7
0x01
AVP1
VTH
AVN1
VREF
0x0A
V9
N9
I7
0x02
ANP1
VTH
ANN1
VREF
0x0B
V10
N10
I7
0x03
AN2
VTH
AV2
VREF
0x0C
I6
I5
I7
0x04
AN3
VTH
AV3
VREF
0x0D
I4
I3
I7
0x05
AN4
VTH
AV4
VREF
0x0E
IPO_A
IPO_B
I7
0x06
AN5
VTH
AV5
VREF
0x0F
I2
I1
I7
0x07
AN6
VTH
AV6
VREF
0x08
AN7
VTH
AV7
VREF
0x09
AN8
VTH
AV8
VREF
0x0A
AN9
VTH
AV9
VREF
0x0B
AN10
VTH
AV10
VREF
0x0C
VREFPS
VREFNS
VREFPC
VREFNC
0x0D
PSIN
NSIN
PCOS
VDDAH
0x0E
PCOS
NCOS
PSIN
VDDAH
0x0F,
NENF = 1
IPQT
–
–
–
0x0F,
NENF = 0
PSF
NSF
PCF
NCF
Table 51: Test signal multiplexer for analog signals
(TA = 0x01)
Table 52: Test signal multiplexer for digital signals
(iC-Haus test, INC = 0x05)
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 34/35
DESIGN REVIEW: Notes On Chip Functions
iC-LNB X
No.
Function, Parameter/Code
Description and Application Notes
1
FlexCount outputs low:
NOUTLO = 1
Due to potential malfunction this parameter must not be used.
2
Permissible interpolator resolutions:
RESIPO = 0x0 (8 bit) or
RESIPO = 0x3 (deactivated)
Interpolator resolution 6/7 bit:
If the rotation alters its direction, incremental and parallel outputs may switch
wrong.
3
Default value of address 0x11 is 0x50
For configuration of iC-LNB first program address 0x11 to 0xA0, then follow
sequence in figure 4.
4
LCMOD not available
standard control active
5
LCTYP (address 0x06):
reset value is 0x30
For configuration of iC-LNB first program address 0x06 to 0x60, then follow
sequence in Figure 4.
Table 53: Notes on chip functions regarding iC-LNB chip release X
iC-LNB X1
No.
Function, Parameter/Code
Description and Application Notes
1
Interpolation without angle hysteresis
(Elec. Char. No. 703)
Use FlexCount (NENFLEX=0) with hysteresis of at least 1 LSB configured by
HYS.
2
LCMOD not available
standard control active
3
LCTYP (address 0x06):
reset value is 0x30
For configuration of iC-LNB first program address 0x06 to 0x60, then follow
sequence in Figure 4.
Table 54: Notes on chip functions regarding iC-LNB chip release X1
iC-LNB W1
No.
Function, Parameter/Code
1
LCTYP (address 0x06):
reset value is 0x30
Description and Application Notes
For configuration of iC-LNB first program address 0x06 to 0x60, then follow
sequence in Figure 4.
Table 55: Notes on chip functions regarding iC-LNB chip release W1
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
iC-LNB 18-BIT OPTO ENCODER
preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 35/35
ORDERING INFORMATION
Type
Package
Options
Order Designation
iC-LNB
30-pin optoBGA
standard reticle LNB1R
standard reticle LNB4R
customer specific reticle
iC-LNB oBGA LNB2C-1R
iC-LNB oBGA LNB2C-4R
iC-LNB oBGA LNB2C-xR
38-pin optoQFN
standard reticle LNB1R
customer specific reticle
iC-LNB oQFN38-7x5-1R
iC-LNB oQFN38-7x5-xR
Sin/Cos 1024 PPR,
10 bit digital
OD/ID ∅42/18 mm, glass
LNB1S 42-1024
Sin/Cos 1024 PPR,
10 bit digital
OD/ID ∅26/9.6 mm, glass
LNB4S 26-1024
Standard
Code Discs
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners