ISSI IS25CD025-JNLE 256kbit single operating voltage serial flash memory Datasheet

IS25CD025
256Kbit Single Operating Voltage Serial Flash Memory
With 100 MHz Dual-Output SPI Bus Interface
Output SPI Bus Interface
FEATURES
Memory With 100 MHz DualBus
Interface
Memory
With 100 MHz
• Low Power
Consumption
•Output
Single SPI
Power
Supply
Operation
Typical
6
mA
active
read current
SPI 2.70
BusVInterface
-Dual-Output
Low voltage range:
- 3.60 V
- Typical 10 mA program/erase current
• Memory Organization
- IS25CD025: 32K x 8 (256Kbit)
• Cost Effective Sector/Block Architecture
-256Kb : Uniform 4KByte sectors / one uniform
32KByte blocks
• Low standby current 10uA (Max)
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Sector, Block or Chip Erase Operation
- Maximum 7 ms sector, block or chip erase
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as readonly
• High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin SOIC 150mil
- 8-pin TSSOP
- KGD (Call Factory)
- Automotive Grades Available
- Lead-free (Pb-free) package
GENERAL DESCRIPTION
The IS25CD025 are 256Kbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output.
The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the
fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from
2.70 Volt to 3.60 Volt, to perform read, erase and program operations. The devices can be programmed in
standard EPROM programmers.
The IS25CD025 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial
Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command
codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.
The IS25CD025 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered
in 8-pin SOIC 150mil and 8-pin TSSOP. The devices operate at wide temperatures between -40°C to +105°C.
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IS25CD025
CONNECTION DIAGRAMS
CE#
1
8
SO
2
7
Vcc
HOLD#
CE#
SO
WP#
GND
1
2
3
4
8
7
6
5
Vcc
HOLD#
SCK
SI
8-Pin TSSOP
WP#
GND
3
6
SCK
4
5
SIO
8-Pin SOIC
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
SCK
SIO
SO
GND
Vcc
WP#
INPUT
INPUT/OUTPUT
OUTPUT
HOLD#
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input/Output
Serial Data Output
Ground
Device Power Supply
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends
on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is
high, the devices are not write-protected.
Hold: Pause serial communication by the master device without resetting
the serial sequence.
INPUT
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IS25CD025
BLOCK DIAGRAM
SIO
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IS25CD025
SPI MODES DESCRIPTION
Multiple IS25CD025 devices can be connected on the
SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 1. The devices
support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDIO
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
SPI Master
(i.e. Microcontroller)
CS3
CS2
SO
SIO
SCK
SPI Memory
Device
CS1
CE#
WP#
SO
SIO
SCK
CE#
WP#
CE#
HOLD#
SIO
SPI Memory
Device
SPI Memory
Device
HOLD#
SO
WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
appropriate.
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
MSb
Input mode
SO
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MSb
4
IS25CD025
SYSTEM CONFIGURATION
The IS25CD025 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI)
of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The
devices have two superset features that can be enabled through specific software instructions and the
Configuration Register:
Memory Density
256Kbit
Block No.
Block 0
Block
Size
(KBytes)
32
Sector 0
Sector 1
Sector
Size
(KBytes)
4
4
000000h - 000FFFh
001000h - 001FFFh
:
:
:
Sector 7
4
007000h - 007FFFh
Sector No.
Address Range
Table 1. Block/Sector Addresses of IS25CD025
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IS25CD025
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and are allowed. The WEL bit is set by a Write Enable
Status Register Bit Definitions.
(WREN) instruction. Each write register, program and
erase instruction must be preceded by a WREN
The BP0, BP1, BP2, and SRWD are non-volatile
instruction. The WEL bit can be reset by a Write
memory cells that can be written by a Write Status
Disable (WRDI) instruction. It will automatically be the
Register (WRSR) instruction. The default value of the
reset after the completion of a write instruction.
BP2, BP1, BP0 were set to “0” and SRWD bits was set
to “0” at factory. Once a “0” or “1”is written, it will not be BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,
changed by device power-up or power-down, and can BP0) bits are used to define the portion of the memory
only be altered by the next WRSR instruction. The
area to be protected. Refer to Tables 7, 8 and 9 for the
Status Register can be read by the Read Status
Block Write Protection bit settings. When a defined
Register (RDSR). Refer to Table 10 for Instruction Set. combination of BP2, BP1, and BP0 bits are set, the
corresponding memory area is protected. Any program
The function of Status Register bits are described as
or erase operation to that area will be inhibited. Note:
follows:
a Chip Erase (CHIP_ER) instruction is executed
successfully only if all the Block Protection Bits are set
WIP bit: The Write In Progress (WIP) bit is read-only,
as “0”s.
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
SRWD bit: The Status Register Write Disable (SRWD)
“0”, the device is ready for a write status register,
bit operates in conjunction with the Write Protection
program or erase operation. When the WIP bit is “1”,
(WP#) signal to provide a Hardware Protection Mode.
the device is busy.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
WEL bit: The Write Enable Latch (WEL) bit indicates
the WP# is pulled low (VIL), the volatile bits of Status
the status of the internal write enable latch. When the
Register (SRWD, BP2, BP1, BP0) become read-only,
WEL is “0”, the write enable latch is disabled, and all
and a WRSR instruction will be ignored. If the SRWD is
write operations, including write status register, page
set to “1” and WP# is pulled high (VIH), the Status
program, sector erase, block and chip erase operations Register can be changed by a WRSR instruction.
are inhibited. When the WEL bit is “1”, write operations
Table 5. Status Register Format
Default (flash bit)
Bit 7
SRWD
0
Bit 6
Bit 5
Reserved
0
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Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
6
IS25CD025
REGISTERS (CONTINUED)
Table 6. Status Register Bit Definition
Bit
Name
Bit 0
WIP
Bit 1
WEL
Bit 2
Bit 3
Bit 4
Bits 5 - 6
BP0
BP1
BP2
N/A
Bit 7
SRWD
Definition
Write In Progress Bit:
"0" indicates the device is ready
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Table 7 and Table 8 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Reserved: Always "0"s
Status Register Write Disable: (See Table 9 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Non-Volatile
bit
R
No
R/W
No
R/W
Yes
N/A
R/W
Yes
Table 8. Block Write Protect Bits for IS25CD025
Status Register Bits
BP2
BP1
BP0
Not used
0
0
Not used
0
1
Not used
1
0
Not used
1
1
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Protected Memory Area
256Kbit
None
None
None
All blocks: 000000h - 007FFFh
7
IS25CD025
REGISTERS (CONTINUED)
PROTECTION MODE
The IS25CD025 have two types of write-protection
Table 9. Hardware Write Protection on Status
mechanisms: hardware and software. These are used Register
to prevent irrelevant operation in a possibly noisy
environment and protect the data integrity.
SRWD
WP#
Status Register
0
Low
Writable
HARDWARE WRITE-PROTECTION
1
Low
Protected
The devices provide two hardware write-protection
0
High
Writable
features:
1
High
Writable
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of eight
before the executing. Any incomplete instruction
command sequence will be ignored.
b. The Write Protection (WP#) pin provides a
hardware write protection method for BP2, BP1, BP0
and SRWD in the Status Register. Refer to the
STATUS REGISTER description.
c.
Write inhibit is 2.4V, all write sequence will be
ignored when Vcc drop to 2.4V and lower
SOFTWARE WRITE PROTECTION
The IS25CD025 also provides two software write
protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by executing a Write
Enable (WREN) instruction. If the WEL bit is not
enabled first, the program, erase or write register
instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or the whole memory area to be write-protected.
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IS25CD025
DEVICE OPERATION
The IS25CD025 utilize an 8-bit instruction register.
Refer to Table 10 Instruction Set for details of the
Instructions and Instruction Codes. All instructions,
addresses, and data are shifted in with the most
significant bit (MSB) first on Serial Data Input (SI). The
input data on SI is latched on the rising edge of Serial
Clock (SCK) after Chip Enable (CE#) is driven low
(VIL). Every instruction sequence starts with a one-byte
instruction code and is followed by address bytes, data
bytes, or both address bytes and data bytes,
depending on the type of instruction. CE# must be
driven high (VIH) after the last bit of the instruction
sequence has been shifted in.
The timing for each instruction is illustrated in the
following operational descriptions.
Table 10. Instruction Set
Instruction Name
Hex
Code
RDID
JEDEC ID READ
ABh
9Fh
RDMDID
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FRDO
PAGE_ PROG
90h
06h
04h
05h
01h
03h
0Bh
3Bh
02h
SECTOR_ER
D7h/
20h
D8h
C7h/
60h
BLOCK_ER
CHIP_ER
Operation
Command
Cycle
Maximum
Frequency
Read Manufacturer and Product ID
Read Manufacturer and Product ID by JEDEC ID
Command
Read Manufacturer and Device ID
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Fast Read Dual Output
Page Program Data Bytes Into Memory
4 Bytes
1 Byte
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
33 MHz
100 MHz
100 MHz
100 MHz
Sector Erase
4 Bytes
1 Byte
1 Byte
1 Byte
2 Bytes
4 Bytes
5 Bytes
5 Bytes
4 Bytes +
256B
4 Bytes
Block Erase
Chip Erase
4 Bytes
1 Byte
100 MHz
100 MHz
100 MHz
HOLD OPERATION
HOLD# is used in conjunction with CE# to select
the IS25CD025. When the devices are selected and
a serial sequence is underway, HOLD# can be
used to pause the serial communication with the
master device without resetting the serial sequence.
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To pause, HOLD# is brought low while the SCK
signal is low. To resume serial communication,
HOLD# is brought high while the SCK signal is low
(SCK may still toggle during HOLD). Inputs to Sl will
be ignored while SO is in the high impedance state.
9
IS25CD025
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION) OPERATION
CE# goes high. The Device ID outputs repeatedly if
The Read Product Identification (RDID) instruction is
continuously send the additional clock cycles on SCK
for reading out the old style of 8-bit Electronic
while CE# is at low.
Signature, whose values are shown as table of ID
Definitions. This is not same as RDID or JEDEC ID
Table 11. Product Identification
instruction. It’s not recommended to use for new
design. For new design, please use RDID or JEDEC ID
instruction.
Product Identification
Data
First Byte
9Dh
The RDES instruction code is followed by three dummy
Manufacturer ID
Second Byte
7Fh
bytes, each bit being latched-in on SI during the rising
Device ID:
Device ID 1
Device ID 2
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
IS25CD025
02h
2Fh
falling edge of SCK. The RDES instruction is ended by
Figure 3. Read Product Identification Sequence
CE#
0
1
7
8
9
38
31
46
39
47
54
SCK
INSTRUCTION
SI
SO
3 Dummy Bytes
1010 1011b
HIGH IMPEDANCE
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Device ID1
Device ID1
Device ID1
10
IS25CD025
DEVICE OPERATION (CONTINUED)
JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)
OPERATION
The JEDEC ID READ instruction allows the user to
read the manufacturer and product ID of devices. Refer
to Table 11 Product Identification for pFlash
Manufacturer ID and Device ID. After the JEDEC ID
READ command is input, the second Manufacturer ID
(7Fh) is shifted out on SO with the MSB first, followed
by the first Manufacturer ID (9Dh) and the Device ID
(2Fh), each bit shifted out during the falling edge of
SCK. If CE# stays low after the last bit of the Device ID
is shifted out, the Manufacturer ID and Device ID will
loop until CE# is pulled high.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
CE#
0
15 16
7 8
23 24
31
SCK
INSTRUCTION
SI
SO
1001 1111b
HIGH IMPEDANCE
Manufacture ID2
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Manufacture ID1
Device ID2
11
IS25CD025
DEVICE OPERATION (CONTINUED)
RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)
OPERATION
The RDMDID instruction allows the user to read the
manufacturer and product ID of devices. Refer to Table
11 Product Identification for pFlash Manufacturer ID
and Device ID. The RDMDID command is input,
followed by a 24-bit address pointing to an ID table.
The table contains the first Manufacturer ID (9Dh) and
the Device ID (2Fh), and is shifted out on SO with the
MSB first, each bit shifted out during the falling edge of
SCK. If CE# stays low after the last bit of the Device ID
is shifted out, the Manufacturer ID and Device ID will
loop until CE# is pulled high.
Figure 5. Read Product Identification by RDMDID READ Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
SCK
28
29
30
31
1
A0
...
3 - BYTE ADDRESS
SIO
INSTRUCTION = 1001 0000b
23
22
42
43
... 3
21
2
HIGH IMPEDANCE
SO
CE#
32
33
34
35
36
37
38
39
40
41
44
45
46
47
2
1
0
SCK
SIO
Manufacturer ID1
SO
7
6
5
4
3
Device ID1
2
1
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0
7
6
5
4
3
12
IS25CD025
CE#
48
49
50
51
52
53
54
55
3
2
1
0
56
SCK
SIO
Manufacturer ID2
SO
7
6
5
4
Note :
(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)
ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
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IS25CD025
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the
Write Enable Latch (WEL) bit. The WEL bit of the
IS25CD025 is reset to the write –protected state after
power-up. The WEL bit must be write enabled before
any write operation, including sector, block erase, chip
erase, page program and write status register
operations. The WEL bit will be reset to the writeprotect state automatically upon completion of a write
operation. The WREN instruction is required before
any above operation is executed.
Figure 6. Write Enable Sequence
SIO
WRDI COMMAND (WRITE DISABLE) OPERATION
The Write Disable (WRDI) instruction resets the WEL
bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write
instruction, since the WEL bit is automatically reset.
Figure 7. Write Disable Sequence
SIO
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IS25CD025
DEVICE OPERATION (CONTINUED)
RDSR COMMAND (READ STATUS REGISTER) OPERATION
The Read Status Register (RDSR) instruction provides
access to the Status Register. During the execution of
a program, erase or write status register operation, all
other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or
completion of an operation by reading the WIP bit of
Status Register.
Figure 8. Read Status Register Sequence
SIO
WRSR COMMAND (WRITE STATUS REGISTER) OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and
status register write protection features by writing “0”s
or “1” s into the volatile BP2, BP1, BP0, and SRWD
bits.
Figure 9. Write Status Register Sequence
SIO
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IS25CD025
DEVICE OPERATION (CONTINUED)
READ COMMAND (READ DATA) OPERATION
The Read Data (READ) instruction is used to read
memory data of a IS25CD025 under normal mode
running up to 33 MHz.
The READ instruction code is transmitted via the Sl
line, followed by three address bytes (A23 - A0) of the
first memory location to be read. A total of 24 address
bits are shifted in, but only AMS (most significant
address) - A0 are decoded. The remaining bits (A23 –
AMS) are ignored. The first byte addressed can be at
any memory location. Upon completion, any data on
the Sl will be ignored. Refer to Table 12 for the related
Address Key.
The first byte data (D7 - D0) addressed is then shifted
out on the SO line, MSb first. A single byte of data, or
up to the whole memory array, can be read out in one
READ instruction. The address is automatically
incremented after each byte of data is shifted out. The
read operation can be terminated at any time by driving
CE# high (VIH) after the data comes out. When the
highest address of the devices is reached, the address
counter will roll over to the 000000h address, allowing
the entire memory to be read in one continuous READ
instruction.
Table 12. Address Key
Address
AN (AMS – A0)
Don't Care Bits
IS25CD025
A14 - A0
A23 – A15
Figure 12. Read Data Sequence
SIO
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IS25CD025
DEVICE OPERATION (CONTINUED)
FAST_READ COMMAND (FAST READ DATA) OPERATION
The FAST_READ instruction is used to read memory
data at up to a 100 MHz clock.
The first byte addressed can be at any memory
location. The address is automatically incremented
The FAST_READ instruction code is followed by three after each byte of data is shifted out. When the highest
address bytes (A23 - A0) and a dummy byte (8 clocks), address is reached, the address counter will roll over to
transmitted via the SI line, with each bit latched-in
the 000000h address, allowing the entire memory to be
during the rising edge of SCK. Then the first data byte read with a single FAST_READ instruction. The
addressed is shifted out on the SO line, with each bit
FAST_READ instruction is terminated by driving CE#
shifted out at a maximum frequency fCT, during the
high (VIH).
falling edge of SCK.
Figure 13. Fast Read Data Sequence
SIO
SIO
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IS25CD025
DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on
two output pins each at up to a 100 MHz clock.
is output on SO, while simultaneously the second bit is
output on SIO.
The FRDO instruction code is followed by three
address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in
during the rising edge of SCK. Then the first data byte
addressed is shifted out on the SO and SIO lines, with
each pair of bits shifted out at a maximum frequency
fCT, during the falling edge of SCK. The first bit (MSB)
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDO instruction. FRDO instruction
is terminated by driving CE# high (VIH).
Figure 14. Fast Read Dual-Output Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
SCK
28
30
31
2
1
0
29
...
3 - BYTE ADDRESS
SIO
INSTRUCTION = 0011 1011b
23
22 21
... 3
HIGH IMPEDANCE
SO
CE#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
6
4
2
0
6
4
2
0
6
1
7
SCK
SIO
DATA OUT 1
SO
HIGH IMPEDANCE
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7
5
3
DATA OUT 2
1
7
5
3
18
IS25CD025
DEVICE OPERATION (CONTINUED)
PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION
The Page Program (PAGE_PROG) instruction allows
up to 256 bytes data to be programmed into memory in
a single operation. The destination of the memory to be
programmed must be outside the protected memory
area set by the Block Protection (BP2, BP1, BP0) bits.
A PAGE_PROG instruction which attempts to program
into a page that is write-protected will be ignored.
Before the execution of PAGE_PROG instruction, the
Write Enable Latch (WEL) must be enabled through a
Write Enable (WREN) instruction.
The PAGE_PROG instruction code, three address
bytes and program data (1 to 256 bytes) are input via
the Sl line. Program operation will start immediately
after the CE# is brought high, otherwise the
PAGE_PROG instruction will not be executed. The
internal control logic automatically handles the
programming voltages and timing. During a program
operation, all instructions will be ignored except the
RDSR instruction. The progress or completion of the
program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in
progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the
address counter rolls over within the same page, the
previously latched data are discarded, and the last 256
bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page.
When the end of the page is reached, the address will
wrap around to the beginning of the same page. If the
data to be programmed are less than a full page, the
data of all other bytes on the same page will remain
unchanged.
Note: A program operation can alter “1”s into “0”s, but
an erase operation is required to change “0”s back to
“1”s. A byte cannot be reprogrammed without first
erasing the whole sector or block.
Figure 15. Page Program Sequence
SIO
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19
IS25CD025
DEVICE OPERATION (CONTINUED)
ERASE OPERATION
The memory array of the IS25CD025 is organized into
uniform 4 KByte sectors or 32KByte uniform blocks (a
block consists of eight adjacent sectors).
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Erase
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
WIP bit is “1”, the erase operation is still in progress. If
the WIP bit is “0”, the erase operation has been
completed.
BLOCK_ER COMMAND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 32
KByte block of the IS25CD025. Before the execution of
a BLOCK_ER instruction, the Write Enable Latch
(WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 17 for Block Erase
Sequence.(address don’t care)
A SECTOR_ER instruction erases a 4 KByte sector
Before the execution of a SECTOR_ER instruction, the
Write Enable Latch (WEL) must be set via a Write
CHIP_ER COMMAND (CHIP ERASE) OPERATION
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
A Chip Erase (CHIP_ER) instruction erases the entire
operation.
memory array of a IS25CD025. Before the execution of
CHIP_ER instruction, the Write Enable Latch (WEL)
A SECTOR_ER instruction is entered, after CE# is
must be set via a Write Enable (WREN) instruction.
pulled low to select the device and stays low during the The WEL is reset automatically after completion of a
entire instruction sequence The SECTOR_ER
chip erase operation.
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
The CHIP_ER instruction code is input via the SI.
pulled high. The internal control logic automatically
Erase operation will start immediately after CE# is
handles the erase voltage and timing. Refer to Figure
pulled high, otherwise the CHIP_ER instruction will not
16 for Sector Erase Sequence.
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
During an erase operation, all instruction will be
18 for Chip Erase Sequence.
ignored except the Read Status Register (RDSR)
instruction. The progress or completion of the erase
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IS25CD025
DEVICE OPERATION (CONTINUED)
Figure 16. Sector Erase Sequence
SIO
Figure 17. Block Erase Sequence
SIO
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IS25CD025
Figure 18. Chip Erase Sequence
SIO
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IS25CD025
ABSOLUTE MAXIMUM RATINGS (1)
-65oC to +125oC
-65oC to +125oC
Temperature Under Bias
Storage Temperature
Surface Mount Lead Soldering Temperature
Lead-free Package
Input Voltage with Respect to Ground on All Pins (2)
All Output Voltage with Respect to Ground
VCC (2)
260oC 3 Seconds
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +6.0 V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only. The functional operation of the device conditions that exceed those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number
Operating Temperature (Extended Grade)
Operating Temperature (Automotive, A1 Grade)
Operating Temperature (Automotive, A2 Grade)
Vcc Power Supply
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Rev. G
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IS25CD025
-40oC to 105oC
-40oC to 85oC
-40oC to 105oC
2.70 V – 3.60 V
23
IS25CD025
DC CHARACTERISTICS
Applicable over recommended operating range from:
TAC = -40°C to +105°C, VCC = 2.70 V to 3.60 V (unless otherwise noted).
Symbol
Parameter
ICC1
Vcc Active Read Current
ICC2
Vcc Program/Erase Current
ISB1
Vcc Standby Current CMOS
Condition
VCC = 3.60V at 33 MHz, SO =
Open
VCC = 3.60V at 33 MHz, SO =
Open
VCC = 3.60V, CE# = VCC
ISB2
Vcc Standby Current TTL
VCC = 3.60V, CE# = VIH to VCC
ILI
Input Leakage Current
VIN = 0V to VCC
o
Min
o
VIN = 0V to VCC, TAC = 0 C to 85 C
Typ
Max
Units
6
10
mA
10
15
mA
1
10
µA
2
mA
1
µA
1
µA
ILO
Output Leakage Current
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input HIgh Voltage
0.7VCC
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
2.70V < VCC <
3.60V
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Rev. G
07/31/2013
IOL = 2.1 mA
IOH = -100 µA
VCC - 0.2
V
24
IS25CD025
AC CHARACTERISTICS
Applicable over recommended operating range from VCC = 2.70 V to 3.60 V
CL = 1 TTL Gate and 10 pF (unless otherwise noted).
Symbol
fCT
fC
tRI
tFI
tCKH
tCKL
tCEH
tCS
tCH
tDS
tDH
tHS
tHD
tV
tOH
tLZ
tHZ
tDIS
tEC
tPP
tVCS
tw
Parameter
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CE# High Time
CE# Setup Time
CE# Hold Time
Data In Setup Time
Data in Hold Time
Hold Setup Time
Hold Time
Output Valid
Output Hold Time Normal Mode
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Sector/Block/Chip Erase Time
Page Program Time
VCC Set-up Time
Write Status Register time (flash bit)
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Rev. G
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Min
0
0
Typ
Max
100
33
8
8
4
4
25
10
5
2
2
15
15
8
0
2
200
200
100
7
5
50
2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
µs
ms
25
IS25CD025
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING (1)
SIO
Note: 1. For SPI Mode 0 (0,0)
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IS25CD025
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
CIN
COUT
Typ
4
8
Max
6
12
Units
pF
pF
Conditions
VIN = 0 V
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD
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Rev. G
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INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
27
IS25CD025
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (CE# must follow the voltage applied on Vcc)
until Vcc reaches the correct value:
- Vcc(min) at Power-up, and then for a further delay of
tVCE
- Vss at Power-down
Usually a simple pull-up resistor on CE# can be used
to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset (POR)
circuit is included. The logic inside the device is held
reset while Vcc is less than the POR threshold value
(Vwi) during power up, the device does not respond to
any instruction until a time delay of tPUW has elapsed
after the moment that Vcc rised above the VWI
threshold. However, the correct operation of the device
is not guaranteed if, by this time, Vcc is still below
Vcc(min). No Write Status Register, Program or Erase
instructions should be sent until the later of:
- tPUW after Vcc passed the VWI threshold
- tVCE after Vcc passed the Vcc(min) level
At Power-up, the device is in the following state:
- The device is in the Standby mode
- The Write Enable Latch (WEL) bit is reset
At Power-down, when Vcc drops from the operating
voltage, to below the Vwi, all write operations are
disabled and the device does not respond to any write
instruction.
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
V (write inhibit)
Read Access Allowed
Device fully accessible
tPUW
Time
Symbol
tVCE
*1
tPUW *1
Parameter
Vcc(min) to CE# Low
Power-Up time delay to Write instruction
*1
VWI
Write Inhibit Voltage
Note : *1. These parameters are characterized only.
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Rev. G
07/31/2013
Min.
Max.
10
1
Unit
us
10
ms
2.4
V
28
IS25CD025
PROGRAM/ERASE PERFORMANCE
Parameter
Sector Erase Time
Block Erase Time
Chip Erase Time
Page Programming Time
Unit
ms
ms
ms
ms
Typ
2
Max
7
7
7
5
Remarks
From writing erase command to erase completion
From writing erase command to erase completion
From writing erase command to erase completion
From writing program command to program completion
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Endurance
Data Retention
ESD - Human Body Model
ESD - Machine Model
Latch-Up
Min
200,000
20
2,000
200
100 + ICC1
Unit
Cycles
Years
Volts
Volts
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
Note: These parameters are characterized and are not 100% tested.
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IS25CD025
PACKAGE TYPE INFORMATION
JN
8-Pin SOIC 150mil Broad Small Outline Integrated Circuit Package (Unit: millimeters)
Note: Package dimensions are shown in mm
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Rev. G
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IS25CD025
PACKAGE TYPE INFORMATION (CONTINUED)
JD
8-pin TSSOP Package (Unit: millimeters)
Pin1
6.2
6.6
4.3
4.5
0.127
Detail A
2.9
3.1
1.00
1.05
1.05
1.20
Detail A
0.25
0.30
GAGE PLANE
0.05
0.15
0.25
0.65
0.5
0.7
00
80
Unit : millimeters
Note: Package dimensions are shown in mm
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Rev. G
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31
IS25CD025
ORDERING INFORMATION:
Density
256K
Frequency
(MHz)
100
Order Part Number
Package
IS25CD025-JNLE
IS25CD025-JDLE
IS25CD025-JNLA*
IS25CD025-JDLA*
IS25CD025-JWLE
8-pin SOIC 150mil
8-pin TSSOP
8-pin SOIC 150mil (Call Factory)
8-pin TSSOP (Call Factory)
KGD (Call Factory)
A* = A1, A2 Automotive Temperature Ranges
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