CAT5241 Quad Digital Potentiometer (POT) with 64 Taps and I2C Interface http://onsemi.com Description The CAT5241 is four Digital POTs integrated with control logic and 16 bytes of NVRAM memory. Each digital POT consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each digital POT. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a I2C serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). The CAT5241 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. Four Linear-taper Digital Potentiometers 64 Resistor Taps per Potentiometer End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW Potentiometer Control and Memory Access via I2C Interface Low Wiper Resistance, Typically 80 W Nonvolatile Memory Storage for up to Four Wiper Settings for Each Potentiometer Automatic Recall of Saved Wiper Settings at Power Up 2.5 to 6.0 Volt Operation Standby Current less than 1 mA 1,000,000 Nonvolatile WRITE Cycles 100 Year Nonvolatile Memory Data Retention 20-lead SOIC and TSSOP Packages Industrial Temperature Range These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. 20 1 SOIC−20 W SUFFIX CASE 751BJ PIN CONNECTIONS RW0 VCC 1 RL0 RW3 RH0 RL3 A0 RH3 A2 A1 RW1 Features TSSOP−20 Y SUFFIX CASE 948AQ RL1 CAT5241 A3 SCL RH1 RW2 SDA RL2 GND RH2 SOIC−20 (W) TSSOP−20 (Y) (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: CAT5241/D CAT5241 MARKING DIAGRAMS (SOIC−20) (TSSOP−20) L3B CAT5241WT −RRYMXXXX RLB CAT5241YT 3YMXXX L = Assembly Location 3 = Lead Finish − Matte−Tin B = Product Revision (Fixed as “B”) CAT5241W = Device Code T = Temperature Range (I = Industrial) − = Dash RR = Resistance 25 = 2.5 KW 10 = 10 KW 50 = 50 KW 00 = 100 KW Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXXX = Last Four Digits of Assembly Lot Number R = Resistance 1 = 2.5 KW 2 = 10 KW 4 = 50 KW 5 = 100 KW L = Assembly Location B = Product Revision (Fixed as “B”) CAT5241Y = Device Code T = Temperature Range (I = Industrial) 3 = Lead Finish − Matte−Tin Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXX = Last Three Digits of Assembly Lot Number http://onsemi.com 2 CAT5241 RH0 SCL RH2 RH3 WIPER CONTROL REGISTERS I2C BUS INTERFACE SDA RH1 RW0 RW1 RW2 A0 A1 A2 A3 NONVOLATILE DATA REGISTERS CONTROL LOGIC RW3 RL0 RL1 RL2 RL3 Figure 1. Functional Diagram SDA: Serial Data Table 1. PIN DESCRIPTION Pin (SOIC) Name 1 RW0 Wiper Terminal for Potentiometer 0 2 RL0 Low Reference Terminal for Potentiometer 0 3 RH0 High Reference Terminal for Potentiometer 0 4 A0 Device Address, LSB 5 A2 Device Address 6 RW1 Wiper Terminal for Potentiometer 1 7 RL1 Low Reference Terminal for Potentiometer 1 8 RH1 High Reference Terminal for Potentiometer 1 The CAT5241 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-OR’d with the other open drain or open collector outputs. Function A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5241. RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. 9 SDA Serial Data Input/Output 10 GND Ground 11 RH2 High Reference Terminal for Potentiometer 2 12 RL2 Low Reference Terminal for Potentiometer 2 13 RW2 Wiper Terminal for Potentiometer 2 14 SCL Bus Serial Clock 15 A3 Device Address 16 A1 Device Address 17 RH3 High Reference Terminal for Potentiometer 3 18 RL3 Low Reference Terminal for Potentiometer 3 19 RW3 Wiper Terminal for Potentiometer 3 20 VCC Supply Voltage RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. Device Operation The CAT5241 is four resistor arrays integrated with I2C serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the I2C bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer’s non-volatile data registers. Also, the device can be instructed to operate in an “increment/decrement” mode. Pin Descriptions SCL: Serial Clock The CAT5241 serial clock input pin is used to clock all data transfers into or out of the device. http://onsemi.com 3 CAT5241 Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Ratings Units Temperature Under Bias −55 to +125 C Storage Temperature Range −65 to +150 C −2.0 to +VCC +2.0 V Voltage on any Pin with Respect to VSS (Notes 1, 2) VCC with Respect to Ground −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25C) 1.0 W Lead Soldering Temperature (10 s) 300 C Wiper Current 12 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC + 1 V. Table 3. RECOMMENDED OPERATING CONDITIONS Parameter Ratings Units VCC +2.5 to +6.0 V Operating Ambient Temperature (Industrial) −40 to +85 C Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Parameter Symbol Test Conditions Min Typ Max Units RPOT Potentiometer Resistance (−00) 100 kW RPOT Potentiometer Resistance (−50) 50 kW RPOT Potentiometer Resistance (−10) 10 kW RPOT Potentiometer Resistance (−25) 2.5 kW Potentiometer Resistance Tolerance 20 % 1 % 25C, each pot 50 mW 6 mA 300 W 150 W RPOT Matching Power Rating IW Wiper Current RW Wiper Resistance IW = 3 mA @ VCC = 3 V RW Wiper Resistance IW = 3 mA @ VCC = 5 V VTERM VN Voltage on any RH or RL Pin Noise VSS = 0 V (Note 3) Resolution 80 GND VCC TBD nV/Hz 1.6 % Absolute Linearity (Note 4) RW(n)(actual)−R(n)(expected) (Note 7) 1 LSB (Note 6) Relative Linearity (Note 5) RW(n+1)−[RW(n)+LSB] (Note 7) 0.2 LSB (Note 6) TCRPOT Temperature Coefficient of RPOT (Note 3) TCRATIO Ratiometric Temp. Coefficient (Note 3) CH/CL/CW Potentiometer Capacitances (Note 3) 10/10/25 pF RPOT = 50 kW (Note 3) 0.4 MHz fc Frequency Response ppm/C 300 20 ppm/C 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 6. LSB = RTOT / 63 or (RH − RL) / 63, single pot 7. n = 0, 1, 2, ..., 63 http://onsemi.com 4 CAT5241 Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Parameter Symbol Test Conditions Min Typ Max Units fSCL = 400 kHz 1 mA VIN = GND or VCC; SDA = GND; RWX = GND (Note 8) 1 mA VIN = GND to VCC 10 mA VOUT = GND to VCC 10 mA ICC Power Supply Current ISB Standby Current (VCC = 5.0 V) ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage −1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V 0.4 V VOL1 Output Low Voltage (VCC = 3.0 V) IOL = 3 mA 8. All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground. Table 6. CAPACITANCE (Note 9) (TA = 25C, f = 1.0 MHz, VCC = +5.0 V) Symbol Parameter Test Conditions Min Typ Max Units CI/O Input/Output Capacitance (SDA) VI/O = 0 V 8 pF CIN Input Capacitance (A0, A1, A2, A3, SCL) VIN = 0 V 6 pF Max Units Clock Frequency 400 kHz Noise Suppression Time Constant at SCL, SDA Inputs 50 ns SLC Low to SDA Data Out and ACK Out 0.9 ms Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol fSCL TI (Note 9) tAA tBUF (Note 9) Parameter Min Typ Time the Bus Must Be Free Before a New Transmission Can Start 1.2 ms Start Condition Hold Time 0.6 ms tLOW Clock Low Period 1.2 ms tHIGH Clock High Period 0.6 ms tSU:STA Start Condition Setup Time (For a Repeated Start Condition) 0.6 ms tHD:DAT Data in Hold Time 0 ns tSU:DAT Data in Setup Time 100 ns tHD:STA tR (Note 9) SDA and SCL Rise Time 0.3 ms tF (Note 9) SDA and SCL Fall Time 300 ns tSU:STO tDH Stop Condition Setup Time 0.6 ms Data Out Hold Time 50 ns Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.) Parameter Symbol Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Max Units 5 ms 9. This parameter is tested initially and after a design or process change that affects the parameter. Table 9. WRITE CYCLE LIMITS (Note 10) (Over recommended operating conditions unless otherwise stated.) Symbol tWR Parameter Min Write Cycle Time Typ 10. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. http://onsemi.com 5 CAT5241 Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Reference Test Method Min Typ Max Units NEND (Note 11) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 11) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 11) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts ILTH (Notes 11, 12) Latch-Up JEDEC Standard 17 100 mA 11. This parameter is tested initially and after a design or process change that affects the parameter. 12. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:STO tSU:DAT SDA IN tBUF tDH tAA SDA OUT Figure 2. Bus Timing SCL 8TH BIT SDA ACK BYTE n tWR STOP CONDITION START CONDITION Figure 3. Write Cycle Timing SDA SCL START BIT STOP BIT Figure 4. Start/Stop Timing http://onsemi.com 6 ADDRESS CAT5241 Serial Bus Protocol The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5241 (see Figure 6). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5 V and ground are hard-wired to these pins to establish the device’s address. After the Master sends a START condition and the slave address byte, the CAT5241 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5241 will be considered a slave device in all applications. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5241 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5241 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5241 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5241 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the address of the SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 5. Acknowledge Timing http://onsemi.com 7 CAT5241 Write Operation Acknowledge Polling In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5241. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5241 acknowledges once more and the Master generates the STOP condition, at which time if a non-volatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT5241 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5241 is still busy with the write operation, no ACK will be returned. If the CAT5241 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. CAT5241 0 1 0 1 A3 A2 A1 A0 * A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. ** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins. Figure 6. Slave Address Bits SDA LINE SLAVE ADDRESS Fixed op code BUS ACTIVITY: MASTER S T A R T Variable Pot/WCR Address Data Register Address INSTRUCTION BYTE S T O P DR WCR DATA P S A C K A C K Figure 7. Write Timing http://onsemi.com 8 A C K CAT5241 Instructions and Register Description Instruction Byte The next byte sent to the CAT5241 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The P1 and P0 bits point to one of four Wiper Control Registers. The least two significant bits, R1 and R0, point to one of the four data registers of each associated potentiometer. The format is shown in Figure 9. Slave Address Byte The first byte sent to the CAT5241 from the master/ processor is called the Slave Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5241 are fixed at 0101[B] (refer to Figure 8). The next four bits, A3 − A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 − A0 input pins for the CAT5241 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 − A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Table 11. DATA REGISTER SELECTION Data Register Selected R1 R0 DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 Device Type Identifier ID3 0 ID2 ID1 1 0 Slave Address ID0 A3 A2 A1 A0 1 (LSB) (MSB) Figure 8. Identification Byte Format Instruction Opcode I3 I2 WCR/Pot Selection I1 I0 P1 P0 (MSB) Data Register Selection R1 R0 (LSB) Figure 9. Instruction Byte Format http://onsemi.com 9 CAT5241 Wiper Control and Data Registers Data Registers (DR) Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5 ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. Wiper Control Register (WCR) The CAT5241 contains four 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5241 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Instructions Four of the nine instructions are three bytes in length. These instructions are: Read Wiper Control Register – read the current wiper position of the selected potentiometer in the WCR Write Wiper Control Register – change current wiper position in the WCR of the selected potentiometer Read Data Register – read the contents of the selected Data Register Write Data Register – write a new value to the selected Data Register. Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero) Instruction Set I3 I2 I1 I0 WCR1/P1 WCR0/P0 R1 R0 Operations Read Wiper Control Register 1 0 0 1 1/0 1/0 0 0 Read the contents of the Wiper Control Register pointed to by P1−P0 Write Wiper Control Register 1 0 1 0 1/0 1/0 0 0 Write new value to the Wiper Control Register pointed to by P1−P0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by P1−P0 and R1−R0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1−P0 and R1−R0 XFR Data Register to Wiper Control Register 1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by P1−P0 and R1−R0 to its associated Wiper Control Register XFR Wiper Control Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Control Register pointed to by P1−P0 to the Data Register pointed to by R1−R0 Global XFR Data Registers to Wiper Control Registers 0 0 0 1 0 0 1/0 1/0 Transfer the contents of the Data Registers pointed to by R1−R0 of all four pots to their respective Wiper Control Registers Global XFR Wiper Control Registers to Data Register 1 0 0 0 0 0 1/0 1/0 Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1−R0 of all four pots Increment/Decrement Wiper Control Register 0 0 1 0 1/0 1/0 0 0 Instruction http://onsemi.com 10 Enable Increment/decrement of the Control Latch pointed to by P1−P0 CAT5241 The basic sequence of the three byte instructions is illustrated in Figure 11. These three-byte instructions exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a maximum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 10. These instructions transfer data between the host/processor and the CAT5241; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. 0 SDA 1 0 Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. Increment/Decrement Command The final command is Increment/Decrement (Figures 6 and 12). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5241 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal Device ID R Address T A C K I0 P1 P0 R1 R0 A C K Instruction Pot/WCR Register Opcode Address Address I3 I2 I1 S T O P Figure 10. Two-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 A I3 I2 I1 I0 P1 P0 R1 R0 A D7 D6 D5 D4 D3 D2 D1 D0 C T C K K A Device ID Internal WCR[7:0] Instruction R Pot/WCR Data Address or Opcode Address Register T Data Register D[7:0] Address A S C T K O P Figure 11. Three-Byte Instruction Sequence 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 A3 A2 A1 A0 Device ID Internal Address A C K I3 I2 I1 I0 Instruction Opcode P1 P0 R1 R0 Data Pot/WCR Address Register Address A C K I N C 1 Figure 12. Increment/Decrement Instruction Sequence http://onsemi.com 11 I N C 2 I N C n D E C 1 D E C n S T O P CAT5241 INC/DEC Command Issued tWRID SCL SDA Voltage Out RW Figure 13. Increment/Decrement Timing Limits Instruction Format Table 13. READ WIPER CONTROL REGISTER (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 0 1 P1 P0 0 0 A C K DATA 7 6 5 4 3 2 1 0 A C K S T O P A C K S T O P A C K S T O P A C K S T O P Table 14. WRITE WIPER CONTROL REGISTER (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 0 P1 P0 0 0 A C K DATA 7 6 5 4 3 2 1 0 Table 15. READ DATA REGISTER (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 1 P1 P0 R1 R0 A C K DATA 7 6 5 4 3 2 1 0 Table 16. WRITE DATA REGISTER (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 1 0 0 P1 P0 http://onsemi.com 12 R1 R0 A C K DATA 7 6 5 4 3 2 1 0 CAT5241 Instruction Format (continued) Table 17. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 0 0 0 1 0 0 R1 R0 A C K S T O P A C K S T O P A C K S T O P A C K S T O P Table 18. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 0 0 0 0 R1 R0 Table 19. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 1 1 0 P1 P0 R1 R0 Table 20. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 1 0 1 P1 P0 R1 R0 Table 21. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR) S T A R T DEVICE ADDRESSES 0 NOTE: 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 0 0 1 0 P1 P0 0 0 A C K DATA I/D I/D ... I/D I/D Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. http://onsemi.com 13 S T O P CAT5241 Table 22. ORDERING INFORMATION Orderable Part Number Resistance (kW) CAT5241WI−25−T1 2.5 CAT5241WI−10−T1 10 CAT5241WI−50−T1 50 CAT5241WI−00−T1 100 CAT5241YI−25−T2 2.5 CAT5241YI−10−T2 10 CAT5241YI−50−T2 50 CAT5241YI−00−T2 100 CAT5241WI25 2.5 CAT5241WI10 10 CAT5241WI50 50 CAT5241WI00 100 CAT5241YI25 2.5 CAT5241YI10 10 CAT5241YI50 50 CAT5241YI00 100 Lead Finish Package Shipping† SOIC (Pb−Free) 1000 / Tape & Reel TSSOP (Pb−Free) 2000 / Tape & Reel SOIC (Pb−Free) 36 Units / Tube TSSOP (Pb−Free) 74 Units / Tube Matte−Tin †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com. 14. All packages are RoHS-compliant (Lead-free, Halogen-free). 15. The standard lead finish is Matte-Tin. 16. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. http://onsemi.com 14 CAT5241 PACKAGE DIMENSIONS SOIC−20, 300 mils CASE 751BJ ISSUE O SYMBOL E1 MIN NOM MAX 2.49 2.64 A 2.36 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.41 0.51 c 0.20 0.27 0.33 D 12.60 12.80 13.00 E 10.01 10.30 10.64 E1 7.40 7.50 7.60 E 1.27 BSC e b e PIN#1 IDENTIFICATION h 0.25 L 0.40 0.75 0.81 1.27 θ 0º 8º θ1 5º 15º TOP VIEW D h q1 q A2 A h q1 L A1 END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. http://onsemi.com 15 c CAT5241 PACKAGE DIMENSIONS TSSOP20, 4.4x6.5 CASE 948AQ ISSUE A b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.50 6.60 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e L 0.65 BSC 0.45 L1 θ 0.60 0.75 1.00 REF 0º 8º e TOP VIEW D c A2 A θ1 L A1 SIDE VIEW END VIEW L1 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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