Cypress CY7C1470BV25-200BZXI 72-mbit (2 m x 36/4 m x 18) pipelined sram with noblâ ¢ architecture Datasheet

CY7C1470BV25
CY7C1472BV25
72-Mbit (2 M × 36/4 M × 18)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte Write capability
■
Single 2.5 V power supply
■
2.5 V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 3.0 ns (for 250-MHz device)
■
Clock Enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1470BV25 available in JEDEC-standard Pb-free 100-pin
TQFP and Pb-free 165-ball FBGA package. CY7C1472BV25
available in JEDEC-standard Pb-free 100-pin TQFP
■
IEEE 1149.1 JTAG Boundary Scan compatible
■
Burst capability – linear or interleaved burst order
■
“ZZ” Sleep Mode option and Stop Clock option
The CY7C1470BV25 and CY7C1472BV25 are 2.5 V,
2 M × 36/4 M × 18 synchronous pipelined burst SRAMs with No
Bus Latency™ (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read or write operations
with no wait states. The CY7C1470BV25 and CY7C1472BV25
are equipped with the advanced (NoBL) logic required to enable
consecutive read or write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent read or write
transitions. The CY7C1470BV25 and CY7C1472BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1470BV25 and BWa–BWb for
CY7C1472BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document Number: 001-15032 Rev. *K
•
198 Champion Court
•
250 MHz
200 MHz
167 MHz
Unit
3.0
450
120
3.0
450
120
3.4
400
120
ns
mA
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 25, 2013
CY7C1470BV25
CY7C1472BV25
Logic Block Diagram – CY7C1470BV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
E
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
E
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1472BV25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
BW b
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
Document Number: 001-15032 Rev. *K
E
DQ s
DQ Pa
DQ Pb
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Page 2 of 29
CY7C1470BV25
CY7C1472BV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Linear Burst Address Table ......................................... 8
Interleaved Burst Address Table ................................. 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Write Cycle Description ..................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
Performing a TAP RESET ......................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
Document Number: 001-15032 Rev. *K
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
Boundary Scan Exit Order ............................................. 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Electrical Characteristics ............................................... 18
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 19
Switching Characteristics .............................................. 20
Switching Waveforms .................................................... 21
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Package Diagrams .......................................................... 24
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Page 3 of 29
CY7C1470BV25
CY7C1472BV25
Pin Configurations
CY7C1470BV25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPb
DQb
DQb
VDDQ
VSS
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
CY7C1472BV25
(4 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 001-15032 Rev. *K
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
VSS
VDD
NC(288)
NC(144)
A
A
A
A
A
A
A
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
(2 M × 36)
NC(288)
NC(144)
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 29
CY7C1470BV25
CY7C1472BV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1470BV25 (2 M × 36)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
7
8
9
10
11
A
A
NC
CLK
CEN
WE
ADV/LD
CE1
BWc
BWb
CE3
NC/1G
A
CE2
DQPc
DQc
NC
DQc
VDDQ
BWa
VSS
VDDQ
BWd
VSS
VDD
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
VDDQ
VDD
DQc
DQc
NC
DQd
DQc
DQc
NC
DQd
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQb
NC
DQa
DQb
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC/144M
A
A
A
TDI
A1
TDO
A
A
A
R
MODE
A
A
A
TMS
A0
TCK
A
A
A
Document Number: 001-15032 Rev. *K
VSS
VDDQ
NC/288M
A
Page 5 of 29
CY7C1470BV25
CY7C1472BV25
Pin Definitions
Pin Name
A0, A1, A
I/O Type
Pin Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
Synchronous
BWa, BWb,
InputByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd Synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be driven
LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
OE
InputOutput Enable, Active LOW. Combined with the synchronous logic block inside the device to control
Asynchronous the direction of the I/O pins. When LOW, the I/O pins can behave as outputs. When deasserted HIGH,
I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[18:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[71:0]. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE must not change states during operation. When left floating
MODE defaults HIGH, to an interleaved burst order.
TDO
JTAG Serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
TDI
JTAG Serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
Input
Synchronous
TMS
Test Mode TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Select
Synchronous
Document Number: 001-15032 Rev. *K
Page 6 of 29
CY7C1470BV25
CY7C1472BV25
Pin Definitions (continued)
Pin Name
TCK
VDD
VDDQ
I/O Type
Pin Description
JTAG Clock Clock Input to the JTAG Circuitry.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for the I/O Circuitry.
VSS
Ground
NC
–
No Connects. This pin is not connected to the die.
NC (144M,
288M,
576M, 1G)
–
These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G
densities.
ZZ
Ground for the Device. Must be connected to ground of the system.
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin has must be LOW or left floating. ZZ pin has an
internal pull down.
Functional Overview
The
CY7C1470BV25
and
CY7C1472BV25
are
synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during read or write
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 3.0 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[x] can be used to conduct Byte Write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the input signal WE is
deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
Document Number: 001-15032 Rev. *K
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV25 and CY7C1472BV25 have an on-chip
burst counter that enables the user to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW to load a new address into
the SRAM, as described in the Single Read Accesses section.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst mode,
a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps
around when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enables inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25). In addition, the address for the subsequent
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25) (or a subset for Byte Write operations, see
Partial Write Cycle Description on page 10 for details) inputs is
Page 7 of 29
CY7C1470BV25
CY7C1472BV25
latched into the device and the Write is complete.
Sleep Mode
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1470BV25 and BWa,b for CY7C1472BV25)
signals. The CY7C1470BV25 and CY7C1472BV25 provides
Byte Write capability that is described in Partial Write Cycle
Description on page 10. Asserting the WE input with the selected
BW input selectively writes to only the desired bytes. Bytes not
selected during a Byte Write operation remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte Write capability has been
included to greatly simplify read, modify, or write sequences,
which can be reduced to simple Byte Write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Because the CY7C1470BV25 and CY7C1472BV25 are
common I/O devices, data must not be driven into the device
while the outputs are active. OE can be deasserted HIGH before
presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1470BV25, DQa,b/DQPa,b for CY7C1472BV25) inputs.
Doing so tri-states the output drivers. As a safety precaution, DQ
and
DQP
(DQa,b,c,d/DQPa,b,c,d
for
CY7C1470BV25,
DQa,b/DQPa,b for CY7C1472BV25) are automatically tri-stated
during the data portion of a write cycle, regardless of the state of
OE.
(MODE = GND)
Linear Burst Address Table
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Burst Write Accesses
Interleaved Burst Address Table
The CY7C1470BV25 and CY7C1472BV25 has an on-chip burst
counter that enables the user to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in Single Write Accesses on page 7.
When ADV/LD is driven HIGH on the subsequent clock rise, the
Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1470BV25, BWa,b for CY7C1472BV25) inputs must be
driven in each cycle of the burst write to write the correct bytes
of data.
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ  VDD 0.2 V
tZZS
Device operation to ZZ
ZZVDD  0.2 V
tZZREC
ZZ recovery time
ZZ  0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 001-15032 Rev. *K
Min
Max
Unit
–
120
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 8 of 29
CY7C1470BV25
CY7C1472BV25
Truth Table
The truth table for CY7C1470BV25 and CY7C1472BV25 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L–H
Tri-State
Continue Deselect Cycle
None
X
L
H
X
X
X
L
L–H
Tri-State
Read Cycle (Begin Burst)
External
L
L
L
H
X
L
L
L–H Data Out (Q)
Next
X
L
H
X
X
L
L
L–H Data Out (Q)
External
L
L
L
H
X
H
L
L–H
Tri-State
Next
X
L
H
X
X
H
L
L–H
Tri-State
External
L
L
L
L
L
X
L
L–H
Data In (D)
Write Cycle (Continue Burst)
Next
X
L
H
X
L
X
L
L–H
Data In (D)
NOP/Write Abort (Begin Burst)
None
L
L
L
L
H
X
L
L–H
Tri-State
Write Abort (Continue Burst)
Next
X
L
H
X
H
X
L
L–H
Tri-State
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tri-State
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired Byte Write Selects are asserted, see Partial Write Cycle Description on page 10 for details.
2. Write is defined by WE and BW[a:d]. See Partial Write Cycle Description on page 10 for details.
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQs and DQP[a:d] = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 001-15032 Rev. *K
Page 9 of 29
CY7C1470BV25
CY7C1472BV25
Partial Write Cycle Description
The partial write cycle description for CY7C1470BV25 and CY7C1472BV25 follows. [8, 9, 10, 11]
Function (CY7C1470BV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1472BV25)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired Byte Write Selects are asserted, see Partial Write Cycle Description for details.
9. Write is defined by WE and BW[a:d]. See Partial Write Cycle Description for details.
10. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
11. Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate write is based on which Byte Write is active.
Document Number: 001-15032 Rev. *K
Page 10 of 29
CY7C1470BV25
CY7C1472BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470BV25 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion places
an added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 2.5 V I/O logic
levels.
The CY7C1470BV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. During power up, the device comes
up in a reset state, which does not interfere with the operation of
the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP RESET
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Document Number: 001-15032 Rev. *K
During power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. During power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts the data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 16. Three of these instructions are listed as
Page 11 of 29
CY7C1470BV25
CY7C1472BV25
RESERVED and must not be used. The other five instructions
are described in this section in detail.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is executed
whenever the instruction register is loaded with all 0s. EXTEST
is not implemented in this SRAM TAP controller, and therefore
this device is not compliant to 1149.1. The TAP controller does
recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
Document Number: 001-15032 Rev. *K
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 29
CY7C1470BV25
CY7C1472BV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-15032 Rev. *K
Page 13 of 29
CY7C1470BV25
CY7C1472BV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
Document Number: 001-15032 Rev. *K
UNDEFINED
Page 14 of 29
CY7C1470BV25
CY7C1472BV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
–
ns
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
Input pulse levels ...............................................VSS to 2.5 V
1.25V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
50Ω
Output reference levels .............................................. 1.25 V
TDO
Test load termination supply voltage .......................... 1.25 V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [14]
Description
VOH1
Output HIGH Voltage
Min
Max
Unit
IOH = –1.0 mA, VDDQ = 2.5 V
Test Conditions
1.7
–
V
2.1
–
V
–
0.4
V
VOH2
Output HIGH Voltage
IOH = –100 A, VDDQ = 2.5 V
VOL1
Output LOW Voltage
IOL = 1.0 mA, VDDQ = 2.5 V
VOL2
Output LOW Voltage
IOL = 100 A, VDDQ = 2.5 V
–
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input Load Current
GND  VI  VDDQ
–5
5
A
Notes
12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
14. All voltages refer to VSS (GND).
Document Number: 001-15032 Rev. *K
Page 15 of 29
CY7C1470BV25
CY7C1472BV25
Identification Register Definitions
Instruction Field
CY7C1470BV25 (2 M × 36)
Revision Number (31:29)
000
Device Depth (28:24)
01011
Description
Describes the version number
Reserved for internal use
Architecture/Memory Type (23:18)
001000
Defines memory type and architecture
Bus Width/Density (17:12)
100100
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
ID Register Presence Indicator (0)
1
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order – 165-ball FBGA
71
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-15032 Rev. *K
Page 16 of 29
CY7C1470BV25
CY7C1472BV25
Boundary Scan Exit Order
(2 M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
2
D1
22
P2
41
J11
61
B7
42
K10
62
B6
3
E1
23
R4
43
J10
63
A6
4
D2
24
P6
44
H11
64
B5
5
E2
25
R6
45
G11
65
A5
6
F1
26
R8
46
F11
66
A4
7
G1
27
P3
47
E11
67
B4
8
F2
28
P4
48
D10
68
B3
9
G2
29
P8
49
D11
69
A3
10
J1
30
P9
50
C11
70
A2
11
K1
31
P10
51
G10
71
B2
12
L1
32
R9
52
F10
13
J2
33
R10
53
E10
14
M1
34
R11
54
A9
15
N1
35
N11
55
B9
16
K2
36
M11
56
A10
17
L2
37
L11
57
B10
18
M2
38
M10
58
A8
19
R1
39
L10
59
B8
20
R2
40
K11
60
A7
Document Number: 001-15032 Rev. *K
Page 17 of 29
CY7C1470BV25
CY7C1472BV25
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
Commercial
DC to Outputs in Tri-State .................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Industrial
Ambient
Temperature
VDD
VDDQ
0 °C to +70 °C 2.5 V – 5% / +5% 2.5 V – 5% to
VDD
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [15, 16]
Description
Test Conditions
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
–
V
–
0.4
V
1.7
VDD + 0.3
V
–0.3
0.7
V
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Output Leakage Current
GND  VI  VDDQ, Output Disabled
–5
5
A
VDD Operating Supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
–
450
mA
–
450
mA
6.0 ns cycle,
167 MHz
–
400
mA
4.0 ns cycle,
250MHz
–
200
mA
5.0 ns cycle,
200 MHz
–
200
mA
6.0 ns cycle,
167 MHz
–
200
mA
–
120
mA
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
For 2.5 V I/O
VOH
Output HIGH Voltage
For 2.5 V I/O, IOH =1.0 mA
VOL
Output LOW Voltage
For 2.5 V I/O, IOL =1.0 mA
VIH
Input HIGH Voltage [15]
For 2.5 V I/O
VIL
Input LOW Voltage
[15]
For 2.5 V I/O
IX
Input Current of ZZ
IOZ
IDD
[17]
4.0 ns cycle,
250 MHz
5.0 ns cycle,
200 MHz
ISB1
ISB2
Automatic CE Power Down
Current – TTL Inputs
Automatic CE Power Down
Current – CMOS Inputs
Max. VDD, Device Deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected, All speed
VIN  0.3 V or VIN > VDDQ 0.3 V, grades
f=0
Notes
15. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
16. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15032 Rev. *K
Page 18 of 29
CY7C1470BV25
CY7C1472BV25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [15, 16]
ISB3
Description
Automatic CE Power Down
Current – CMOS Inputs
ISB4
Automatic CE Power Down
Current – TTL Inputs
Test Conditions
Min
Max
Unit
Max. VDD, Device Deselected, 4.0 ns cycle,
VIN  0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
5.0 ns cycle,
200 MHz
–
200
mA
–
200
mA
6.0 ns cycle,
167 MHz
–
200
mA
All speed
grades
–
135
mA
Max. VDD, Device Deselected,
VIN  VIH or VIN  VIL, f = 0
Capacitance
Parameter [18]
Description
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
Control input capacitance
CCLK
CIO
TA = 25 °C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
6
6
pF
5
5
pF
8
8
pF
Clock input capacitance
6
6
pF
Input/Output capacitance
5
5
pF
Thermal Resistance
Parameter [18]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
24.63
16.3
C/W
2.28
2.1
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 1538 
VL = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
18. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-15032 Rev. *K
Page 19 of 29
CY7C1470BV25
CY7C1472BV25
Switching Characteristics
Over the Operating Range
Parameter [19, 20]
tPower[21]
Description
VCC(typical) to the first access
Read or Write
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
4.0
–
5.0
–
6.0
–
ns
Clock
tCYC
Clock cycle time
FMAX
Maximum operating frequency
–
250
–
200
–
167
MHz
tCH
Clock HIGH
2.0
–
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.0
–
2.2
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.0
–
3.4
ns
tOEV
OE LOW to output valid
–
3.0
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.3
–
1.5
–
ns
tCHZ
Clock to high Z [22, 23, 24]
–
3.0
–
3.0
–
3.4
ns
[22, 23, 24]
tCLZ
Clock to low Z
1.3
–
1.3
–
1.5
–
ns
tEOHZ
OE HIGH to output high Z[22, 23,
–
3.0
–
3.0
–
3.4
ns
OE LOW to output low Z [22, 23, 24]
0
–
0
–
0
–
ns
tEOLZ
24]
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tWES
WE, BWx setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tALS
ADV/LD setup before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tCES
Chip select setup
1.4
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tCEH
Chip Select hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
Hold Times
Notes
19. Timing reference is 1.25 V when VDDQ = 2.5 V.
20. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted.
21. This part has a voltage regulator internally; tpower is the time power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
22. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage.
23. At any supplied voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 001-15032 Rev. *K
Page 20 of 29
CY7C1470BV25
CY7C1472BV25
Switching Waveforms
Figure 5. Read/Write Timing [25, 26, 27]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW x
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH,CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document Number: 001-15032 Rev. *K
Page 21 of 29
CY7C1470BV25
CY7C1472BV25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [28, 29, 30]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 7. ZZ Mode Timing [31, 32]
CLK
t
ZZ
I
t
ZZ
ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
28. For this waveform ZZ is tied LOW.
29. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH,CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
30. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
31. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.
32. IOs are in High Z when exiting ZZ sleep mode.
Document Number: 001-15032 Rev. *K
Page 22 of 29
CY7C1470BV25
CY7C1472BV25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
200
Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
CY7C1470BV25-167AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1470BV25-167BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Industrial
CY7C1470BV25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1472BV25-200AXC
CY7C1470BV25-200AXI
250
Industrial
CY7C1470BV25-200BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Industrial
CY7C1470BV25-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1470BV25-250BZXC
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1470BV25-250AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
Ordering Code Definitions
CY 7
C 147X B V25 - XXX XX X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
AX = 100-pin TQFP
BZX = 165-ball FBGA
Frequency Range: XXX = 167 MHz or 200 MHz or 250 MHz
VDD: V25 = 2.5 V
Die Revision
147X = 1470 or 1472
1470 = PL, 2 Mb × 36 (72 Mb)
1472 = PL, 4 Mb × 18 (72 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-15032 Rev. *K
Page 23 of 29
CY7C1470BV25
CY7C1472BV25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 001-15032 Rev. *K
Page 24 of 29
CY7C1470BV25
CY7C1472BV25
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *D
Document Number: 001-15032 Rev. *K
Page 25 of 29
CY7C1470BV25
CY7C1472BV25
Acronyms
Document Conventions
Acronym
Description
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
EIA
Electronic Industries Alliance
FBGA
Fine-Pitch Ball Grid Array
I/O
Input/Output
JEDEC
Joint Electron Devices Engineering Council
JTAG
Joint Test Action Group
LSB
Least Significant Bit
MSB
Most Significant Bit
OE
Output Enable
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-15032 Rev. *K
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
µA
microampere
mA
milliampere
mm
millimeter
ms
millisecond
MHz
megahertz
ns
nanosecond

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 26 of 29
CY7C1470BV25
CY7C1472BV25
Document History Page
Document Title: CY7C1470BV25/CY7C1472BV25, 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-15032
Orig. of
Change
Rev.
ECN No.
Issue Date
**
1032642
See ECN
*A
1562503
See ECN
VKN /
AESA
Updated Features (Removed 1.8 V I/O supply information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed 1.8 V I/O
supply information).
Removed the section “1.8 V TAP AC Test Conditions”.
Removed the section “1.8 V TAP AC Output Load Equivalent”.
Updated TAP DC Electrical Characteristics and Operating Conditions
(Removed 1.8 V I/O supply information).
Updated Electrical Characteristics (Removed 1.8 V I/O supply information).
Updated AC Test Loads and Waveforms (Removed 1.8 V I/O supply
information).
Updated Switching Characteristics (Removed 1.8 V I/O supply information).
*B
1897447
See ECN
VKN /
AESA
Updated Electrical Characteristics (Added Note 17 and referred the same note
in IDD parameter).
*C
2082487
See ECN
VKN
*D
2159486
See ECN
VKN /
PYRS
*E
2898663
03/24/2010
NJY
Updated Ordering Information (Removed inactive parts from Ordering
Information table).
Updated Package Diagrams.
*F
2905460
04/06/2010
VKN
Updated Ordering Information (Removed inactive part numbers
CY7C1470BV25-167BZC, CY7C1470BV25-167BZI,
CY7C1470BV25-167BZXC, CY7C1470BV25-200BZC,
CY7C1472BV25-250BZC, CY7C1474BV25-167BGC,
CY7C1474BV25-167BGI, CY7C1474BV25-200BGC,
CY7C1474BV25-200BGI, CY7C1474BV25-200BGXI from the ordering
information table).
*G
3061663
10/15/2010
NJY
Updated Ordering Information (Removed pruned parts
CY7C1472BV25-200BZI, CY7C1472BV25-200BZIT from the ordering
information table) and added Ordering Code Definitions.
Updated Package Diagrams.
*H
3207526
03/28/2011
NJY
Updated Ordering Information (updated part numbers).
Updated Package Diagrams.
Updated in new template.
*I
3257192
05/14/2011
NJY
Updated Ordering Information (updated part numbers).
Added Acronyms and Units of Measure.
Document Number: 001-15032 Rev. *K
Description of Change
VKN /
New data sheet.
KKVTMP
Changed status from Preliminary to Final.
Minor Change (Moved to the external web).
Page 27 of 29
CY7C1470BV25
CY7C1472BV25
Document History Page (continued)
Document Title: CY7C1470BV25/CY7C1472BV25, 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-15032
Rev.
ECN No.
Issue Date
*J
3545503
03/08/2012
*K
3912915
02/25/2013
Document Number: 001-15032 Rev. *K
Orig. of
Change
Description of Change
PRIT / NJY Updated Features (Removed CY7C1474BV25 related information).
Updated Functional Description (Removed CY7C1474BV25 related
information).
Removed Logic Block Diagram – CY7C1474BV25.
Updated Pin Configurations (Removed CY7C1474BV25 related information).
Updated Functional Overview (Removed CY7C1474BV25 related
information).
Updated Truth Table (Removed CY7C1474BV25 related information).
Updated Partial Write Cycle Description (Removed CY7C1474BV25 related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1472BV25 and CY7C1474BV25 related information).
Updated Identification Register Definitions (Removed CY7C1472BV25 and
CY7C1474BV25 related information).
Updated Scan Register Sizes (Removed Bit Size (× 18) and Bit Size (× 72)
columns).
Removed “Boundary Scan Exit Order (4 M × 18)” and “Boundary Scan Exit
Order (1 M × 72)”.
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams
Replaced IO with I/O in all instances across the document.
PRIT
Updated Ordering Information:
Added part number CY7C1470BV25-250AXI.
Page 28 of 29
CY7C1470BV25
CY7C1472BV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15032 Rev. *K
Revised February 25, 2013
Page 29 of 29
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.