NSC LM3676SDX-1.8 2mhz, 600ma step-down dc-dc converter with mode control Datasheet

LM3676 2MHz, 600mA Step-Down DC-DC Converter with
Mode Control
General Description
Features
The LM3676 step-down DC-DC converter is optimized for
powering low voltage circuits from a single Li-Ion cell battery
and input voltage rails from 2.9V to 5.5V. It provides up to
600mA load current, over the entire input voltage range.
There are several different fixed voltage output options available as well as an adjustable output voltage version.
The LM3676 has a mode-control pin that allows the user to
select continuous Forced PWM mode over the complete load
range or an intelligent PFM-PWM mode that changes modes
depending on the load. PWM mode offers superior efficiency
under high load conditions (>100mA) and the lowest output
noise performance. In Auto mode, PFM-PWM, hysteretic
PFM extends the battery life through reduction of the quiescent current to 16µA (typ.) during light loads and system
standby.
The LM3676 is available in a 8-lead non-pullback LLP package in leaded (PB) and lead-free (NO PB) versions. A high
switching frequency of 2 MHz (typ) allows use of tiny surfacemount components, an inductor and two ceramic capacitors.
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16 µA typical quiescent current
600 mA maximum load capability
2 MHz PWM fixed switching frequency (typ)
Automatic PFM/PWM mode switching or Forced PWM
mode
Available in fixed output voltages and adjustable version
8-Lead non-pullback LLP package
Internal synchronous rectification for high efficiency
Internal soft start
0.01 µA typical shutdown current
Operates from a single Li-Ion cell battery
Only three tiny surface-mount external components
required (one inductor, two ceramic capacitors)
Current overload and Thermal shutdown protection
Applications
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Mobile phones
PDAs
MP3 players
W-LAN
Portable instruments
Digital still cameras
Portable Hard disk drives
Typical Application Circuits
20176401
FIGURE 1. Typical Application Circuit
© 2007 National Semiconductor Corporation
201764
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LM3676 2MHz, 600mA Step-Down DC-DC Converter with Mode Control
December 2006
LM3676
20176431
FIGURE 2. Typical Application Circuit for ADJ version
Connection Diagram and Package Mark Information
20176402
FIGURE 3.
LLP8 Package NS Package Number SDA08A
Pin Descriptions (8-Lead LLP)
Pin #
Name
Description
1
PGND
Power Ground Pin.
2
SW
Switching node connection to the internal PFET switch and NFET synchronous rectifier.
3
MODE
Mode Control Pin: > 1.0V selects continous PWM mode ; <0.4V selects Auto (PFM-PWM)
mode. Do not leave this pin floating.
4
FB
Feedback analog input. Connect directly to the output filter capacitor for fixed voltage
versions. For adjustable version external resistor dividers are required (Figure 2). The
internal resistor dividers are disabled for the adjustable version.
5
EN
Enable pin. The device is in shutdown mode when voltage to this pin is <0.4V and enabled
when >1.0V. Do not leave this pin floating.
6
NC
Not Connected. Leave Pin Floating. Do Not Connect to other pins
7
SGND
8
VIN
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Signal Ground Pin.
Power Supply input. Connect to the input filter capacitor (Figure 1).
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LM3676
Ordering Information (8-Lead LLP)
Voltage
Option
ADJ
Order Number
Spec
LM3676SD-ADJ
NOPB
LM3676SDX-ADJ
NOPB
Package Marking
1000 units, Tape-and-Reel
S008B
LM3676SD-ADJ
LM3676SDX-ADJ
1.5
NOPB
1000 units, Tape-and-Reel
LM3676SDX-1.5
NOPB
1000 units, Tape-and-Reel
S007B
LM3676SDX-1.5
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
LM3676SD-1.8
NOPB
LM3676SDX-1.8
NOPB
1000 units, Tape-and-Reel
S009B
LM3676SD-1.8
LM3676SDX-1.8
3.3
4500 units, Tape-and-Reel
4500 units, Tape-and-Reel
LM3676SD-1.5
LM3676SD-1.5
1.8
Supplied As
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
LM3676SD-3.3
NOPB
LM3676SDX-3.3
NOPB
1000 units, Tape-and-Reel
S010B
LM3676SD-3.3
LM3676SDX-3.3
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
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LM3676
Human Body Model
Machine Model
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN Pin: Voltage to GND
FB, SW, EN, Mode Pin:
Continuous Power Dissipation
(Note 3)
Junction Temperature (TJ-MAX)
Storage Temperature Range
Maximum Lead Temperature
(Soldering, 10 sec.)
ESD Rating (Note 4)
2 kV
200V
Operating Ratings (Notes 1, 2)
−0.2V to 6.0V
(GND−0.2V) to
(VIN + 0.2V)
Internally Limited
Input Voltage Range
2.9V to 5.5V
Recommended Load Current
0mA to 600 mA
Junction Temperature (TJ) Range
−30°C to +125°C
Ambient Temperature (TA) Range (Note −30°C to +85°C
5)
+125°C
−65°C to +150°C
260°C
Thermal Properties
Junction-to-Ambient Thermal
Resistance (θJA) for 4 layer
board (Note 6)
56°C/W
Electrical Characteristics
(Notes 2, 8, 9) Limits in standard typeface are for TJ = 25°C. Limits in boldface type
apply over the full operating junction temperature range (−30°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to
the LM3676SD with VIN = 3.6V
Symbol
VFB
Parameter
Condition
Feedback Voltage (Fixed / Adj) (Note 11)
Min
Typ
-4
Max
Units
+4
%
Line Regulation
2.9V ≤ VIN ≤ 5.5V
IO = 10 mA
0.031
%/V
Load Regulation
100 mA ≤ IO ≤ 600 mA
VIN= 3.6V
0.0013
%/mA
VREF
Internal Reference Voltage
ISHDN
Shutdown Supply Current
EN = 0V
0.5
IQ
DC Bias Current into VIN
No load, device is not switching
(FB forced higher than
programmed output voltage)
RDSON (P)
RDSON (N)
ILIM
Switch Peak Current Limit (Note 7)
VIH
Logic High Input for EN and Mode Pin
VIL
Logic Low Input for EN and Mode Pin
IEN
Enable (EN) Input Current
IMode
Mode Pin Input Current
FOSC
Internal Oscillator Frequency
V
0.01
2
µA
16
35
µA
Pin-Pin Resistance for PFET
380
500
mΩ
Pin-Pin Resistance for NFET
250
400
mΩ
1020
1200
mA
Open Loop
830
V
1.0
0.01
PWM Mode
1.6
0.4
V
1
µA
0.01
1
µA
2
2.6
MHz
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see
the Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and disengages at
TJ= 130°C (typ.).
Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 5: In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in
the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA) in the application, as given by the following equation:TA-MAX= TJ-MAX
− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at different ambient temperatures.
Note 6: Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care
must be given to thermal dissipation issues in board design. Specified value of 130 °C/W for LLP is based on a 4 layer, 4" x 3", 2/1/1/2 oz. Cu board as per JEDEC
standards is used.
Note 7: Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects
open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor
current measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 8: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: The parameters in the electrical characteristic table are tested at VIN= 3.6V unless otherwise specified. For performance over the input voltage range
refer to datasheet curves.
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LM3676
Note 10: ADJ version is configured to 1.5V output.
Note 11: Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V.
Dissipation Rating Table
θJA
TA≤ 25°C
Power Rating
TA= 60°C
Power Rating
TA= 85°C
Power Rating
56°C/W (4 layer board) 8 Lead nonpullback LLP package
1.78W
1.16W
714mW
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LM3676
Block Diagram
20176418
FIGURE 4. Simplified Functional Diagram
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LM3676
Typical Performance Characteristics
Circuit of LM3676SD, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted.
Quiescent Supply Current vs. Supply Voltage
Shutdown Current vs. Temp
20176405
20176404
Feedback Bias Current vs. Temp
Switching Frequency vs. Temperature
20176440
20176447
RDS(ON) vs. Temperature
Open/Closed Loop Current Limit vs. Temperature
20176433
20176448
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LM3676
Output Voltage vs. Supply Voltage
(VOUT = 1.5V)
Output Voltage vs. Temperature
(VOUT = 1.5V)
20176429
20176406
Output Voltage vs. Output Current
(VOUT = 1.5V)
Line Transient Response
VOUT = 1.5V (PWM Mode)
20176412
20176407
Efficiency vs. Output Current
(VOUT = 1.5V, L = 2.2 µH)
Efficiency vs. Output Current
(VOUT = 3.3V, L = 2.2 µH)
20176441
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20176442
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LM3676
Load Transient Response (VOUT = 1.5V)
(PFM Mode 0.5mA to 50mA)
Load Transient Response (VOUT = 1.5V)
(PFM Mode 50mA to 0.5mA)
20176414
20176415
Mode Change by Load Transients
VOUT = 1.5V (PFM to PWM)
Mode Change by Load Transients
VOUT = 1.5V (PWM to PFM)
20176420
20176421
Mode Change by Mode Pin
VOUT = 1.5V (PFM to PWM)
Mode Change by Mode Pin
VOUT = 1.5V (PWM to PFM)
20176454
20176455
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LM3676
Load Transient Response
VOUT = 1.5V (PWM Mode)
Start Up into PWM Mode
VOUT = 1.5V (Output Current= 300mA)
20176413
20176424
Start Up into PFM Mode
VOUT = 1.5V (Output Current= 1mA)
20176419
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DEVICE INFORMATION
The LM3676, a high efficiency step down DC-DC switching
buck converter, delivers a constant voltage from a single LiIon battery and input voltage rails from 2.9V to 5.5V to
portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, the
LM3676 has the ability to deliver up to 600 mA depending on
the input voltage, output voltage, ambient temperature and
the inductor chosen.
There are three modes of operation depending on the current
required and Mode pin - PWM (Pulse Width Modulation), PFM
(Pulse Frequency Modulation), and shutdown. The device
operates in PWM mode if the load current > 80 mA or when
the Mode pin is set high. When the mode pin is set low, Auto
mode, lighter load current causes the device to automatically
switch into PFM for reduced current consumption (IQ = 16 µA
typ) and prolong battery life . Shutdown mode turns off the
device, offering the lowest current consumption
(ISHUTDOWN = 0.01 µA typ).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. As shown in Figure 1, only three external power
components are required for implementation.
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage
is 2.9V or higher.
20176423
CIRCUIT OPERATION
During the first portion of each switching cycle, the control
block in the LM3676 turns on the internal PFET switch. This
allows current to flow from the input through the inductor to
the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field.
During the second portion of each cycle, the controller turns
the PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output
filter capacitor and load, which ramps the inductor current
down with a slope of - VOUT/L.
The output filter stores charge when the inductor current is
high, and releases it when inductor current is low, smoothing
the voltage across the load.
The output voltage is regulated by modulating the PFET
switch on time to control the average current sent to the load.
The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier
at the SW pin to a low-pass filter formed by the inductor and
output filter capacitor. The output voltage is equal to the average voltage at the SW pin.
FIGURE 5. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, the LM3676 uses an internal NFET as
a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
Current Limiting
A current limit feature allows the LM3676 to protect itself and
external components during overload conditions. PWM mode
implements current limiting using an internal comparator that
trips at 1020 mA (typ). If the output is shorted to ground the
device enters a timed current limit mode where the NFET is
turned on for a longer duration until the inductor current falls
below a low threshold. This allows the inductor current more
time to decay, thereby preventing runaway.
PFM OPERATION
At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply current to
maintain high efficiency.
The part automatically transitions into PFM mode when either
of two conditions occurs for a duration of 32 or more clock
cycles:
A. The NFET current reaches zero.
B. The peak PMOS switch current drops below the IMODE
level, (Typically IMODE < 30mA + VIN/42 Ω ).
MODE PIN
Setting the Mode pin low (<0.4V) places the LM3676 in Auto
mode. During Auto mode the device automatically switches
between PFM-PWM depending on the load. Setting Mode
high (>1.0V) places the part in Forced PWM. The part is in
forced PWM regardless of the load. Do not leave the Mode
pin floating.
PWM OPERATION
During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows
the converter to achieve good load and line regulation. The
DC gain of the power stage is proportional to the input voltage.
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LM3676
To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced.
While in PWM mode, the output voltage is regulated by
switching at a constant frequency and then modulating the
energy per cycle to control power to the load. At the beginning
of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the
control logic turns off the switch. The current limit comparator
can also turn off the switch in case the current limit of the
PFET is exceeded. Then the NFET switch is turned on and
the inductor current ramps down. The next cycle is initiated
by the clock turning off the NFET and turning on the PFET.
Operation Description
LM3676
is turned on. It remains on until the output voltage reaches the
‘high’ PFM threshold or the peak current exceeds the IPFM
level set for PFM mode. The typical peak current in PFM mode
is: IPFM = 112mA + VIN/27Ω .
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 8), the
PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘sleep’ mode is 16µA (typ), which allows the part to achieve
high efficiency under extremely light load conditions.
If the load current should increase during PFM mode (see
Figure 8) causing the output voltage to fall below the ‘low2’
PFM threshold, the part will automatically transition into fixedfrequency PWM mode. When VIN =2.9V the part transitions
from PWM to PFM mode at ~35mA output current and from
PFM to PWM mode at ~85mA , when VIN=3.6V, PWM to PFM
transition happens at ~50mA and PFM to PWM transition
happens at ~100mA, when VIN =4.5V, PWM to PFM transition
happens at ~65mA and PFM to PWM transition happens at
~115mA.
20176422
FIGURE 6. Typical PFM Operation
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between ~0.6% and ~1.7% above the
nominal PWM output voltage. If the output voltage is below
the ‘high’ PFM comparator threshold, the PMOS power switch
20176403
FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode
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SOFT START
The LM3676 has a soft-start circuit that limits in-rush current
during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from
logic low to logic high after Vin reaches 2.9V. Soft start is implemented by increasing switch current limit in steps of 70mA,
140mA, 280mA and 1020mA (typical switch current limit). The
start-up time thereby depends on the output capacitor and
load current demanded at start-up. Typical start-up times with
a 10µF output capacitor and 300mA load is 400µs and with
1mA load is 275µs.
• VOUT: output voltage (volts)
• VFB : feedback voltage = 0.5V
• R1: feedback resistor from VOUT to FB
• R2: feedback resistor from FB to GND
For any output voltage greater than or equal to 1.1V, a zero
must be added around 45 kHz for stability. The formula for
calculation of C1 is:
LDO - LOW DROP OUT OPERATION
The LM3676-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support of
the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the
device operates near 100% duty cycle, output voltage ripple
is approximately 25 mV.
The minimum input voltage needed to support the output voltage is
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
• ILOAD
• RDSON, PFET
• RINDUCTOR
For output voltages higher than 2.5V, a pole must be placed
at 45 kHz as well. If the pole and zero are at the same frequency the formula for calculation of C2 is:
Load current
The formula for location of zero and pole frequency created
by adding C1 and C2 is given below. By adding C1, a zero as
well as a higher frequency pole is introduced.
Drain to source resistance of PFET
switch in the triode region
Inductor resistance
Application Information
OUTPUT VOLTAGE SELECTION FOR LM3676-ADJ
The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT
to FB, then to GND. VOUT is adjusted to make the voltage at
FB equal to 0.5V. The resistor from FB to GND (R2) should
be 200 kΩ to keep the current drawn through this network well
See the "LM3676-ADJ configurations for various VOUT" table.
LM3676-ADJ Configurations For Various VOUT (Circuit of Figure 2)
VOUT(V)
R1(kΩ)
R2 (kΩ)
C1 (pF)
C2 (pF)
L (µH)
CIN (µF)
COUT(µF)
1.1
240
200
15
none
2.2
4.7
10
1.2
280
200
12
none
2.2
4.7
10
1.3
320
200
12
none
2.2
4.7
10
1.5
357
178
10
none
2.2
4.7
10
1.6
442
200
8.2
none
2.2
4.7
10
1.7
432
178
8.2
none
2.2
4.7
10
1.8
464
178
8.2
none
2.2
4.7
10
1.875
523
191
6.8
none
2.2
4.7
10
2.5
402
100
8.2
none
2.2
4.7
10
2.8
464
100
8.2
33
2.2
4.7
10
3.3
562
100
6.8
33
2.2
4.7
10
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LM3676
below the 16 µA quiescent current level (PFM mode) but large
enough that it is not susceptible to noise. If R2 is 200 kΩ, and
VFB is 0.5V, the current through the resistor feedback network
will be 2.5 µA. The output voltage of the adjustable parts
ranges from 1.1V to 3.3V.
The formula for output voltage selection is:
SHUTDOWN MODE
Setting the EN input pin low (<0.4V) places the LM3676 in
shutdown mode. During shutdown the PFET switch, NFET
switch, reference, control and bias circuitry of the LM3676 are
turned off. Setting EN high (>1.0V) enables normal operation.
It is recommended to set EN pin low to turn off the LM3676
during system power up and undervoltage conditions when
the supply is less than 2.9V. Do not leave the EN pin floating.
LM3676
A 2.2 µH inductor with a saturation current rating of at least
1200 mA is recommended for most applications.The
inductor’s resistance should be less than 0.3Ω for good efficiency. Table one lists suggested inductors and suppliers. For
low-cost applications, an unshielded bobbin inductor could be
considered. For noise critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay
out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded
inductor, in the event that noise from low-cost bobbin models
is unacceptable.
INDUCTOR SELECTION
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current
ripple should be small enough to achieve the desired output
voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention
must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum
ambient temperature of application should be requested from
the manufacturer. The minimum value of inductance to
guarantee good performance is 1.76µH at ILIM (typ) dc
current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred.
There are two methods to choose the inductor saturation current rating.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most
applications. Place the input capacitor as close as possible to
the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not
use Y5V. DC bias characteristics of ceramic capacitors must
be considered when selecting case sizes like 0805 and 0603.
The minimum input capacitance to guarantee good performance is 2.2µF at 3V dc bias; 1.5µF at 5V dc bias
including tolerances and over ambient temperature
range. The input filter capacitor supplies current to the PFET
switch of the LM3676 in the first half of each cycle and reduces voltage ripple imposed on the input power source. A
ceramic capacitor’s low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating.
The input current ripple can be calculated as:
Method 1:
The saturation current should be greater than the sum of the
maximum load current and the worst case average to peak
inductor current. This can be written as
•
•
•
•
IRIPPLE: average to peak inductor current
IOUTMAX: maximum load current (600mA)
VIN: maximum input voltage in application
L : min inductor value including worst case tolerances
(30% drop can be considered for method 1)
• f : minimum switching frequency (1.6Mhz)
• VOUT: output voltage
Method 2:
A more conservative and recommended approach is to
choose an inductor that has a saturation current rating greater
than the maximum current limit of 1200mA.
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Model
Vendor
Dimensions LxWxH(mm)
D.C.R (max)
DO3314-222MX
Coilcraft
3.3 x 3.3 x 1.4
200 mΩ
LPO3310-222MX
Coilcraft
3.3 x 3.3 x 1.0
150 mΩ
ELL5GM2R2N
Panasonic
5.2 x 5.2 x 1.5
53 mΩ
CDRH2D14-2R2
Sumida
3.2 x 3.2 x 1.55
94 mΩ
Voltage peak-to-peak ripple due to ESR can be expressed as
follow:
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the rms (root
mean squared) value can be used to get an approximate value of peak-to-peak ripple.
The peak-to-peak ripple voltage, rms value can be expressed
as follow:
OUTPUT CAPACITOR SELECTION
A ceramic output capacitor of 10 µF, 6.3V is sufficient for most
applications. Use X7R or X5R types; do not use Y5V. DC bias
characteristics of ceramic capacitors must be considered
when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc
bias curves should be requested from them as part of the capacitor selection process.
The minimum output capacitance to guarantee good performance is 5.75µF at 1.8V dc bias including tolerances
and over ambient temperature range. The output filter capacitor smoothes out current flow from the inductor to the
load, helps maintain a steady output voltage during transient
load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and
sufficiently low ESR to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be
calculated as:
Voltage peak-to-peak ripple due to capacitance can be expressed as follow:
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the
output capacitor (RESR).
The RESR is frequency dependent (as well as temperature
dependent); make sure the value used for calculations is at
the switching frequency of the part.
TABLE 2. Suggested Capacitors and Their Suppliers
Model
Type
Vendor
Voltage Rating
Case Size
Inch (mm)
4.7 µF for CIN
C2012X5R0J475K
Ceramic, X5R
TDK
6.3V
0805 (2012)
JMK212BJ475K
Ceramic, X5R
Taiyo-Yuden
6.3V
0805 (2012)
GRM21BR60J475K
Ceramic, X5R
Murata
6.3V
0805 (2012)
C1608X5R0J475K
Ceramic, X5R
TDK
6.3V
0603 (1608)
10 µF for COUT
GRM21BR60J106K
Ceramic, X5R
Murata
6.3V
0805 (2012)
JMK212BJ106K
Ceramic, X5R
Taiyo-Yuden
6.3V
0805 (2012)
C2012X5R0J106K
Ceramic, X5R
TDK
6.3V
0805 (2012)
C1608X5R0J106K
Ceramic, X5R
TDK
6.3V
0603 (1608)
15
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LM3676
TABLE 1. Suggested Inductors and Their Suppliers
LM3676
currents from circulating through the ground plane. It also
reduces ground bounce at the LM3676 by giving it a lowimpedance ground connection. Connect SGND to PGND
at one single point within the board layout.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
5. Route noise sensitive traces, such as the voltage
feedback path, away from noisy traces between the
power components. The voltage feedback trace must
remain close to the LM3676 circuit and should be direct
but should be routed opposite to noisy components. This
reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the
feedback trace on another layer and to have a ground
plane between the top layer and layer on which the
feedback trace is routed. In the same manner for the
adjustable part it is desired to have the feedback dividers
on the bottom layer.
6. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noisesensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place
the DC-DC converter on one corner of the board, arrange the
CMOS digital circuitry around it (since this also generates
noise), and then place sensitive preamplifiers and IF stages
on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is postregulated to reduce conducted noise, using low-dropout
linear regulators.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability.
Good layout for the LM3676 can be implemented by following
a few simple design rules below. Refer to Figure 8 for top layer
board layout.
1. Place the LM3676, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching
currents and act as antennas. Following this rule reduces
radiated noise. Special care must be given to place the
input filter capacitor very close to the VIN and GND pin.
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor
through the LM3676 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground through the LM3676 by the inductor to
the output filter capacitor and then back through ground
forming a second current loop. Routing these loops so
the current curls in the same direction prevents magnetic
field reversal between the two half-cycles and reduces
radiated noise.
3. Connect the ground pins of the LM3676 and filter
capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this
to the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
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16
LM3676
20176464
FIGURE 8. Top layer of board layout for LLP
17
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LM3676
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead LLP Package
NS Package Number SDA08A
www.national.com
18
LM3676
Notes
19
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LM3676 2MHz, 600mA Step-Down DC-DC Converter with Mode Control
Notes
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