LINER LTC1857 16-bit, 1msps 8-channel differential â±10.24v input softspan adc with wide input common mode range Datasheet

Features
LTC2335-16
16-Bit, 1Msps 8-Channel
Differential ±10.24V Input SoftSpan ADC
with Wide Input Common Mode Range
Description
1Msps Throughput
nn ±1LSB INL (Maximum)
nn Guaranteed 16-Bit, No Missing Codes
nn Differential, Wide Common Mode Range Inputs
nn 8-Channel Multiplexer with SoftSpan Input Ranges:
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
nn 94.4dB Single-Conversion SNR (Typical)
nn −109dB THD (Typical) at f = 2kHz
IN
nn 118dB CMRR, 125dB Active Crosstalk (Typical)
nn Rail-to-Rail Input Overdrive Tolerance
nn Programmable Sequencer with No-Latency Control
nn Guaranteed Operation to 125°C
nn Integrated Reference and Buffer (4.096V)
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
nn No Pipeline Delay, No Cycle Latency
nn 180mW Power Dissipation (Typical)
nn 48-Lead (7mm × 7mm) LQFP Package
The LTC®2335-16 is a 16-bit, low noise 8-channel multiplexed successive approximation register (SAR) ADC with
differential, wide common mode range inputs. Operating
from a 5V low voltage supply, flexible high voltage supplies,
and using the internal reference and buffer, this SoftSpanTM
ADC can be configured on a conversion-by-conversion
basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to
5.12V signals on any channel. Alternately, the ADC may
be programmed to cycle through a sequence of channels
and ranges without further user intervention.
nn
The wide input common mode range and 118dB CMRR of
the LTC2335-16 analog inputs allow the ADC to directly
digitize a variety of signals, simplifying signal chain design. This input signal flexibility, combined with ±1LSB
INL, no missing codes at 16 bits, and 94.4dB SNR, makes
the LTC2335-16 an ideal choice for many high voltage
applications requiring wide dynamic range.
The LTC2335-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces.
Applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.
Other Patents pending.
Programmable Logic Controllers
Industrial Process Control
nn Power Line Monitoring
nn Test and Measurement
nn
nn
Typical Application
15V
0.1µF
5V
0.1µF
2.2µF
Integral Nonlinearity vs
Output Code and Channel
1.8V TO 5V
0.1µF
CMOS OR LVDS
I/O INTERFACE
0V
0V
–10V
–5V
+10V
0V
0V
–10V
–10V
UNIPOLAR
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
• • •
TRUE BIPOLAR
+10V
VCC
IN0+
IN0–
VDDLBYP
0.75
OVDD LVDS/CMOS
PD
SDO
SCKO
SCKI
SDI
CS
BUSY
CNV
16-BIT
SAMPLING
ADC
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
0.50
LTC2335-16
MUX
IN7+
IN7–
VDD
1.00
INL ERROR (LSB)
+10V
ARBITRARY
FULLY
DIFFERENTIAL
+5V
SAMPLE
CLOCK
0.25
0
–0.25
–0.50
–0.75
VEE REFBUF
REFIN
–1.00
–32768
GND
233516 TA01a
0.1µF
47µF
0.1µF
–16384
0
16384
OUTPUT CODE
32768
233516 TA01b
–15V
233516f
For more information www.linear.com/LTC2335-16
1
LTC2335-16
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
IN7+
IN7–
GND
VEE
GND
VDD
VDD
GND
VDDLBYP
CS
BUSY
SDI
Supply Voltage (VCC)......................–0.3V to (VEE + 40V)
Supply Voltage (VEE)................................. –17.4V to 0.3V
Supply Voltage Difference (VCC – VEE).......................40V
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)
Analog Input Voltage
IN0+ to IN7+,
IN0– to IN7– (Note 4).......... (VEE – 0.3V) to (VCC + 0.3V)
REFIN..................................................... –0.3V to 2.8V
REFBUF, CNV (Note 5).............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 5)...... –0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 5)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2335C................................................. 0°C to 70°C
LTC2335I..............................................–40°C to 85°C
LTC2335H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
IN6– 1
IN6+ 2
IN5– 3
IN5+ 4
IN4– 5
IN4+ 6
IN3– 7
IN3+ 8
IN2– 9
IN2+ 10
IN1– 11
IN1+ 12
GND
SDO–
SDO+
SCKO–/SDO
SCKO+/SCKO
OVDD
GND
SCKI–/SCKI
SCKI+
SDI–
SDI+
GND
IN0– 13
IN0+ 14
GND 15
VCC 16
VEE 17
GND 18
REFIN 19
GND 20
REFBUF 21
PD 22
LVDS/CMOS 23
CNV 24
36
35
34
33
32
31
30
29
28
27
26
25
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/W
Order Information
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2335CLX-16#PBF
LTC2335CLX-16#PBF
LTC2335LX-16
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
LTC2335ILX-16#PBF
LTC2335ILX-16#PBF
LTC2335LX-16
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 85°C
LTC2335HLX-16#PBF
LTC2335HLX-16#PBF
LTC2335LX-16
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
233516f
2
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LTC2335-16
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 6)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range
(IN0+ to IN7+)
VIN–
Absolute Input Range
(IN0– to IN7–)
VIN+ – VIN– Input Differential Voltage
Range
VCM
TYP
MAX
UNITS
(Note 7)
VEE
VCC – 4
V
(Note 7)
l
VEE
VCC – 4
V
SoftSpan 7: ±2.5 • VREFBUF Range (Note 7)
SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7)
SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 3: ±1.25 • VREFBUF Range (Note 7)
SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7)
SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7)
SoftSpan 0: 0V to 1.25 • VREFBUF/1.024 Range (Note 7)
l
–2.5 • VREFBUF
l –2.5 • VREFBUF/1.024
l
0
l
0
l
–1.25 • VREFBUF
l –1.25 • VREFBUF/1.024
l
0
l
0
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
V
V
V
V
V
V
V
V
Input Common Mode Voltage (Note 7)
Range
VIN+ – VIN– Input Differential Overdrive
Tolerance
MIN
l
(Note 8)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
CMRR
Input Common Mode
Rejection Ratio
VIN+ = VIN− = 18VP-P 200Hz Sine
VIHCNV
l
VEE
VCC – 4
V
l
−(VCC − VEE)
(VCC − VEE)
V
l
–1
1
µA
l
100
CNV High Level Input Voltage
l
1.3
VILCNV
CNV Low Level Input Voltage
l
IINCNV
CNV Input Current
VIN = 0V to VDD
50
10
pF
pF
118
dB
V
–10
l
0.5
V
10
μA
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
Resolution
No Missing Codes
l
16
l
16
TYP
MAX
UNITS
Bits
Bits
Transition Noise
SoftSpans 7 and 6: ±10.24V and ±10V Ranges
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges
SoftSpans 3 and 2: ±5.12V and ±5V Ranges
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges
INL
Integral Linearity Error
(Note 10)
l
–1
±0.3
1
LSB
DNL
Differential Linearity Error (Note 11)
l
−0.9
±0.2
0.9
LSB
Zero-Scale Error
l
−550
±160
550
ZSE
(Note 12)
0.33
0.65
0.5
1.0
Zero-Scale Error Drift
FSE
Full-Scale Error
LSBRMS
LSBRMS
LSBRMS
LSBRMS
±2
(Note 12)
l
Full-Scale Error Drift
−0.1
±0.025
±2.5
μV
μV/°C
0.1
%FS
ppm/°C
233516f
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3
LTC2335-16
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
SINAD
Signal-to-(Noise +
Distortion) Ratio
SNR
91.8
87.2
89.3
83.8
94.3
90.1
92.0
87.0
dB
dB
dB
dB
Signal-to-Noise Ratio
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
92.3
87.3
89.5
83.8
94.4
90.1
92.0
87.0
dB
dB
dB
dB
THD
Total Harmonic Distortion
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
Channel-to-Channel
Active Crosstalk
Alternating Conversions with 18VP-P 200Hz Sine in ±10.24V
Range, Crosstalk to Any Other Channel
–109
–111
–113
–114
101
99
105
105
–3dB Input Bandwidth
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Transient Response
MAX
–101
–99
–104
–103
dB
dB
dB
dB
110
112
114
115
dB
dB
dB
dB
–125
dB
7
MHz
1
ns
150
ps
3
Full-Scale Step, 0.005% Settling
UNITS
psRMS
360
ns
Internal Reference Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
CONDITIONS
Internal Reference Temperature Coefficient
(Note 14)
Internal Reference Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
2.043
2.048
2.053
5
20
l
0.1
Internal Reference Output Impedance
VREFIN
REFIN Voltage Range
1.25
V
ppm/°C
mV/V
20
REFIN Overdriven (Note 7)
UNITS
kΩ
2.2
V
233516f
4
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LTC2335-16
Reference Buffer Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
VREFBUF
Reference Buffer Output Voltage
REFIN Overdriven, VREFIN = 2.048V
REFBUF Voltage Range
REFBUF Overdriven (Notes 7, 15)
REFBUF Input Impedance
VREFIN = 0V, Buffer Disabled
REFBUF Load Current
VREFBUF = 5V, (Notes 15, 16)
VREFBUF = 5V, Acquisition or Nap Mode (Note 15)
IREFBUF
MIN
TYP
MAX
UNITS
l
4.091
4.096
4.101
V
l
2.5
5
V
13
1.1
0.39
l
kΩ
1.4
mA
mA
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
VIH
High Level Input Voltage
l 0.8 • OVDD
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
VIN = 0V to OVDD
l
V
–10
0.2 • OVDD
V
10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IOUT = –500μA
l OVDD – 0.2
5
pF
VOL
Low Level Output Voltage
IOUT = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = OVDD
50
mA
V
0.2
–10
10
V
μA
LVDS Digital Inputs and Outputs
VID
Differential Input Voltage
l
200
350
600
mV
l
RID
On-Chip Input Termination
Resistance
90
106
10
125
Ω
MΩ
VICM
Common-Mode Input Voltage
l
IICM
Common-Mode Input Current
0.3
1.2
2.2
V
VIN+ = VIN– = 0V to OVDD
l
–10
10
μA
VOD
VOCM
Differential Output Voltage
RL = 100Ω Differential Termination
l
275
350
425
mV
Common-Mode Output Voltage
RL = 100Ω Differential Termination
l
1.1
1.2
1.3
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
–10
10
μA
CS = 0V, VICM = 1.2V
CS = OVDD
233516f
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5
LTC2335-16
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
VCC
Supply Voltage
l
VEE
Supply Voltage
l
TYP
MAX
UNITS
0
38
V
–16.5
0
V
VCC − VEE Supply Voltage Difference
l
10
VDD
Supply Voltage
l
4.75
IVCC
Supply Current
1Msps Sample Rate
Acquisition Mode
Nap Mode
Power Down Mode
l
l
l
l
IVEE
Supply Current
1Msps Sample Rate
Acquisition Mode
Nap Mode
Power Down Mode
l
l
l
l
–5.1
–4.9
–1.1
–15
l
1.71
38
V
5.00
5.25
V
3.5
3.8
0.7
1
4.3
4.5
0.9
15
mA
mA
mA
μA
–4.0
–4.0
–0.8
–1
mA
mA
mA
μA
CMOS I/O Mode
OVDD
Supply Voltage
5.25
V
IVDD
Supply Current
1Msps Sample Rate
1Msps Sample Rate, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
12.6
11.3
1.6
1.4
65
65
14.5
13.0
2.1
1.9
175
450
mA
mA
mA
mA
μA
µA
IOVDD
Supply Current
1Msps Sample Rate (CL = 25pF)
Acquisition or Nap Mode
Power Down Mode
l
l
l
2.6
1
1
4.2
20
20
mA
μA
μA
PD
Power Dissipation
1Msps Sample Rate
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
182
125
30
0.36
0.36
224
152
40
1.4
2.8
mW
mW
mW
mW
mW
5.25
V
LVDS I/O Mode
OVDD
Supply Voltage
IVDD
Supply Current
1Msps Sample Rate
1Msps Sample Rate, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
14.8
13.8
3.2
3.0
65
65
17.1
15.9
3.8
3.7
175
450
mA
mA
mA
mA
μA
µA
IOVDD
Supply Current
1Msps Sample Rate, (RL = 100Ω)
Acquisition or Nap Mode (RL = 100Ω)
Power Down Mode
l
l
l
7
7
1
8.5
8.0
20
mA
mA
μA
PD
Power Dissipation
1Msps Sample Rate
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
204
151
55
0.36
0.36
248
180
69
1.4
2.8
mW
mW
mW
mW
mW
l
2.375
233516f
6
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LTC2335-16
ADC Timing Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
l
MIN
TYP
tCYC
Time Between Conversions
l
1
l
450
500
l
420
480
MAX
UNITS
1
Msps
μs
tCONV
Conversion Time
tACQ
Acquisition Time
tCNVH
CNV High Time
l
40
tCNVL
CNV Low Time
l
420
tBUSYLH
CNV↑ to BUSY Delay
tQUIET
Digital I/O Quiet Time from CNV↑
l
20
ns
tPDH
PD High Time
l
40
ns
tPDL
PD Low Time
l
40
ns
tWAKE
REFBUF Wake-Up Time
(tACQ = tCYC – tCONV – tBUSYLH)
CL = 25pF
550
ns
ns
ns
30
l
CREFBUF = 47μF, CREFIN = 0.1μF
ns
200
ns
ms
CMOS I/O Mode
tSCKI
SCKI Period
tSCKIH
tSCKIL
tSSDISCKI
SDI Setup Time from SCKI↑
tHSDISCKI
tDSDOSCKI
(Notes 17, 18)
l
10
ns
SCKI High Time
l
4
ns
SCKI Low Time
l
4
ns
(Note 17)
l
2
ns
SDI Hold Time from SCKI↑
(Note 17)
l
1
SDO Data Valid Delay from SCKI↑
CL = 25pF (Note 17)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI↑
CL = 25pF (Note 17)
l
1.5
tSKEW
SDO to SCKO Skew
ns
7.5
ns
ns
(Note 17)
l
–1
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
CL = 25pF (Note 17)
l
0
0
1
ns
tEN
Bus Enable Time After CS↓
(Note 17)
l
15
ns
tDIS
Bus Relinquish Time After CS↑
(Note 17)
l
15
ns
ns
LVDS I/O Mode
tSCKI
SCKI Period
(Note 19)
l
4
ns
1.5
ns
1.5
ns
tSCKIH
SCKI High Time
(Note 19)
l
tSCKIL
SCKI Low Time
(Note 19)
l
tSSDISCKI
SDI Setup Time from SCKI
(Notes 11, 19)
l
1.2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Notes 11, 19)
l
–0.2
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
(Notes 11, 19)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
(Notes 11, 19)
l
1
tSKEW
SDO to SCKO Skew
(Note 11)
l
–0.4
(Note 11)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
tEN
Bus Enable Time After CS↓
l
tDIS
Bus Relinquish Time After CS↑
l
6
ns
0.4
ns
ns
0
ns
50
ns
15
ns
233516f
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7
LTC2335-16
ADC Timing Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below VEE or above VCC, they
will be clamped by internal diodes. This product can handle input currents
of up to 100mA below VEE or above VCC without latch-up.
Note 5: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 6: –16.5V ≤ VEE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,
VDD = 5V, unless otherwise specified.
Note 7: Recommended operating conditions.
Note 8: Refer to Absolute Maximum Ratings section for pin voltage limits
related to device reliability.
Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 1Msps,
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Note 10: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 11: Guaranteed by design, not subject to test.
Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
error for these SoftSpan ranges is the worst-case deviation of the first
and last code transitions from ideal and includes the effect of offset
error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is
the offset voltage measured from 0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 0000 0000 0000 0001. Full-scale error
for these SoftSpan ranges is the worst-case deviation of the last code
transition from ideal and includes the effect of offset error.
Note 13: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 16: IREFBUF varies proportionally with sample rate.
Note 17: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 18: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 19: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timing
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
233516 F01a
LVDS Timing (Differential)
+200mV
tWIDTH
–200mV
tDELAY
tDELAY
+200mV
+200mV
–200mV
–200mV
0V
0V
233516 F01b
Figure 1. Voltage Levels for Timing Specifications
233516f
8
For more information www.linear.com/LTC2335-16
LTC2335-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code and Channel
1.00
Integral Nonlinearity
vs Output Code and Channel
1.00
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
0.75
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
–32768
–1.00
–32768
–16384
0
16384
OUTPUT CODE
32768
1.00
–16384
0
16384
OUTPUT CODE
–0.25
±10.24V AND ±10V
RANGES
–0.75
–16384
0
16384
OUTPUT CODE
0.25
–0.25
–0.75
–0.75
250000
–1.00
32768
COUNTS
0.25
–0.50
ARBITRARY DRIVE
IN+/IN– COMMON MODE
SWEPT –10.24V to 10.24V
0
16384
OUTPUT CODE
32768
0
32768
49152
OUTPUT CODE
65536
DC Histogram (Near Full-Scale)
±10.24V RANGE
200000
200000
150000
150000
100000
±10.24V RANGE
100000
50000
50000
0
16384
250000
–3
–2
–1
0
1
2
0
32741
32743
32745
32747
CODE
CODE
233516 G07
0V to 10.24V AND
0V to 10V RANGES
233516 G06
COUNTS
TRUE BIPOLAR DRIVE (IN– = 0V)
–16384
–0.25
233516 G05
±10.24V RANGE
–1.00
–32768
0
–0.50
0
16384
OUTPUT CODE
0V to 5.12V AND
0V to 5V RANGES
0.25
–0.50
–16384
65536
0.50
DC Histogram (Zero-Scale)
–0.25
32768
49152
OUTPUT CODE
UNIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
0
Integral Nonlinearity
vs Output Code
–0.75
1.00
±10.24V, ±10V,
±5.12V, AND ±5V
RANGES
–1.00
–32768
32768
0
16384
Integral Nonlinearity
vs Output Code and Range
233516 G04
1.00
0
233516 G03
INL ERROR (LSB)
0
INL ERROR (LSB)
INL ERROR (LSB)
±5.12V AND ±5V
RANGES
–1.00
–32768
–0.25
32768
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ONE CHANNEL
0.75
0.50
–0.50
–0.10
Integral Nonlinearity
vs Output Code and Range
0.50
0.25
0.00
–0.05
233516 G02
TRUE BIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
0.05
–0.20
Integral Nonlinearity
vs Output Code and Range
1.00
0.10
–0.15
233516 G01
INL ERROR (LSB)
0.15
DNL ERROR (LSB)
INL ERROR (LSB)
INL ERROR (LSB)
0
ALL RANGES
ALL CHANNELS
0.20
0.50
0.25
0.50
0.25
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
0.75
0.50
0.75
Differential Nonlinearity
vs Output Code and Range
233516 G08
233516 G09
233516f
For more information www.linear.com/LTC2335-16
9
LTC2335-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
32k Point FFT fSMPL = 1Msps,
32k Point FFT fSMPL = 1Msps,
fSMPL = 1Msps, IN+ = –7dBFS 2kHz
fIN = 2kHz
fIN = 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
–40
SNR = 94.5dB
THD = –109dB
SINAD = 94.4dB
SFDR = 111dB
–60
–80
–100
–120
–40
–80
–40
–100
–120
–100
–120
–140
–140
–160
–160
–180
–180
400
500
0
100
200
300
FREQUENCY (kHz)
0
SNR = 92.2dB
THD = –117dB
SINAD = 92.1dB
SFDR = 118dB
–60
–80
–100
–120
96
–100
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
95
SNR
SINAD
94
100
200
300
FREQUENCY (kHz)
400
92
2.5
500
500
THD, Harmonics vs VREFBUF,
fIN = 2kHz
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
THD
2ND
–115
3RD
–120
3
3.5
4
4.5
REFBUF VOLTAGE (V)
–70
92.0
SINAD
SNR
88.0
84.0
80.0
THD, HARMONICS (dBFS)
–80
1k
10k
FREQUENCY (Hz)
100k
233516 G16
3
3.5
4
4.5
REFBUF VOLTAGE (V)
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
0
–100
THD
–130
3RD
2ND
10
±10.24V RANGE
2VP-P FULLY DIFFERENTIAL DRIVE
–20
–90
–110
–40
–60
–80
–100
–120
THD
–140
100
1k
10k
FREQUENCY (Hz)
5
233516 G15
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–120
100
–130
2.5
THD, Harmonics
vs Input Frequency
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
10
5
233516 G14
SNR, SINAD
vs Input Frequency
76.0
400
–110
THD, HARMONICS (dBFS)
0
233516 G13
96.0
200
300
FREQUENCY (kHz)
–125
–160
100.0
100
–105
93
–140
–180
0
233516 G12
SNR, SINAD vs VREFBUF,
fIN = 2kHz
SNR, SINAD (dBFS)
–40
–180
500
233516 G11
±5.12V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–20
400
THD, HARMONICS (dBFS)
200
300
FREQUENCY (kHz)
32k Point FFT fSMPL = 1Msps,
fIN = 2kHz
SNR, SINAD (dBFS)
–80
–160
100
SFDR = 119dB
SNR = 94.6dB
–60
–140
0
±10.24V RANGE
ARBITRARY DRIVE
–20
SNR = 94.5dB
THD = –122dB
SINAD = 94.5dB
SFDR = 119dB
–60
233516 G10
AMPLITUDE (dBFS)
0
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
AMPLITUDE (dBFS)
0
100k
233516 G17
–160
–15
2ND
–10
3RD
–5
0
5
10
INPUT COMMON MODE (V)
15
233516 G18
233516f
10
For more information www.linear.com/LTC2335-16
LTC2335-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
94.8
–60
±10.24V RANGE
IN+ = IN– = 18VP-P SINE
ALL CHANNELS
130
±10.24V RANGE
+
–70 IN0– = 0V
IN0 = 18VP-P SINE
–80 IN1+, IN1–, IN2+, IN2– = 0V
120
SNR
94.6
CMRR (dB)
SNR, SINAD (dBFS)
140
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
Crosstalk vs Input Frequency
and Conversion Sequence
SINAD
94.4
CROSSTALK (dB)
95.0
CMRR vs Input Frequency
and Channel
SNR, SINAD vs Input Level,
fIN = 2kHz
110
100
90
80
94.2
60
0
10
100
1k
10k
FREQUENCY (Hz)
100k
–95
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
SINAD
93
–105
THD
–110
2ND
–115
3RD
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.4
0.2
–0.025
–0.050
–0.075
233516 G25
MAX DNL
0.0
–0.2
–0.4
MIN DNL
MIN INL
–1.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
233516 G24
0.075
Zero-Scale Error vs
Temperature and Channel
0.050
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
2.0
±10.24V RANGE
ALL CHANNELS
–0.075
5 25 45 65 85 105 125
TEMPERATURE (°C)
MAX INL
–0.6
1.5
ZERO-SCALE ERROR (LSB)
0.000
–0.100
–55 –35 –15
0.100
FULL-SCALE ERROR (%)
FULL-SCALE ERROR (%)
0.025
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
0.8
233516 G23
±10.24V RANGE
ALL CHANNELS
1M
INL, DNL vs Temperature
Negative Full-Scale Error vs
Temperature and Channel
0.050
100k
–0.8
–125
–55 –35 –15
Positive Full-Scale Error vs
Temperature and Channel
0.075
1k
10k
FREQUENCY (Hz)
0.6
233516 G22
0.100
100
1.0
–120
92
–55 –35 –15
CH1, CH1, CH1, CH1...
10
233516 G21
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–100
94
–150
1M
THD, Harmonics vs Temperature,
fIN = 2kHz
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
SNR
–120
233516 G20
SNR, SINAD vs Temperature,
fIN = 2kHz
95
CH0, CH1, CH0, CH1...
–140
233516 G19
96
–110
INL, DNL ERROR (LSB)
–30
–20
–10
INPUT LEVEL (dBFS)
CH0, CH2, CH0, CH2...
–100
–130
70
94.0
–40
–90
±10.24V RANGE
ALL CHANNELS
1.0
0.5
0
–0.5
–1.0
–1.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
233516 G26
–2.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
233516 G27
233516f
For more information www.linear.com/LTC2335-16
11
LTC2335-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
Power-Down Current
vs Temperature
Supply Current vs Temperature
18
SUPPLY CURRENT (mA)
12
10
8
6
IVCC
4
2
IOVDD
0
–2
IVEE
–4
IVDD
100
POWER-DOWN CURRENT (µA)
IVDD
14
120 VCC
10
1
0.1
0.01
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.051
INTERNAL REFERENCE OUTPUT (V)
1.0
VCC = 38V, VEE = 0V
VCM = 0V to 34V
0
–0.5
–1.5
–2.0
–17
80
70
IOVDD
VCC = 21.5V, VEE = –16.5V
VCM = –16.5V to 17.5V
0
17
INPUT COMMON MODE (V)
34
100
1k
10k
FREQUENCY (Hz)
100k
2.050
2.049
2.048
2.047
2.046
8
6
IVCC
4
2
0
IOVDD
IVEE
–4
5 25 45 65 85 105 125
TEMPERATURE (°C)
IVDD
10
–2
2.045
–55 –35 –15
1M
Supply Current vs Sampling Rate
WITH NAP MODE
14 t CNVL = 500ns
12
–6
0
200
400
600
800
SAMPLING FREQUENCY (kHz)
233516 G32
1000
233516 G33
Step Response
(Fine Settling)
100
24576
80
16384
±10.24V RANGE
IN+ = 249.99984kHz SQUARE WAVE
IN– = 0V
–16384
–24576
–32768
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
233516 G34
DEVIATION FROM FINAL VALUE (LSB)
OUTPUT CODE (LSB)
10
233516 G30
15 UNITS
32768
–8192
VDD
16
Step Response
(Large-Signal Settling)
0
50
5 25 45 65 85 105 125
TEMPERATURE (°C)
233516 G31
8192
60
SUPPLY CURRENT (mA)
±10.24V RANGE
0.5
90
Internal Reference Output
vs Temperature
1.5
VEE
100
233516 G29
Offset Error
vs Input Common Mode
2.0
110
–IVEE
233516 G28
–1.0
130
IVCC
–6
–55 –35 –15
IN+ = IN– = 0V
OVDD
140
PSRR (dB)
16
OFFSET ERROR (LSB)
PSRR vs Frequency
150
1000
60
±10.24V RANGE
IN+ = 249.99984kHz
SQUARE WAVE
IN– = 0V
40
20
0
–20
–40
–60
–80
–100
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
233516 G35
233516f
12
For more information www.linear.com/LTC2335-16
LTC2335-16
Pin Functions
Pins that are the Same for All Digital I/O Modes
IN0+ to IN7+, IN0− to IN7− (Pins 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 47, and 48): Positive and Negative
Analog Inputs, Channels 0 to 7. The converter samples
(VIN+ – VIN–) and digitizes the selected channel. Wide
input common mode range (VEE ≤ VCM ≤ VCC – 4V) and
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the selected SoftSpan configuration.
GND (Pins 15, 18, 20, 25, 30, 36, 41, 44, 46): Ground.
Solder all GND pins to a solid ground plane.
VCC (Pin 16): Positive High Voltage Power Supply. The
range of VCC is 0V to 38V with respect to GND and 10V to
38V with respect to VEE. Bypass VCC to GND close to the
pin with a 0.1μF ceramic capacitor. In applications where
VCC is shorted to GND this capacitor may be omitted.
VEE (Pins 17, 45): Negative High Voltage Power Supply.
The range of VEE is 0V to –16.5V with respect to GND and
–10V to –38V with respect to VCC. Connect Pins 17 and 45
together and bypass the VEE network to GND close to Pin
17 with a 0.1μF ceramic capacitor. In applications where
VEE is shorted to GND this capacitor may be omitted.
REFIN (Pin 19): Bandgap Reference Output/Reference
Buffer Input. An internal bandgap reference nominally
outputs 2.048V on this pin. An internal reference buffer
amplifies VREFIN to create the converter master reference
voltage VREFBUF = 2 • VREFIN on the REFBUF pin. When
using the internal reference, bypass REFIN to GND (Pin
20) close to the pin with a 0.1μF ceramic capacitor to filter
the bandgap output noise. If more accuracy is desired,
overdrive REFIN with an external reference in the range
of 1.25V to 2.2V.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2 • VREFIN on
this pin, nominally 4.096V when using the internal bandgap
reference. Bypass REFBUF to GND (Pin 20) close to the
pin with a 47μF ceramic capacitor. The internal reference
buffer may be disabled by grounding its input at REFIN.
With the buffer disabled, overdrive REFBUF with an external reference voltage in the range of 2.5V to 5V. When
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
Using a high input impedance amplifier to buffer VREFBUF
to any external circuits is recommended.
PD (Pin 22): Power Down Input. When this pin is brought
high, the LTC2335-16 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
CNV (Pin 24): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
BUSY (Pin 38): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pins 42, 43): 5V Power Supply. The range of VDD
is 4.75V to 5.25V. Connect Pins 42 and 43 together and
bypass the VDD network to GND with a shared 0.1μF
ceramic capacitor close to the pins.
233516f
For more information www.linear.com/LTC2335-16
13
LTC2335-16
Pin Functions
CMOS I/O Mode
LVDS I/O Mode
SDI+, SDI–, SCKI+, SDO+, SDO– (Pins 26, 27, 28, 34,
and 35): LVDS Inputs and Outputs. In CMOS I/O mode
these pins are Hi-Z.
SDI+, SDI– (Pins 26 and 27): LVDS Positive and Negative Serial Data Input. Differentially drive SDI+/SDI– with
the desired MUX control words (see Table 1a), latched
on both the rising and falling edges of SCKI+/SCKI–. The
SDI+/SDI– input pair is internally terminated with a 100Ω
differential resistor when CS is low.
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO. For standard
SPI bus operation, capture output data at the receiver on
rising edges of SCKI. SCKI is allowed to idle either high
or low. Logic levels are determined by OVDD.
OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched to
the serial output data stream on SDO. The resulting SCKO
frequency is half that of SCKI. Rising and falling edges of
SCKO may be used to capture SDO data at the receiver
(FPGA) in double data rate (DDR) fashion. For standard
SPI bus operation, SCKO is not used and should be left
unconnected. SCKO is forced low at the falling edge of
BUSY. Logic levels are determined by OVDD.
SDO (Pin 33): CMOS Serial Data Output. The most recent
conversion result along with channel configuration information is clocked out onto the SDO pin on each rising edge
of SCKI. Output data formatting is described in the Digital
Interface section. Logic levels are determined by OVDD.
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with
the desired MUX control words (see Table 1a), latched
on the rising edges of SCKI. Hold SDI low while clocking SCKI to configure the next conversion according to
the previously programmed sequence. Logic levels are
determined by OVDD.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
SCKI+, SCKI– (Pins 28 and 29): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS is low.
OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+, SCKO– (Pins 32 and 33): LVDS Positive and
Negative Serial Clock Output. SCKO+/SCKO– outputs a
copy of the input serial I/O clock received on SCKI+/SCKI–,
skew-matched with the serial output data stream on SDO+/
SDO–. Use the rising and falling edges of SCKO+/SCKO–
to capture SDO+/SDO– data at the receiver (FPGA). The
SCKO+/SCKO– output pair must be differentially terminated
with a 100Ω resistor at the receiver (FPGA).
SDO+, SDO– (Pins 34 and 35): LVDS Positive and Negative Serial Data Output. The most recent conversion result
along with channel configuration information is clocked out
onto SDO+/SDO– on both rising and falling edges of SCKI+/
SCKI–. The SDO+/SDO– output pair must be differentially
terminated with a 100Ω resistor at the receiver (FPGA).
SDI (Pin 37): CMOS Serial Data Input. In LVDS I/O mode
this pin is Hi-Z.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
233516f
14
For more information www.linear.com/LTC2335-16
LTC2335-16
Configuration Tables
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Binary SoftSpan Codes SS[2:0] Based on Desired
Analog Input Range. Combine MUX Word Header (10) with Binary Channel Number and SoftSpan Code to Form MUX Control Word
C[7:0]. Use Serial Interface to Program LTC2335-16 Sequencer as Shown in Figures 17 to 20
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
FULL SCALE RANGE
BINARY FORMAT OF
CONVERSION RESULT
111
110
101
100
011
010
001
000
±2.5 • VREFBUF
±2.5 • VREFBUF/1.024
0V to 2.5 • VREFBUF
0V to 2.5 • VREFBUF/1.024
±1.25 • VREFBUF
±1.25 • VREFBUF/1.024
0V to 1.25 • VREFBUF
0V to 1.25 • VREFBUF/1.024
5 • VREFBUF
5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Table 1b. Reference Configuration Table. The LTC2335-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
Internal Reference with
Internal Buffer
VREFIN
VREFBUF
2.048V
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±10.24V
110
±10V
101
0V to 10.24V
100
0V to 10V
011
±5.12V
4.096V
1.25V
(Min Value)
2.5V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
2.2V
(Max Value)
4.4V
010
±5V
001
0V to 5.12V
000
0V to 5V
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
000
0V to 3.052V
111
±11V
110
±10.742V
101
0V to 11V
100
0V to 10.742V
011
±5.5V
010
±5.371V
001
0V to 5.5V
000
0V to 5.371V
233516f
For more information www.linear.com/LTC2335-16
15
LTC2335-16
Configuration Tables
Table 1b. Reference Configuration Table (Continued). The LTC2335-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
VREFIN
0V
VREFBUF
BINARY SoftSpan CODE
SS[2:0]
2.5V
(Min Value)
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V
5V
(Max Value)
ANALOG INPUT RANGE
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
000
0V to 3.052V
111
±12.5V
110
±12.207V
101
0V to 12.5V
100
0V to 12.207V
011
±6.25V
010
±6.104V
001
0V to 6.25V
000
0V to 6.104V
233516f
16
For more information www.linear.com/LTC2335-16
LTC2335-16
Functional Block Diagram
CMOS I/O Mode
IN0+
VCC
VDD
VDDLBYP
IN0–
OVDD
LTC2335-16
2.5V
REGULATOR
IN1+
SDO
IN1–
IN2+
SCKO
SEQUENCER
CMOS
SERIAL
I/O
INTERFACE
8-CHANNEL MULTIPLEXER
IN2–
IN3+
IN3–
IN4+
IN4–
IN5+
IN5–
16-BIT
SAMPLING
ADC
IN6+
IN6–
20k
2.048V
REFERENCE
IN7+
IN7–
VEE
GND
SDI
SCKI
CS
16 BITS
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
233516 BD01
LVDS I/O Mode
IN0+
VCC
VDD
VDDLBYP
IN0–
OVDD
LTC2335-16
SDO+
2.5V
REGULATOR
IN1+
SDO–
IN1–
SCKO+
IN2+
IN3+
IN3–
IN4+
IN4–
IN5+
IN5–
SEQUENCER
8-CHANNEL MULTIPLEXER
IN2–
16-BIT
SAMPLING
ADC
IN6+
IN6–
2.048V
REFERENCE
IN7+
IN7–
VEE
GND
20k
LVDS
SERIAL
I/O
INTERFACE
SCKO–
SDI+
SDI–
SCKI+
SCKI–
16 BITS
CS
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
233516 BD02
233516f
For more information www.linear.com/LTC2335-16
17
LTC2335-16
Timing Diagram
CMOS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
BUSY
CONVERT
ACQUIRE
1
2
3
4
C7
C6
C5 C4
5
6
7
8
9
C3
C2
C1
C0 C7
10
11
12
13
14
15
C6
C5
C4
C3
C2 C1
16
17
18
19
20
21
22
23
24
SCKI
DON’T CARE
SDI
CONTROL WORD FOR
CONVERSION N + 1
C0
CONTROL WORD FOR
CONVERSION N + 2
SCKO
DON’T CARE
SDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 CH2 CH1 CH0 SS2 SS1 SS0 D15
0
CONVERSION RESULT
CHANNEL ID
SoftSpan
CONVERSION RESULT
(REPETITION)
233516 TD01
CONVERSION N
LVDS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
SCKI
(LVDS)
SDI
(LVDS)
ACQUIRE
1
DON’T CARE
C7
2
C6
3
4
C5 C4
5
6
7
8
C3
C2
C1
CONTROL WORD FOR
CONVERSION N + 1
9
10
11 12
13 14
C0 C7
C6
C5
C3
C4
15 16
C2 C1
17 18
19 20
21 22
23 24
C0
CONTROL WORD FOR
CONVERSION N + 2
SCKO
(LVDS)
SDO
(LVDS)
DON’T CARE
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION RESULT
CONVERSION N
0
0 CH2 CH1 CH0 SS2 SS1 SS0 D15
CHANNEL ID
SoftSpan
CONVERSION RESULT
(REPETITION)
233516 TD02
233516f
18
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
The LTC2335-16 is a 16-bit, low noise 8-channel multiplexed successive approximation register (SAR) ADC with
differential, wide common mode range inputs. The ADC
operates from a 5V low voltage supply and flexible high
voltage supplies, nominally ±15V. Using the integrated
low-drift reference and buffer (VREFBUF = 4.096V nominal),
this SoftSpan ADC can be configured on a conversion-byconversion basis to accept ±10.24V, 0V to 10.24V, ±5.12V,
or 0V to 5.12V signals on any channel. Alternately, the
ADC may be programmed to cycle through a sequence of
channels and ranges without further user intervention. The
input signal range may be expanded up to ±12.5V using
an external 5V reference.
The wide input common mode range and high CMRR
(118dB typical, VIN+ = VIN– = 18VP-P 200Hz Sine) of the
LTC2335-16 analog inputs allow the ADC to directly digitize
a variety of signals, simplifying signal chain design. The
absolute common mode input range is determined by
the choice of high voltage supplies, which may be biased
asymmetrically around ground and include the ability for
either the positive or negative supply to be tied directly to
ground. This input signal flexibility, combined with ±1LSB
INL, no missing codes at 16-bits, and 94.4dB SNR, makes
the LTC2335-16 an ideal choice for many high voltage
applications requiring wide dynamic range.
The LTC2335-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and modern
FPGAs. The LTC2335-16 typically dissipates 180mW when
converting at 1Msps throughput. Optional nap and power
down modes may be employed to further reduce power
consumption during inactive periods.
Converter Operation
The LTC2335-16 operates in two phases. During the acquisition phase, the sampling capacitors in each channel
connect to their respective analog input pins and track the
differential analog input voltage (VIN+ – VIN–). A rising edge
on the CNV pin transitions the S/H circuits from track mode
to hold mode, sampling the input signals and initiating a
conversion. During the conversion phase, the selected
channel's sampling capacitors are connected to a 16-bit
charge redistribution capacitor D/A converter (CDAC). The
CDAC is sequenced through a successive approximation
algorithm, effectively comparing the sampled input voltage
with binary-weighted fractions of the channel’s SoftSpan
full-scale range (e.g., VFSR/2, VFSR/4 … VFSR/65536) using
a differential comparator. At the end of this process, the
CDAC output approximates the channel’s sampled analog
input. The ADC control logic then prepares the 16-bit digital
output code for serial transfer.
Transfer Function
The LTC2335-16 digitizes the full-scale voltage range into
216 levels. In conjunction with the ADC master reference
voltage, VREFBUF, the selected SoftSpan configuration
determines its input voltage range, full-scale range, LSB
size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±10.24V bipolar analog input voltage range, which corresponds to a
20.48V full-scale range with a 312.5μV LSB. Other SoftSpan
configurations and reference voltages may be employed to
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s complement binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.
OUTPUT CODE (TWO’S COMPLEMENT)
Overview
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
233516 F02
Figure 2. LTC2335-16 Two’s Complement Transfer Function
233516f
For more information www.linear.com/LTC2335-16
19
LTC2335-16
OUTPUT CODE (STRAIGHT BINARY)
Applications Information
the sampling switches, each of which has approximately
600Ω (RIN) of on-resistance. This behavior occurs on all
channels, so that the LTC2335-16 may respond instantly
to user-requested changes in multiplexer configuration
with no additional settling time required.
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
VCC
000...001
FSR = +FS
1LSB = FSR/65536
000...000
0V
RIN
600Ω
IN+
CIN
40pF
FSR – 1LSB
INPUT VOLTAGE (V)
VEE
233516 F03
VCC
Figure 3. LTC2335-16 Straight Binary Transfer Function
RIN
600Ω
IN–
Analog Inputs
The LTC2335-16 samples the voltage difference (VIN+ –
VIN–) between its analog input pins over a wide common
mode input range while attenuating unwanted signals
common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode input
range coupled with high CMRR allows the IN+/IN– analog
inputs to swing with an arbitrary relationship to each
other, provided each pin remains between (VCC – 4V)
and VEE. This unique feature of the LTC2335-16 enables
it to accept a wide variety of signal swings, including
traditional classes of analog input signals such as pseudodifferential unipolar, pseudo-differential true bipolar, and
fully differential, simplifying signal chain design.
The wide operating range of the high voltage supplies
offers further input common mode flexibility. As long as
the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individual allowed operating
ranges, including the ability for either of the supplies to be
tied directly to ground. This feature enables the common
mode input range of the LTC2335-16 to be tailored to the
specific application’s requirements.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4.
At the start of acquisition, the 40pF sampling capacitors
(CIN) connect to the analog input pins IN+/IN– through
CIN
40pF
BIAS
VOLTAGE
233516 F04
VEE
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
The initial voltage on both capacitors of the just-converted
channel will be approximately the sampled common mode
voltage (VIN+ + VIN–)/2 from the previous conversion.
Other channels’ capacitors will retain approximately the
voltage of their respective IN+/IN– pin at the beginning of
the previous conversion. The external circuitry connected
to IN+ and IN– must source or sink the charge that flows
through RIN as the sampling capacitors settle from their
initial voltages to the new input pin voltages over the
course of the acquisition interval. During conversion, nap,
and power down modes, the analog inputs draw only a
small leakage current. The diodes at the inputs provide
ESD protection.
Bipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 7, 6, 3,
or 2, the LTC2335-16 digitizes the differential analog
input voltage (VIN+ – VIN–) over a bipolar span of
±2.5 • VREFBUF, ±2.5 • VREFBUF/1.024, ±1.25 • VREFBUF, or
±1.25 • VREFBUF/1.024, respectively, as shown in Table
1a. These SoftSpan ranges are useful for digitizing input
signals where IN+ and IN– swing above and below each
233516f
20
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
other. Traditional examples include fully differential input
signals, where IN+ and IN– are driven 180 degrees out-ofphase with respect to each other centered around a common
mode voltage (VIN+ + VIN–)/2, and pseudo-differential true
bipolar input signals, where IN+ swings above and below
a ground reference level, driven on IN–. Regardless of the
chosen SoftSpan range, the wide common mode input
range and high CMRR of the IN+/IN– analog inputs allow
them to swing with an arbitrary relationship to each other,
provided each pin remains between (VCC – 4V) and VEE.
The output data format for all bipolar SoftSpan ranges is
two’s complement.
Unipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 5, 4, 1,
or 0, the LTC2335-16 digitizes the differential analog
input voltage (VIN+ – VIN–) over a unipolar span of 0V
to 2.5 • VREFBUF, 0V to 2.5 • VREFBUF/1.024, 0V to 1.25 •
VREFBUF, or 0V to 1.25 • VREFBUF/1.024, respectively, as
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A
traditional example includes pseudo-differential unipolar
input signals, where IN+ swings above a ground reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode input range and high
CMRR of the IN+/IN– analog inputs allow them to swing
with an arbitrary relationship to each other, provided each
pin remains between (VCC – 4V) and VEE. The output data
format for all unipolar SoftSpan ranges is straight binary.
Input Drive Circuits
The initial voltage on each channel’s sampling capacitors
at the start of acquisition must settle to the new input
pin voltages during the acquisition interval. The external
circuitry connected to IN+ and IN– must source or sink
the charge that flows through RIN as this settling occurs.
The LTC2335-16 sampling network RC time constant of
24ns implies a 16-bit settling time to a full-scale step of
approximately 11 • (RIN • CIN) = 264ns. The impedance and
self-settling of external circuitry connected to the analog
input pins will increase the overall settling time required.
Low impedance sources can directly drive the inputs of
the LTC2335-16 without gain error, but high impedance
sources should be buffered to ensure sufficient settling
during acquisition and to optimize the linearity and distortion performance of the ADC. Settling time is an important
consideration even for DC input signals, as the voltages on
the sampling capacitors will differ from the analog input
pin voltages at the start of acquisition.
Most applications should use a buffer amplifier to drive the
analog inputs of the LTC2335-16. The amplifier provides
low output impedance, enabling fast settling of the analog
signal during the acquisition phase. It also provides isolation between the signal source and the charge flow at the
analog inputs when entering acquisition.
Input Filtering
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a lowbandwidth filter to minimize noise. The simple one-pole
RC lowpass filter shown in Figure 5 is sufficient for many
applications.
At the output of the buffer, a lowpass RC filter network
formed by the 600Ω sampling switch on-resistance (RIN)
and the 40pF sampling capacitance (CIN) limits the input
bandwidth on each channel to 7MHz, which is fast enough
to allow for sufficient transient settling during acquisition
while simultaneously filtering driver wideband noise.
A buffer amplifier with low noise density should be selected to minimize SNR degradation over this bandwidth.
An additional filter network may be placed between the
buffer output and ADC input to further minimize the noise
233516f
For more information www.linear.com/LTC2335-16
21
LTC2335-16
Applications Information
TRUE BIPOLAR
INPUT SIGNAL
LOWPASS
SIGNAL FILTER
160Ω
+
BUFFER
AMPLIFIER
0V
–
10nF
IN0+
IN0–
LTC2335-16
BW = 100kHz
ONLY CHANNEL 0 SHOWN FOR CLARITY
233516 F05
Figure 5. True Bipolar Signal Chain with Input Filtering
contribution of the buffer. A simple one-pole lowpass RC
filter is sufficient for many applications.
This filter interacts with the buffer amplifier and slows
input settling. It is important that the inputs settle to 16bit resolution within the ADC acquisition time (tACQ), as
insufficient settling can limit INL and THD performance.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Buffering Arbitrary and Fully Differential Analog Input
Signals
The wide common mode input range and high CMRR of
the LTC2335-16 allow each channel’s IN+ and IN– pins
to swing with an arbitrary relationship to each other,
provided each pin remains between (VCC – 4V) and VEE.
This unique feature of the LTC2335-16 enables it to accept
a wide variety of signal swings, simplifying signal chain
design. In many applications, connecting a channel’s IN+
and IN– pins directly to the existing signal chain circuitry
will not allow the channel’s sampling network to settle to
16-bit resolution within the ADC acquisition time (tACQ). In
these cases, it is recommended that two unity-gain buffers
be inserted between the signal source and the ADC input
pins, as shown in Figure 6a. Table 2 lists several amplifier
and lowpass filter combinations recommended for use in
this circuit.
The LT1358 combines fast settling, high linearity, and low
input-referred noise density, allowing it to approach the
full ADC data sheet SNR and THD specifications, when
used with a lowpass filter, as shown in the FFT plots in
Figures 6b to 6e. It may be used without a filter at a loss of
0.2dB SNR due to wideband noise. The LT1469 achieves
the full ADC specifications for DC precision, THD, and
linearity, at a cost of 0.5dB in SNR. Finally, the LT1355
provides a good general-purpose combination of THD and
SNR at a lower power. Neither the LT1469 nor LT1355
can afford the slowing effect of a lowpass filter if they are
to be used at the minimum tACQ of 420ns.
Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured
Using Circuit in Figure 6a, ±10.24V Range
AMPLIFIER
RFILT
(Ω)
CFILT
(pF)
INPUT SIGNAL DRIVE
SNR
(dB)
THD
(dB)
SINAD
(dB)
SFDR
(dB)
½ LT1358
100
270
FULLY DIFFERENTIAL
94.5
−120
94.5
120
½ LT1469
0
0
FULLY DIFFERENTIAL
94.0
−124
94.0
120
½ LT1358
100
270
TRUE BIPOLAR
94.5
−107
94.3
108
½ LT1358
0
0
TRUE BIPOLAR
94.3
−108
94.2
110
½ LT1469
0
0
TRUE BIPOLAR
94.0
−109
94.0
110
½ LT1355
0
0
TRUE BIPOLAR
94.1
−103
93.6
104
233516f
22
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LTC2335-16
Applications Information
+10V
FULLY
DIFFERENTIAL
+5V
ARBITRARY
0V
0V
–10V
–5V
TRUE BIPOLAR
+10V
+10V
0V
0V
–10V
–10V
–
15V
AMPLIFIER
IN+
IN–
UNIPOLAR
15V
OPTIONAL
LOWPASS FILTERS
0.1µF
RFILT
+
VCC
IN0+
IN0–
CFILT
LTC2335-16
+
CFILT
AMPLIFIER
–
VEE REFBUF
RFILT
0.1µF
47µF
0.1µF
–15V
REFIN
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233516 F06a
Figure 6a. Buffering Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals.
See Table 2 for Recommended Amplifier and Filter Combinations
Arbitrary Drive
0
±10.24V RANGE
–20
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
–180
0
100
200
300
FREQUENCY (kHz)
400
SNR = 94.5dB
THD = –120dB
SINAD = 94.5dB
SFDR = 120dB
–40
AMPLITUDE (dBFS)
–60
±10.24V RANGE
–20
SFDR = 119dB
SNR = 94.6dB
–40
AMPLITUDE (dBFS)
Fully Differential Drive
0
500
0
100
200
300
FREQUENCY (kHz)
400
233516 F06b
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS
3.1kHz Sine, 32k Point FFT, fSMPL = 1Msps. Circuit Shown in
Figure 6a with LT1358 Amplifiers, RFILT = 100Ω, CFILT = 270pF
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, VCM =
0V, 32k Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with
LT1358 Amplifiers, RFILT = 100Ω, CFILT = 270pF
True Bipolar Drive
0
–60
–80
–100
–120
–60
–80
–100
–120
–140
–160
–160
0
100
200
300
FREQUENCY (kHz)
400
500
SNR = 90.4dB
THD = –110dB
SINAD = 90.3dB
SFDR = 112dB
–40
–140
–180
0V to 10.24V RANGE
–20
AMPLITUDE (dBFS)
SNR = 94.5dB
THD = –107dB
SINAD = 94.3dB
SFDR = 108dB
–40
AMPLITUDE (dBFS)
Unipolar Drive
0
±10.24V RANGE
–20
500
233516 F06c
–180
0
233516 F06d
Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k
Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358
Amplifiers, RFILT = 100Ω, CFILT = 270pF
100
200
300
FREQUENCY (kHz)
400
500
233516 F06e
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358
Amplifiers, RFILT = 100Ω, CFILT = 270pF
233516f
For more information www.linear.com/LTC2335-16
23
LTC2335-16
Applications Information
The two-tone test shown in Figure 6b demonstrates the
arbitrary input drive capability of the LTC2335-16. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2335-16
response, which approaches this ideal with 118dB of
SFDR limited by the converter's second harmonic distortion response to the 3.1kHz sine wave on IN–.
many sensors produce a differential sensor voltage riding
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2335-16 to digitize signals of
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while
the unwanted common mode signal is attenuated by the
ADC CMRR. The circuit employs the ±5V SoftSpan range of
the ADC. Figure 7b shows measured CMRR performance
of this solution, which is competitive with the best commercially available instrumentation amplifiers. Figure 7c
shows measured AC performance of this solution.
In Figure 8, another application circuit is shown which
uses two channels of the LTC2335-16 to sense the voltage on and bidirectional current through a sense resistor
over a wide common mode range. In many applications
of this type, the impedance of the external circuitry is low
enough that the ADC sampling network can fully settle
without buffering.
The ability of the LTC2335-16 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. In practice,
IN+
ARBITRARY
+
–
24V
31V
½ LT1124
LOWPASS FILTERS
18pF
0.1µF
2.49k
COMMON MODE
INPUT RANGE
31V
49.9Ω
6.6nF
2.49k
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
IN–
–
+
LTC2335-16
6.6nF
18pF
0V
VCC
IN0+
IN0–
549Ω
49.9Ω
½ LT1124
BW ~ 500kHz
VEE REFBUF
0.1µF
–5V
ONLY CHANNEL 0 SHOWN FOR CLARITY
47µF
REFIN
0.1µF
–5V
233516 F07a
Figure 7a. Digitize Differential Signals Over a Wide Common Mode Range
233516f
24
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
120
15V
±5V RANGE
110
0.1µF
CMRR (dB)
100
80
P-P SINE
OP AMPS SLEW f IN > 30kHz
70
VS2
10
100
1k
10k
FREQUENCY (Hz)
47µF
0.1µF
0.1µF
233516 F08
100k
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
V – VS2
ISENSE = S1
RSENSE
Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a
–10.24V ≤ VS1 ≤ 10.24V
–10.24V ≤ VS2 ≤ 10.24V
Figure 8. Sense Voltage (CH0) and Current (CH1)
Over a Wide Common Mode Range
0
±5V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
–40
AMPLITUDE (dBFS)
REFIN
–15V
233516 F07b
Buffering Single-Ended Analog Input Signals
SNR = 89.4dB
THD = –112dB
SINAD = 89.4dB
SFDR = 116dB
–60
–80
While the circuit shown in Figure 6a is capable of buffering
single-ended input signals, the circuit shown in Figure 9 is
preferable when the single-ended signal reference level is
inherently low impedance and doesn't require buffering.
This circuit eliminates one driver and lowpass filter, reducing part count, power dissipation, and SNR degradation
due to driver noise. Using the recommended driver and
filter combinations in Table 2, the performance of this
circuit with single-ended input signals is on par with the
performance of the circuit in Figure 6a.
–100
–120
–140
–160
–180
LTC2335-16
IN1+
IN1–
ISENSE
VEE REFBUF
IN+ = IN– = 1VP-P SINE
60
50
RSENSE
IN+ = IN– = 24V
VCC
IN0+
IN0–
VS1
90
0
20
40
60
FREQUENCY (kHz)
80
100
233516 F07c
Figure 7c. IN+/IN– = 450mV 2kHz Fully Differential Sine,
0V ≤ VCM ≤ 24V, 32k Point FFT, fSMPL = 200ksps. Circuit
Shown in Figure 7a
TRUE BIPOLAR
+10V
15V
IN+
0V
AMPLIFIER
–10V
+10V
0V
+
–
–15V
UNIPOLAR
15V
OPTIONAL
LOWPASS FILTER
0.1µF
RFILT
IN0+
IN0–
CFILT
VCC
LTC2335-16
IN–
VEE REFBUF
–10V
0.1µF
47µF
REFIN
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233516 F09
Figure 9. Buffering Single-Ended Input Signals. See Table 2 For Recommended Amplifier and Filter Combinations
233516f
For more information www.linear.com/LTC2335-16
25
LTC2335-16
Applications Information
ADC Reference
LTC2335-16
As shown previously in Table 1b, the LTC2335-16 supports
three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
20k
REFIN
0.1µF
REFBUF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
233516 F10a
Internal Reference with Internal Buffer
The LTC2335-16 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure 10a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 20) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin,
nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorb transient conversion currents, and minimize noise.
Figure 10a. Internal Reference with Internal Buffer Configuration
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 10b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter master reference voltages VREFBUF between 2.5V and 4.4V,
respectively. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2335-16 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
LTC2335-16
20k
REFIN
2.7µF
REFBUF
LTC6655-2.048
47µF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
GND
233516 F10b
Figure 10b. External Reference with Internal Buffer Configuration
233516f
26
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
and 2ppm/°C (maximum) temperature coefficient for high
precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range, complementing
the extended temperature range of the LTC2335-16 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
ceramic capacitor close to the REFIN pin is recommended.
External Reference with Disabled Internal Buffer
The internal reference buffer supports VREFBUF = 4.4V
maximum. Grounding REFIN disables the internal buffer,
allowing REFBUF to be overdriven with an external reference voltage between 2.5V and 5V, as shown in Figure
10c. Maximum input signal swing and SNR are achieved
by overdriving REFBUF using an external 5V reference. The
buffer feedback resistors load the REFBUF pin with 13kΩ
even when the reference buffer is disabled. The LTC6655-5
offers the same small size, accuracy, drift, and extended
temperature range as the LTC6655-2.048, and achieves
a typical SNR of 95.3dB when paired with the LTC233516. Bypass the LTC6655-5 to GND (Pin 20) close to the
REFBUF pin with at least a 47μF ceramic capacitor (X7R,
10V, 1210 size or X5R, 10V, 0805 size) to absorb transient
conversion currents and minimize noise.
The LTC2335-16 converter draws a charge (QCONV) from
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
equivalent of IREFBUF = QCONV • fSMPL, which is proportional
LTC2335-16
20k
REFIN
REFBUF
47µF
LTC6655-5
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
GND
233516 F10c
Figure 10c. External Reference with Disabled Internal
Buffer Configuration
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 11, IREFBUF quickly transitions from approximately
0.4mA to 1.1mA (VREFBUF = 5V, fSMPL = 1Msps). This
current step triggers a transient response in the external
reference that must be considered, since any deviation in
VREFBUF affects converter accuracy. If an external reference
is used to overdrive REFBUF, the fast settling LTC6655
family of references is recommended.
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference
buffer incorporates a proprietary design that minimizes
movements in VREFBUF when responding to a burst of
CNV
IDLE
PERIOD
IDLE
PERIOD
233516 F11
Figure 11. CNV Waveform Showing Burst Sampling
233516f
For more information www.linear.com/LTC2335-16
27
LTC2335-16
Applications Information
±10.24V RANGE
IN+ = 10V
IN– = 0V
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–20
–40
SNR = 94.5dB
THD = –109dB
SINAD = 94.4dB
SFDR = 111dB
–60
–80
–100
–120
–140
–160
–180
3
DEVIATION FROM FINAL VALUE (LSB)
0
AMPLITUDE (dBFS)
conversions following an idle period. Figure 12 compares
the burst conversion response of the LTC2335-16 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal reference buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
0
100
200
300
FREQUENCY (kHz)
400
500
233516 F13
2
Figure 13. 32k Point FFT fSMPL = 1Msps, fIN = 2kHz
EXTERNAL REFERNCE ON REFBUF
Signal-to-Noise Ratio (SNR)
1
0
INTERNAL REFERENCE BUFFER
–1
0
100
200
300
TIME (µs)
400
500
233516 F12
Figure 12. Burst Conversion Response of the
LTC2335-16, fSMPL = 1Msps
Dynamic Performance
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2335-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, excluding DC. Figure 13 shows that the LTC2335-16 achieves a
typical SINAD of 94.3dB in the ±10.24V range at a 1Msps
sampling rate with a true bipolar 2kHz input signal.
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 13 shows
that the LTC2335-16 achieves a typical SNR of 94.4dB in
the ±10.24V range at a 1Msps sampling rate with a true
bipolar 2kHz input signal.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
V22 + V32 + V42 ...VN2
THD = 20log
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 13 shows that
the LTC2335-16 achieves a typical THD of –109dB (N = 6)
in the ±10.24V range at a 1Msps sampling rate with a true
bipolar 2kHz input signal.
233516f
28
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
Power Considerations
Timing and Control
The LTC2335-16 provides four power supply pins: the
positive and negative high voltage power supplies (VCC
and VEE), the 5V core power supply (VDD) and the digital
input/output (I/O) interface power supply (OVDD). As long
as the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individual allowed operating
ranges, including the ability for either of the supplies to be
tied directly to ground. This feature enables the common
mode input range of the LTC2335-16 to be tailored to the
specific application’s requirements. The flexible OVDD supply allows the LTC2335-16 to communicate with CMOS
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems. When using LVDS I/O mode, the range of
OVDD is 2.375V to 5.25V.
CNV Timing
Power Supply Sequencing
The LTC2335-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2335-16 has
an internal power-on-reset (POR) circuit which resets the
converter on initial power-up and whenever VDD drops
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
When employing the internal reference buffer, allow 200ms
for the buffer to power up and recharge the REFBUF bypass
capacitor. Any conversion initiated before these times will
produce invalid results.
The LTC2335-16 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions the S/H circuits
from track mode to hold mode, sampling the input signals
and initiating a conversion. Once a conversion has been
started, it cannot be terminated early except by resetting
the ADC, as discussed in the Reset Timing section. For
optimum performance, drive CNV with a clean, low jitter
signal and avoid transitions on data I/O lines leading up
to the rising edge of CNV. Additionally, for best crosstalk
performance, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
until the conversion is complete. Once CNV is brought high
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conversion process. The CNV timing required to take advantage
of the reduced power nap mode of operation is described
in the Nap Mode section.
Internal Conversion Clock
The LTC2335-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 550ns. With
a minimum acquisition time of 420ns, throughput performance of 1Msps is guaranteed without any external
adjustments. The LTC2335-16 is a multiplexed ADC and
converts one channel per CNV edge, taking a minimum
of 1μs per conversion. Thus, while scanning N channels
(N = 1 to 8), a complete scan takes at least N μs and the
maximum per-channel throughput is 1/N Msps/ch.
Nap Mode
The LTC2335-16 can be placed into nap mode after a conversion has been completed to reduce power consumption
between conversions. In this mode a portion of the device
circuitry is turned off, including circuits associated with
sampling the analog input signals. Nap mode is enabled
233516f
For more information www.linear.com/LTC2335-16
29
LTC2335-16
Applications Information
by keeping CNV high between conversions, as shown in
Figure 14. To initiate a new conversion after entering nap
mode, bring CNV low and hold for at least 420ns before
bringing it high again. The converter acquisition time (tACQ)
is set by the CNV low time (tCNVL) when using nap mode.
Power Down Mode
When PD is brought high, the LTC2335-16 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
draws only a small regulator standby current resulting in a
typical power dissipation of 0.36mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
Reset Timing
A global reset of the LTC2335-16, equivalent to a poweron-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire system to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 15. The reset event is triggered on the second rising edge of PD, and asynchronously
ends based on an internal timer. Reset clears all serial data
output registers and restores the internal sequencer default
state of converting channels 0 through 7 sequentially, all
in SoftSpan 7. If reset is triggered during a conversion, the
conversion is immediately halted. The normal power down
behavior associated with PD going high is not affected by
reset. Once PD is brought low, wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
t CNVL
CNV
tCONV
BUSY
NAP
tACQ
NAP MODE
233516 F14
Figure 14. Nap Mode Timing for the LTC2335-16
tPDH
t WAKE
PD
CNV
BUSY
RESET
tPDL
tCNVH
tCONV
SECOND RISING EDGE OF
PD TRIGGERS RESET
RESET TIME
SET INTERNALLY
233516 F15
Figure 15. Reset Timing for the LTC2335-16
233516f
30
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
Power Dissipation vs Sampling Frequency
Digital Interface
When nap mode is employed, the power dissipation of
the LTC2335-16 decreases as the sampling frequency is
reduced, as shown in Figure 16. This decrease in average power dissipation occurs because a portion of the
LTC2335-16 circuitry is turned off during nap mode, and
the fraction of the conversion cycle (tCYC) spent napping
increases as the sampling frequency (fSMPL) is decreased.
The LTC2335-16 features CMOS and LVDS serial interfaces,
selectable using the LVDS/CMOS pin. The flexible OVDD
supply allows the LTC2335-16 to communicate with any
CMOS logic operating between 1.8V and 5V, including 2.5V
and 3.3V systems, while the LVDS interface supports low
noise digital designs. Together, these I/O interface options
enable the LTC2335-16 to communicate equally well with
legacy microcontrollers and modern FPGAs.
16
SUPPLY CURRENT (mA)
WITH NAP MODE
14 t
CNVL = 500ns
12
10
Serial CMOS I/O Mode
As shown in Figure 17, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data input,
SDI, serial clock output, SCKO, and serial data output,
SDO. Communication with the LTC2335-16 across this
bus occurs during predefined data transaction windows.
Within a window, the device accepts control words on SDI
to configure the SoftSpan range and channel for the next
conversion and program the sequencer, and outputs 24-bit
packets containing the conversion result and configuration
information from the previous conversion on SDO.
IVDD
8
6
4
IVCC
2
IOVDD
0
–2
IVEE
–4
–6
0
200
400
600
800
SAMPLING FREQUENCY (kHz)
1000
233516 F16
Figure 16. Power Dissipation of the LTC2335-16
Decreases with Decreasing Sampling Frequency
CS = PD = 0
SAMPLE N
SAMPLE N + 1
t CYC
tCNVH
t CNVL
CNV
tCONV
BUSY
t ACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SSDISCKI
SCKI
SDI
1
C7
DON’T CARE
2
3
4
5
6
7
C6
C5
C4
C3
C2
C1
t SCKI
8
9 10
t HSDISCKI
11
12
13
t QUIET
t SCKIH
14
15
16
17
18
19 20
t SCKIL
21
22
23
24
C0
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t DSDOBUSYL
t SKEW
t HSDOSCKI
SCKO
t DSDOSCKI
SDO
DON’T CARE
D15
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONVERSION RESULT
0
0
CH2 CH1 CH0 SS2 SS1 SS0 D15
CHANNEL ID
24-BIT PACKET CONVERSION N
SoftSpan
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION) 233516 F17
Figure 17. Serial CMOS I/O Mode, Direct Per-Conversion Configuration
233516f
For more information www.linear.com/LTC2335-16
31
LTC2335-16
Applications Information
New data transaction windows open 10ms after powering up or resetting the LTC2335-16, and at the end of
each conversion on the falling edge of BUSY. The data
transaction should be completed with a minimum tQUIET
time of 20ns prior to the start of the next conversion, as
shown in Figure 17. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no additional analog input settling time required before starting
the next conversion.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO is updated with the latest conversion result from the
just-completed conversion. Rising edges on SCKI serially
clock the conversion result and analog input channel configuration information out on SDO and trigger transitions
on SCKO that are skew-matched to the data on SDO. The
resulting SCKO frequency is half that of SCKI.
SCKI rising edges also latch control words provided on
SDI, which are used to set the SoftSpan range and channel for the next conversion, and program the sequencer.
See the section Configuring the Multiplexer and SoftSpan
Range for further details. SCKI is allowed to idle either
high or low in CMOS I/O mode. As shown in Figure 18,
the CMOS bus is enabled when CS is low and is disabled
and Hi-Z when CS is high, allowing the bus to be shared
across multiple devices.
The data on SDO are formatted as a 24-bit packet consisting
of a 16-bit conversion result followed by two zeros, 3-bit
analog channel ID, and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 17 and 18, if more than
24 SCKI clocks are applied, the 24-bit packet is repeated
indefinitely on SDO.
When interfacing the LTC2335-16 with a standard SPI
bus, capture output data at the receiver on rising edges
of SCKI. SCKO is not used in this case. In other applications, such as interfacing the LTC2335-16 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO in double data rate
(DDR) fashion. Capturing data using SCKO adds robustness to delay variations over temperature and supply.
The LTC2335-16 guarantees a minimum data transfer
window (tACQ – tQUIET) of 400ns while converting at 1Msps.
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 60MHz. Applications
needing to read only the conversion result may send only
16 SCKI pulses and thus have a minimum SCKI frequency
of 40MHz. The LTC2335-16 supports CMOS SCKI frequencies up to 100MHz.
Configuring the Multiplexer and SoftSpan Range in
CMOS I/O Mode
On power-up and after a reset, the LTC2335-16 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI low.
The LTC2335-16 multiplexer and SoftSpan range may
be controlled in two ways, depending on the needs of
the application. If the desired sequence of channels and
SoftSpan ranges are known ahead of time, the LTC233516’s internal sequencer may be programmed with a sequence of up to 16 configurations, and will cycle through
those configurations on subsequent conversions without
further user intervention. Alternately, if ultimate flexibility
is desired, the LTC2335-16 may be directly controlled by
overwriting the sequencer each conversion with the channel and SoftSpan range for the following conversion. This
reconfiguration has no latency and requires no additional
settling time or digital I/O overhead.
Using the Sequencer
To use the internal sequencer of the LTC2335-16, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
specifies the desired channel number and SoftSpan range
for one conversion. The LTC2335-16 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
233516f
32
For more information www.linear.com/LTC2335-16
SDO
tEN
24-BIT RESULT PACKET
PARTIAL WORD
(IGNORED)
RESULT PACKET
(PARTIAL)
Figure 18. Programming the Sequencer for a 10-Conversion Sequence, Serial CMOS Bus Response to CS
24-BIT RESULT PACKET
CONTROL WORD CONTROL WORD
FOR CONV N + 9 FOR CONV N + 10
t DIS
233516 F18
DON’T CARE
Hi-Z
24-BIT RESULT PACKET
CONTROL WORD
FOR CONV N + 8
Hi-Z
CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD
FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7
Hi-Z
CONTROL WORD
FOR CONV N + 1
DON’T CARE
Hi-Z
DON’T CARE
SDI
SCKO
DON’T CARE
SCKI
CS
BUSY
PD = 0
LTC2335-16
Applications Information
233516f
For more information www.linear.com/LTC2335-16
33
LTC2335-16
Applications Information
Each data transaction window is an opportunity to program
the sequencer by clocking in a series of 8-bit control words
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 17 and 18. To program the
sequencer with a series of up to 16 conversion configurations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
The control word format is as follows:
C[7]
C[6]
V
0
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
The V bit (C[7]) controls whether the LTC2335-16 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
If no valid words were provided during the data transaction window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
Thus, once the sequencer has been programmed, simply
hold SDI low during subsequent data transactions to
cycle continually through the programmed sequence of
configurations.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2335-16
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional settling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 17.
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specify the configuration by clocking in the corresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI low. This particular use case is illustrated in
Figure 17. If the desired configuration is not known until
after the conversion data has been read, clock in 24 zeros
on SDI while the 24 bits of data are being read out; since
the V bits of those words are then 0, they are ignored.
Once the configuration has been determined, clock in 8
more bits on SDI which specify the desired configuration
for conversion N+1.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using
positive and negative signal pairs (LVDS+/LVDS−) with bits
differentially encoded as (LVDS+ − LVDS−). These signals
are typically routed using differential transmission lines
with 100Ω characteristic impedance. Logical 1s and 0s
are nominally represented by differential +350mV and
−350mV, respectively. For clarity, all LVDS timing diagrams
and interface discussions adopt the logical rather than
physical convention.
As shown in Figure 19, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communication with the LTC2335-16 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts control words on SDI to configure the
SoftSpan range and channel for the next conversion and
233516f
34
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
CS = PD = 0
SAMPLE N
CNV
(CMOS)
SAMPLE N + 1
t CYC
t CNVH
t CNVL
BUSY
(CMOS)
t CONV
t ACQ
t BUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SSDISCKI
SCKI
(LVDS)
1
2
3
4
5
6
7
8
t SCKI
9
10
11
12
13
14
15
16
17
C7
DON’T CARE
C6
C5
C4
C3
C2
C1
18
19
20
21
22
23
24
t SCKIL
t HSDISCKI
SDI
(LVDS)
t QUIET
t SCKIH
C0
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t DSDOBUSYL
t SKEW
t HSDOSCKI
SCKO
(LVDS)
t DSDOSCKI
SDO
(LVDS)
DON’T CARE
D15
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
CONVERSION RESULT
D0
0
0
CH2 CH1 CH0 SS2 SS1 SS0
CHANNEL ID
24-BIT PACKET CONVERSION N
SoftSpan
D15
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION) 233516 F19
Figure 19. Serial LVDS I/O Mode, Direct Per-Conversion Configuration
program the sequencer, and outputs 24-bit packets containing the conversion result and configuration information
from the previous conversion on SDO.
New data transaction windows open 10ms after powering up or resetting the LTC2335-16, and at the end of
each conversion on the falling edge of BUSY. The data
transaction should be completed with a minimum tQUIET
time of 20ns prior to the start of the next conversion, as
shown in Figure 19. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no additional analog input settling time required before starting
the next conversion.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latest conversion result from the just-completed conversion. Both rising and falling edges on SCKI serially clock the
conversion result and analog input channel configuration
information out on SDO. SCKI is also echoed on SCKO,
skew-matched to the data on SDO. Whenever possible,
it is recommend that rising and falling edges of SCKO be
used to capture DDR serial output data on SDO, as this will
yield the best robustness to delay variations over supply
and temperature.
SCKI rising and falling edges also latch control words
provided on SDI, which are used to set the SoftSpan range
and channel for the next conversion, and program the
sequencer. See the section Configuring the Multiplexer
and SoftSpan Range in LVDS I/O Mode for further details.
As shown in Figure 20, the LVDS bus is enabled when CS
is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices. Due to
the high speeds often involved in LVDS signaling, LVDS
bus sharing must be carefully considered. Transmission
line limitations imposed by the shared bus may limit the
maximum achievable bus clock speed. LVDS inputs are
internally terminated with a 100Ω differential resistor when
CS is low, while outputs must be differentially terminated
with a 100Ω resistor at the receiver (FPGA). SCKI must
idle in the low state in LVDS I/O mode, including when
transitioning CS.
233516f
For more information www.linear.com/LTC2335-16
35
36
SDO
(LVDS)
tEN
24-BIT RESULT PACKET
RESULT PACKET
(PARTIAL)
Figure 20. Programming the Sequencer with a 10-Conversion Sequence, Serial LVDS Bus Response to CS
24-BIT RESULT PACKET
t DIS
233516 F20
DON’T CARE
Hi-Z
24-BIT RESULT PACKET
PARTIAL WORD
(IGNORED)
Hi-Z
CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD
FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7 FOR CONV N + 8 FOR CONV N + 9 FOR CONV N + 10
Hi-Z
CONTROL WORD
FOR CONV N + 1
DON’T CARE
Hi-Z
DON’T CARE
SDI
(LVDS)
SCKO
(LVDS)
DON’T CARE
SCKI
(LVDS)
CS
(CMOS)
BUSY
(CMOS)
PD = 0
LTC2335-16
Applications Information
233516f
For more information www.linear.com/LTC2335-16
LTC2335-16
Applications Information
The data on SDO are formatted as a 24-bit packet consisting
of a 16-bit conversion result followed by two zeros, 3-bit
analog channel ID, and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 19 and 20, if more than
24 SCKI clocks are applied, the 24-bit packet is repeated
indefinitely on SDO.
specifies the desired channel number and SoftSpan range
for one conversion. The LTC2335-16 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
The LTC2335-16 guarantees a minimum data transfer
window (tACQ – tQUIET) of 400ns while converting at 1Msps.
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 30MHz (60Mbps). Applications needing to read only the conversion result may
send only 16 SCKI edges and thus have a minimum SCKI
frequency of 20MHz (40Mbps). The LTC2335-16 supports
LVDS SCKI frequencies up to 250MHz (500Mbps).
Each data transaction window is an opportunity to program
the sequencer by clocking in a series of 8-bit control words
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 19 and 20. To program the
sequencer with a series of up to 16 conversion configurations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
Configuring the Multiplexer and SoftSpan Range in
LVDS I/O Mode
On power-up and after a reset, the LTC2335-16 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI at an LVDS low level.
The LTC2335-16 multiplexer and SoftSpan range may be
controlled in two ways, depending on the needs of the application. If the desired sequence of channels and SoftSpan
ranges are known ahead of time, the LTC2335-16’s internal
sequencer may be programmed with a sequence of up to
16 configurations, and will cycle through those configurations on subsequent conversions without further user
intervention. Alternately if ultimate flexibility is desired, the
LTC2335-16 may be directly controlled by overwriting the
sequencer each conversion with the channel and SoftSpan
range for the following conversion. This reconfiguration
has no latency and requires no additional settling time or
digital I/O overhead.
Using the Sequencer
To use the internal sequencer of the LTC2335-16, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
The control word format is as follows:
C[7]
C[6]
V
0
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
The V bit (C[7]) controls whether the LTC2335-16 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
If no valid words were provided during the data transaction window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
233516f
For more information www.linear.com/LTC2335-16
37
LTC2335-16
Applications Information
Thus, once the sequencer has been programmed, simply
hold SDI at an LVDS low level during subsequent data
transactions to cycle continually through the programmed
sequence of configurations.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2335-16
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional settling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 19.
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specify the configuration by clocking in the corresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI at an LVDS low level. This particular use
case is illustrated in Figure 19. If the desired configuration is not known until after the conversion data has been
read, clock in 24 zeros on SDI while the 24 bits of data
are being read out; since the V bits of those words are
then 0, they are ignored. Once the configuration has been
determined, clock in 8 more bits on SDI which specify the
desired configuration for conversion N+1.
Board Layout
To obtain the best performance from the LTC2335-16, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2412A, the evaluation kit for the LTC2335-16.
233516f
38
For more information www.linear.com/LTC2335-16
LTC2335-16
Package Description
Please refer to http://www.linear.com/product/LTC2335-16#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
9.00 BSC
5.50 REF
7.00 BSC
48
0.50 BSC
1
2
48
SEE NOTE: 4
1
2
9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
XXYY
LTCXXXX
LX-ES
Q_ _ _ _ _ _
e3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
LX48 LQFP 0113 REV A
PACKAGE IN TRAY LOADING ORIENTATION
233516f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2335-16
39
LTC2335-16
Typical Application
Digitize Differential Signals Over a Wide Common Mode Range
IN+
ARBITRARY
+
–
24V
31V
½ LT1124
LOWPASS FILTERS
18pF
0.1µF
2.49k
COMMON MODE
INPUT RANGE
6.6nF
2.49k
IN–
–
+
LTC2335-16
6.6nF
18pF
0V
VCC
IN0+
IN0–
549Ω
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
31V
49.9Ω
49.9Ω
½ LT1124
BW ~ 500kHz
–5V
ONLY CHANNEL 0 SHOWN FOR CLARITY
VEE REFBUF
0.1µF
REFIN
47µF
0.1µF
–5V
233516 TA02
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233516f
40 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2335-16
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2335-16
LT 0116 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2016