TI CC430F6127 Msp430â ¢ soc with rf core Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
MSP430™ SoC with RF Core
FEATURES
1
•
23
•
•
•
True System-on-Chip (SoC) for Low-Power
Wireless Communication Applications
Wide Supply Voltage Range:
3.6 V Down to 1.8 V
Ultra-Low Power Consumption:
– CPU Active Mode (AM): 160 µA/MHz
– Standby Mode (LPM3 RTC Mode):2.0 µA
– Off Mode (LPM4 RAM Retention): 1.0 µA
– Radio in RX: 15 mA, 250 kbps, 915 MHz
MSP430™ System and Peripherals
– 16-Bit RISC Architecture, Extended
Memory, up to 20-MHz System Clock
– Wake-Up From Standby Mode in Less
Than 6 µs
– Flexible Power Management System With
SVS and Brownout
– Unified Clock System With FLL
– 16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
– 16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
– Hardware Real-Time Clock
– Two Universal Serial Communication
Interfaces
– USCI_A0 Supports UART, IrDA, SPI
– USCI_B0 Supports I2C, SPI
– 12-Bit A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
Features (CC430F613x and CC430F513x
Only)
– Comparator
– Integrated LCD Driver With Contrast
Control for up to 96 Segments
(CC430F61xx Only)
– 128-bit AES Security Encryption and
Decryption Coprocessor
– 32-Bit Hardware Multiplier
– Three-Channel Internal DMA
– Serial Onboard Programming, No External
Programming Voltage Needed
– Embedded Emulation Module (EEM)
•
•
•
High-Performance Sub-1-GHz RF Transceiver
Core
– Same as in CC1101
– Wide Supply Voltage Range: 2.0 V to 3.6 V
– Frequency Bands: 300 MHz to 348 MHz,
389 MHz to 464 MHz, and 779 MHz to
928 MHz
– Programmable Data Rate From 0.6 kBaud
to 500 kBaud
– High Sensitivity (-117 dBm at 0.6 kBaud, 111 dBm at 1.2 kBaud, 315 MHz, 1% Packet
Error Rate)
– Excellent Receiver Selectivity and Blocking
Performance
– Programmable Output Power Up to +12
dBm for All Supported Frequencies
– 2-FSK, 2-GFSK, and MSK Supported as well
as OOK and Flexible ASK Shaping
– Flexible Support for Packet-Oriented
Systems: On-Chip Support for Sync Word
Detection, Address Check, Flexible Packet
Length, and Automatic CRC Handling
– Support for Automatic Clear Channel
Assessment (CCA) Before Transmitting (for
Listen-Before-Talk Systems)
– Digital RSSI Output
– Suited for Systems Targeting Compliance
With EN 300 220 (Europe) and
FCC CFR Part 15 (US)
– Suited for Systems Targeting Compliance
With Wireless M-Bus Standard EN 137574:2005
– Support for Asynchronous and
Synchronous Serial Receive or Transmit
Mode for Backward Compatibility With
Existing Radio Communication Protocols
Family Members are Summarized in Table 1
For Complete Module Descriptions, See the
CC430 Family User's Guide (SLAU259)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
I2C is a trademark of others.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
www.ti.com
DESCRIPTION
The Texas Instruments CC430 family of ultra-low-power microcontroller system-on-chip with integrated RF
transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of
applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life
in portable measurement applications. The device features the powerful MSP430 16-bit RISC CPU, 16-bit
registers, and constant generators that contribute to maximum code efficiency.
The CC430 family provides a tight integration between the microcontroller core, its peripherals, software, and the
RF transceiver, making these true system-on-chip solutions easy to use as well as improving performance.
The CC430F61xx series are microcontroller system-on-chip configurations combining the excellent performance
of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32 kB of in-system
programmable flash memory, up to 4 kB of RAM, two 16-bit timers, a high-performance 12-bit A/D converter with
eight external inputs plus internal temperature and battery sensors on CC430F613x devices, comparator,
universal serial communication interfaces (USCI), 128-bit AES security accelerator, hardware multiplier, DMA,
real-time clock module with alarm capabilities, LCD driver, and up to 44 I/O pins.
The CC430F513x series are microcontroller system-on-chip configurations combining the excellent performance
of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32 kB of in-system
programmable flash memory, up to 4 kB of RAM, two 16-bit timers, a high performance 12-bit A/D converter with
six external inputs plus internal temperature and battery sensors, comparator, universal serial communication
interfaces (USCI), 128-bit AES security accelerator, hardware multiplier, DMA, real-time clock module with alarm
capabilities, and up to 30 I/O pins.
Typical applications for these devices include wireless analog and digital sensor systems, heat cost allocators,
thermostats, metering (AMR or AMI), and smart grid wireless networks.
Family members available are summarized in Table 1.
For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
Table 1. Family Members
USCI
(1)
(2)
2
Device
Program
(KB)
SRAM (KB)
Timer_A (1)
LCD_B (2)
Channel A:
UART, LIN,
IrDA, SPI
Channel B:
SPI, I2C
ADC12_A (2)
Comp_B
I/O
Package
Type
CC430F6137
32
4
5, 3
96 seg
1
1
8 ext,
4 int ch.
8 ch.
44
64 RGC
CC430F6135
16
2
5, 3
96 seg
1
1
8 ext,
4 int ch.
8 ch.
44
64 RGC
CC430F6127
32
4
5, 3
96 seg
1
1
n/a
8 ch.
44
64 RGC
CC430F6126
32
2
5, 3
96 seg
1
1
n/a
8 ch.
44
64 RGC
CC430F6125
16
2
5, 3
96 seg
1
1
n/a
8 ch.
44
64 RGC
6 ch.
30
48 RGZ
CC430F5137
32
4
5, 3
n/a
1
1
6 ext,
4 int ch.
CC430F5135
16
2
5, 3
n/a
1
1
6 ext,
4 int ch.
6 ch.
30
48 RGZ
CC430F5133
8
2
5, 3
n/a
1
1
6 ext,
4 int ch.
6 ch.
30
48 RGZ
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 5, 3 would represent two instantiations of Timer_A, the first
instantiation having 5 and the second instantiation having 3 capture compare registers and PWM output generators, respectively.
n/a = not available
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ECCN 5E002 TSPA - Technology / Software Publicly Available
www.ti.com
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 2. Ordering Information (1)
TA
PACKAGED DEVICES (2)
PLASTIC 64-PIN QFN (RGC)
PLASTIC 48-PIN QFN (RGZ)
CC430F6137IRGC
CC430F5137IRGZ
CC430F6135IRGC
CC430F5135IRGZ
CC430F6127IRGC
CC430F5133IRGZ
–40°C to 85°C
CC430F6126IRGC
CC430F6125IRGC
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2009–2013, Texas Instruments Incorporated
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
www.ti.com
CC430F613x Functional Block Diagram
XIN XOUT
(32kHz)
MCLK
Unified
Clock
System
P1.x/P2.x
2x8
REF
ACLK
Comp_B
ADC12
SMCLK
Voltage
Reference
DMA
Controller
3 Channel
Bus
Cntrl
Logic
MAB
P3.x/P4.x
2x8
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3/P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
P5.x
1x8
I/O Ports
P5
1x8 I/Os
MDB
Sub-1GHz
Radio
(CC1101)
SYS
MDB
EEM
(S: 3+1)
Flash
RAM
32kB
16kB
4kB
2kB
CRC16
Watchdog
CPU Interface
MPY32
Port
Mapping
Controller
MODEM
MDB
Spy-BiWire
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XIN RF_XOUT
(26MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO
SVM/SVS
Brownout
TA0
5 CC
Registers
TA1
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
LCD_B
96
Segments
1,2,3,4
Mux
AES128
Security
En-/Decryption
RF/ANALOG
TX & RX
RF_P
4
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RF_N
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
P2.1/PM_TA1CCR0A/CB1/A1
P2.2/PM_TA1CCR1A/CB2/A2
P2.3/PM_TA1CCR2A/CB3/A3
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREFP2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
P2.6/PM_ACLK/CB6/A6
P2.7/PM_ADC12CLK/PM_DMAE0/CB7/A7
AVCC
P5.0/XIN
P5.1/XOUT
AVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
2
47
3
46
4
45
5
44
6
43
7
42
8
9
CC430F613x
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P3.7/PM_SMCLK/S17
P3.6/PM_RFGDO1/S16
P3.5/PM_TA0CCR4A/S15
P3.4/PM_TA0CCR3A/S14
P3.3/PM_TA0CCR2A/S13
P3.2/PM_TA0CCR1A/S12
P3.1/PM_TA0CCR0A/S11
P3.0/PM_CBOUT0/PM_TA0CLK/S10
DVCC
P4.7/S9
P4.6/S8
P4.5/S7
P4.4/S6
P4.3/S5
P4.2/S4
P4.1/S3
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
LCDCAP/R33
COM0
P5.7/COM1/S26
P5.6/COM2/S25
P5.5/COM3/S24
P5.4/S23
VCORE
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
P1.1/PM_RFGDO2/S19
P1.0/PM_RFGDO0/S18
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
R_BIAS
AVCC_RF
AVCC_RF
RF_N
RF_P
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
P5.2/S0
P5.3/S1
P4.0/S2
VSS
Exposed die
attached pad
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 10 for details.
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2013, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
www.ti.com
CC430F612x Functional Block Diagram
XIN XOUT
(32kHz)
MCLK
Unified
Clock
System
P1.x/P2.x
2x8
REF
ACLK
Comp_B
Voltage
Reference
SMCLK
DMA
Controller
3 Channel
Bus
Cntrl
Logic
MAB
P3.x/P4.x
2x8
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3/P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
P5.x
1x8
I/O Ports
P5
1x8 I/Os
MDB
Sub-1GHz
Radio
(CC1101)
SYS
MDB
EEM
(S: 3+1)
Flash
RAM
32kB
32kB
16kB
4kB
2kB
2kB
CRC16
Watchdog
CPU Interface
MPY32
Port
Mapping
Controller
MODEM
MDB
Spy-BiWire
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XIN RF_XOUT
(26MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO
SVM/SVS
Brownout
TA0
5 CC
Registers
TA1
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
LCD_B
96
Segments
1,2,3,4
Mux
AES128
Security
En-/Decryption
RF/ANALOG
TX & RX
RF_P
6
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RF_N
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
www.ti.com
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
P2.0/PM_CBOUT1/PM_TA1CLK/CB0
P2.1/PM_TA1CCR0A/CB1
P2.2/PM_TA1CCR1A/CB2
P2.3/PM_TA1CCR2A/CB3
P2.4/PM_RTCCLK/CB4
P2.5/PM_SVMOUT/CB5
P2.6/PM_ACLK/CB6
P2.7/PM_DMAE0/CB7
AVCC
P5.0/XIN
P5.1/XOUT
AVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
2
47
3
46
4
45
5
44
6
43
7
42
8
9
CC430F612x
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P3.7/PM_SMCLK/S17
P3.6/PM_RFGDO1/S16
P3.5/PM_TA0CCR4A/S15
P3.4/PM_TA0CCR3A/S14
P3.3/PM_TA0CCR2A/S13
P3.2/PM_TA0CCR1A/S12
P3.1/PM_TA0CCR0A/S11
P3.0/PM_CBOUT0/PM_TA0CLK/S10
DVCC
P4.7/S9
P4.6/S8
P4.5/S7
P4.4/S6
P4.3/S5
P4.2/S4
P4.1/S3
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
LCDCAP/R33
COM0
P5.7/COM1/S26
P5.6/COM2/S25
P5.5/COM3/S24
P5.4/S23
VCORE
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
P1.1/PM_RFGDO2/S19
P1.0/PM_RFGDO0/S18
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
R_BIAS
AVCC_RF
AVCC_RF
RF_N
RF_P
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
P5.2/S0
P5.3/S1
P4.0/S2
VSS
Exposed die
attached pad
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 10 for details.
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2013, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
www.ti.com
CC430F513x Functional Block Diagram
XIN XOUT
(32kHz)
MCLK
Unified
Clock
System
P1.x/P2.x
2x8
REF
ACLK
Comp_B
ADC12
SMCLK
Voltage
Reference
DMA
Controller
3 Channel
Bus
Cntrl
Logic
MAB
I/O Ports
P1/P2
2x8 I/Os
P5.x
P3.x
1x8
I/O Ports
P3
1x8 I/Os
1x2
I/O Ports
P5
1x2 I/Os
PA
1x16 I/Os
MDB
Sub-1GHz
Radio
(CC1101)
SYS
MDB
EEM
(S: 3+1)
Flash
RAM
32kB
16kB
8kB
4kB
2kB
CRC16
Watchdog
CPU Interface
MPY32
Port
Mapping
Controller
MODEM
MDB
Spy-BiWire
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
MAB
CPUXV2
incl. 16
Registers
JTAG
Interface
RF_XIN RF_XOUT
(26MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO
SVM/SVS
Brownout
TA0
5 CC
Registers
TA1
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
AES128
Security
En-/Decryption
RF/ANALOG
TX & RX
RF_P
8
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RF_N
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
P2.2/PM_TA1CCR1A/CB2/A2
P2.1/PM_TA1CCR0A/CB1/A1
PJ.3/TCK
PJ.2/TMS
TEST/SBWTCK
RST/NMI/SBWTDIO
AVSS
DVCC
P5.0/XIN
P5.1/XOUT
RGZ PACKAGE
(TOP VIEW)
AVCC
P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
P2.3/PM_TA1CCR2A/CB3/A3
www.ti.com
CC430F613x
CC430F612x
CC430F513x
1
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
PJ.0/TDO
PJ.1/TDI/TCLK
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
3
34
GUARD
P1.7/PM_UCA0CLK/PM_UCB0STE
4
33
R_BIAS
P1.6/PM_UCA0TXD/PM_UCA0SIMO
5
32
AVCC_RF
P1.5/PM_UCA0RXD/PM_UCA0SOMI
6
31
AVCC_RF
VCORE
7
30
RF_N
CC430F513x
DVCC
8
29
RF_P
P1.4/PM_UCB0CLK/PM_UCA0STE
9
28
AVCC_RF
P1.3/PM_UCB0SIMO/PM_UCB0SDA
10
27
AVCC_RF
P1.2/PM_UCB0SOMI/PM_UCB0SCL
11
26
RF_XOUT
P2.6/PM_ACLK
P2.7/PM_ADC12CLK/PM_DMAE0
DVCC
P3.0/PM_CBOUT0/PM_TA0CLK
P3.1/PM_TA0CCR0A
P3.2/PM_TA0CCR1A
P3.4/PM_TA0CCR3A
P3.3/PM_TA0CCR2A
P3.5/PM_TA0CCR4A
P3.7/PM_SMCLK
P3.6/PM_RFGDO1
25
12
13 14 15 16 17 18 19 20 21 22 23 24
P1.0/PM_RFGDO0
P1.1/PM_RFGDO2
RF_XIN
VSS
Exposed die
attached pad
The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 10 for details.
Copyright © 2009–2013, Texas Instruments Incorporated
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CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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www.ti.com
Table 3. CC430F613x and CC430F612x Terminal Functions
TERMINAL
NAME
P1.7/ PM_UCA0CLK/
PM_UCB0STE/ R03
NO.
1
I/O (1)
DESCRIPTION
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
Input/output port of lowest analog LCD voltage (V5)
P1.6/ PM_UCA0TXD/
PM_UCA0SIMO/ R13/LCDREF
2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
P1.5/ PM_UCA0RXD/
PM_UCA0SOMI/ R23
3
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/ R33
4
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
COM0
5
O
LCD common output COM0 for LCD backplane
P5.7/ COM1/ S26
6
I/O
General-purpose digital I/O
LCD common output COM1 for LCD backplane
LCD segment output S26
P5.6/ COM2/ S25
7
I/O
General-purpose digital I/O
LCD common output COM2 for LCD backplane
LCD segment output S25
P5.5/ COM3/ S24
8
I/O
General-purpose digital I/O
LCD common output COM3 for LCD backplane
LCD segment output S24
P5.4/ S23
9
I/O
General-purpose digital I/O
LCD segment output S23
VCORE
10
Regulated core power supply
DVCC
11
Digital power supply
P1.4/ PM_UCB0CLK/
PM_UCA0STE/ S22
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
LCD segment output S22
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA/ S21
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data
LCD segment output S21
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL/ S20
14
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock
LCD segment output S20
P1.1/ PM_RFGDO2/ S19
15
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
LCD segment output S19
P1.0/ PM_RFGDO0/ S18
16
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
LCD segment output S18
P3.7/ PM_SMCLK/ S17
17
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
LCD segment output S17
P3.6/ PM_RFGDO1/ S16
18
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
LCD segment output S16
P3.5/ PM_TA0CCR4A/ S15
19
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
LCD segment output S15
P3.4/ PM_TA0CCR3A/ S14
20
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
LCD segment output S14
P3.3/ PM_TA0CCR2A/ S13
21
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
LCD segment output S13
(1)
10
I = input, O = output
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 3. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
P3.2/ PM_TA0CCR1A/ S12
22
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
LCD segment output S12
P3.1/ PM_TA0CCR0A/ S11
23
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
LCD segment output S11
P3.0/ PM_CBOUT0/PM_TA0CLK/
S10
24
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output; TA0 clock input
LCD segment output S10
DVCC
25
P4.7/ S9
26
I/O
General-purpose digital I/O
LCD segment output S9
P4.6/ S8
27
I/O
General-purpose digital I/O
LCD segment output S8
P4.5/ S7
28
I/O
General-purpose digital I/O
LCD segment output S7
P4.4/ S6
29
I/O
General-purpose digital I/O
LCD segment output S6
P4.3/ S5
30
I/O
General-purpose digital I/O
LCD segment output S5
P4.2/ S4
31
I/O
General-purpose digital I/O
LCD segment output S4
P4.1/ S3
32
I/O
General-purpose digital I/O
LCD segment output S3
P4.0/ S2
33
I/O
General-purpose digital I/O
LCD segment output S2
P5.3/ S1
34
I/O
General-purpose digital I/O
LCD segment output S1
P5.2/ S0
35
I/O
General-purpose digital I/O
LCD segment output S0
RF_XIN
36
I
Input terminal for RF crystal oscillator, or external clock input
RF_XOUT
37
O
Output terminal for RF crystal oscillator
AVCC_RF
38
AVCC_RF
39
Digital power supply
Radio analog power supply
Radio analog power supply
RF_P
40
RF
I/O
RF_N
41
RF
I/O
AVCC_RF
42
Radio analog power supply
AVCC_RF
43
Radio analog power supply
RBIAS
44
External bias resistor for radio reference current
GUARD
45
Power supply connection for digital noise isolation
PJ.0/ TDO
46
I/O
General-purpose digital I/O
Test data output port
PJ.1/ TDI/ TCLK
47
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS
48
I/O
General-purpose digital I/O
Test mode select
PJ.3/ TCK
49
I/O
General-purpose digital I/O
Test clock
TEST/ SBWTCK
50
I
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Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
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Table 3. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O (1)
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
RST/NMI/ SBWTDIO
51
DVCC
52
Digital power supply
AVSS
53
Analog ground supply for ADC12
P5.1/ XOUT
54
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN
55
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC
56
P2.7/ PM_ADC12CLK/
PM_DMAE0/ CB7 (/A7)
57
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output; DMA external trigger input
Comparator_B input CB7
Analog input A7 – 12-bit ADC (CC430F613x only)
P2.6/ PM_ACLK/ CB6 (/A6)
58
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
Comparator_B input CB6
Analog input A6 – 12-bit ADC (CC430F613x only)
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC (CC430F613x only)
Output of reference voltage to the ADC (CC430F613x only)
Input for an external reference voltage to the ADC (CC430F613x only)
P2.5/ PM_SVMOUT/ CB5
(/A5/ VREF+/ VeREF+)
59
I/O
DESCRIPTION
Analog power supply
P2.4/ PM_RTCCLK/ CB4
(/A4/ VREF-/ VeREF-)
60
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC (CC430F613x only)
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage (CC430F613x only)
P2.3/ PM_TA1CCR2A/ CB3 (/A3)
61
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC (CC430F613x only)
P2.2/ PM_TA1CCR1A/ CB2 (/A2)
62
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC (CC430F613x only)
P2.1/PM_TA1CCR0A/CB1(/A1)
63
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC (CC430F613x only)
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0 (/A0)
64
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output; TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC (CC430F613x only)
VSS - Exposed die attach pad
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Ground supply
The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 4. CC430F513x Terminal Functions
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
P2.2/ PM_TA1CCR1A/ CB2/ A2
1
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC
P2.1/ PM_TA1CCR0A/ CB1/ A1
2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0/ A0
3
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output; TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/
PM_UCB0STE
4
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output / USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/
PM_UCA0SIMO
5
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/
PM_UCA0SOMI
6
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
VCORE
7
Regulated core power supply
DVCC
8
Digital power supply
P1.4/ PM_UCB0CLK/
PM_UCA0STE
9
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output / USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA
10
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out/USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL
11
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in/UCSI_B0 I2C clock
P1.1/ PM_RFGDO2
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
P1.0/ PM_RFGDO0
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
P3.7/ PM_SMCLK
14
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
P3.6/ PM_RFGDO1
15
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
P3.5/ PM_TA0CCR4A
16
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
P3.4/ PM_TA0CCR3A
17
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
P3.3/ PM_TA0CCR2A
18
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
P3.2/ PM_TA0CCR1A
19
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
P3.1/ PM_TA0CCR0A
20
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
P3.0/ PM_CBOUT0/ PM_TA0CLK
21
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output; TA0 clock input
DVCC
22
P2.7/ PM_ADC12CLK/
PM_DMAE0
23
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output; DMA external trigger input
P2.6/ PM_ACLK
24
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
RF_XIN
25
I
Input terminal for RF crystal oscillator, or external clock input
RF_XOUT
26
O
Output terminal for RF crystal oscillator
AVCC_RF
27
(1)
Digital power supply
Radio analog power supply
I = input, O = output
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Table 4. CC430F513x Terminal Functions (continued)
TERMINAL
NAME
AVCC_RF
NO.
I/O (1)
28
DESCRIPTION
Radio analog power supply
RF_P
29
RF
I/O
RF_N
30
RF
I/O
AVCC_RF
31
Radio analog power supply
AVCC_RF
32
Radio analog power supply
RBIAS
33
External bias resistor for radio reference current
GUARD
34
Power supply connection for digital noise isolation
PJ.0/ TDO
35
I/O
General-purpose digital I/O
Test data output port
PJ.1/ TDI/ TCLK
36
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS
37
I/O
General-purpose digital I/O
Test mode select
PJ.3/ TCK
38
I/O
General-purpose digital I/O
Test clock
TEST/ SBWTCK
39
I
RST/NMI/ SBWTDIO
40
I/O
DVCC
41
Digital power supply
AVSS
42
Analog ground supply for ADC12
P5.1/ XOUT
43
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN
44
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC
45
Analog power supply
46
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P2.5/ PM_SVMOUT/ CB5/
A5/ VREF+/ VeREF+
Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
P2.4/ PM_RTCCLK/ CB4/
A4/ VREF-/ VeREF-
47
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
P2.3/ PM_TA1CCR2A/ CB3/ A3
48
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC
VSS - Exposed die attach pad
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Ground supply
The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
SHORT-FORM DESCRIPTION
Sub-1-GHz Radio
The implemented sub-1-GHz radio module is based on the industry-leading CC1101, requiring very few external
components. Figure 1 shows a high-level block diagram of the implemented radio.
0
RF_N
FREQ
SYNTH
90
PA
BIAS
RC OSC
RBIAS
XOSC
RF_XIN
MODULATOR
RF_P
INTERFACE TO MCU
ADC
RXFIFO
LNA
TXFIFO
ADC
PACKET HANDLER
DEMODULATOR
RADIO CONTROL
RF_XOUT
Figure 1. Sub-1-GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and
down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic
gain control (AGC), fine channel filtering, demodulation bit and packet synchronization are performed digitally.
The transmitter part is based on direct synthesis of the RF frequency. The frequency synthesizer includes a
completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the downconversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the
ADC and the digital part.
A memory mapped register interface is used for data access, configuration, and status request by the CPU.
The digital baseband includes support for channel configuration, packet handling, and data buffering.
For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
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CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Operating Modes
The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
– Complete data retention
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Comparator_B
Comparator_B Interrupt Flags (CBIV) (1)
Maskable
0FFF8h
60
Watchdog Interval Timer Mode
WDTIFG
Maskable
0FFF6h
59
USCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
Maskable
0FFF4h
58
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
Flags (UCB0IV) (1)
Maskable
0FFF2h
57
ADC12_A
(Reserved on CC430F612x)
ADC12IFG0 ... ADC12IFG15 (ADC12IV) (1)
Maskable
0FFF0h
56
TA0
TA0CCR0 CCIFG0
Maskable
0FFEEh
55
TA0
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1)
Maskable
0FFECh
54
RF1A CC1101-based Radio
Radio Interface Interrupt Flags (RF1AIFIV)
Radio Core Interrupt Flags (RF1AIV)
Maskable
0FFEAh
53
Maskable
0FFE8h
52
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
TA1
TA1CCR0 CCIFG0
Maskable
0FFE6h
51
TA1
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1)
Maskable
0FFE4h
50
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV) (1)
Maskable
0FFE2h
49
I/O Port P2
(1)
Maskable
0FFE0h
48
Maskable
0FFDEh
47
LCD_B
(Reserved on CC430F513x)
P2IFG.0 to P2IFG.7 (P2IV)
LCD_B Interrupt Flags (LCDBIV)
(1)
RTC_A
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1)
Maskable
0FFDCh
46
AES
AESRDYIFG
Maskable
0FFDAh
45
0FFD8h
44
Reserved
(1)
(2)
(3)
(4)
(1)
Reserved
(4)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
Table 6. Memory Organization
Main Memory
(flash)
CC430F6137
CC430F6127
CC430F5137 (1)
CC430F6126 (1)
CC430F6135
CC430F6125
CC430F5135 (1)
CC430F5133 (1)
32kB
32kB
16kB
8kB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
32kB
00FFFFh to 008000h
32kB
00FFFFh to 008000h
16kB
00FFFFh to 00C000h
8kB
00FFFFh to 00E000h
4kB
2kB
2kB
2kB
Sect 1
2kB
002BFFh to 002400h
not available
not available
not available
Sect 0
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Total
Size
Main: Interrupt
vector
Main: code
memory
Bank 0
Total
Size
RAM
Device
Descriptor
Information
memory (flash)
Bootstrap loader
(BSL) memory
(flash)
Peripherals
(1)
All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.
Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the
BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).
Table 7. UART BSL Pin Requirements and Functions
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DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.6
Data transmit
P1.5
Data receive
VCC
Power supply
VSS
Ground supply
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JTAG Operation
JTAG Standard Interface
The CC430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 8. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface. Spy-BiWire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 9. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The
CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and four segments of information memory (Info A to Info D)
of 128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments Info A to Info D can be erased individually, or as a group with the main memory segments.
Segments Info A to Info D are also called information memory.
• Segment A can be locked separately.
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RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however, all data is lost. Features of the RAM memory include:
• RAM memory has n sectors of 2k bytes each.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal
very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an
integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module
is designed to meet the requirements of both low system cost and low-power consumption. The UCS module
features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast
turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal lowfrequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Digital I/O
There are up to five 8-bit I/O ports implemented: ports P1 through P5.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).
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Port Mapping Controller
The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of
ports P1 through P3.
Table 10. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION (PxDIR.y=0)
0
PM_NONE
None
1 (1)
2 (1)
PM_CBOUT1
TA1 clock input
-
PM_ACLK
None
ACLK output
4
PM_MCLK
None
MCLK output
5
PM_SMCLK
None
SMCLK output
6
PM_RTCCLK
None
RTCCLK output
PM_ADC12CLK
-
ADC12CLK output
PM_DMAE0
DMA external trigger input
-
8
PM_SVMOUT
None
SVM output
9
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
10
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
11
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
12
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
13
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
14
PM_TA1CCR0A
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
15
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
16
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
18 (2)
19 (3)
20 (4)
21 (4)
22 (5)
(5)
Comparator_B output (on TA1 clock
input)
PM_TA1CLK
17 (2)
(4)
TA0 clock input
3
7 (1)
(1)
(2)
(3)
DVSS
Comparator_B output (on TA0 clock
input)
PM_CBOUT0
PM_TA0CLK
OUTPUT PIN FUNCTION
(PxDIR.y=1)
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
23
PM_RFGDO0
Radio GDO0 (direction controlled by Radio)
24
PM_RFGDO1
Radio GDO1 (direction controlled by Radio)
25
PM_RFGDO2
26
Reserved
Radio GDO2 (direction controlled by Radio)
None
DVSS
Input or output function is selected by the corresponding setting in the port direction register PxDIR.
UART or SPI functionality is determined by the selected USCI mode.
UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
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Table 10. Port Mapping, Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION (PxDIR.y=0)
OUTPUT PIN FUNCTION
(PxDIR.y=1)
27
Reserved
None
DVSS
28
Reserved
None
DVSS
29
Reserved
None
DVSS
None
DVSS
30
Reserved
31 (0FFh)
(6)
(6)
Disables the output driver as well as the input Schmitt-trigger to prevent
parasitic cross currents when applying analog signals.
PM_ANALOG
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
Table 11. Default Mapping
22
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
(PxDIR.y=0)
OUTPUT PIN FUNCTION
(PxDIR.y=1)
P1.0/P1MAP0
PM_RFGDO0
None
Radio GDO0
P1.1/P1MAP1
PM_RFGDO2
None
Radio GDO2
P1.2/P1MAP2
PM_UCB0SOMI/PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P1.3/P1MAP3
PM_UCB0SIMO/PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P1.4/P1MAP4
PM_UCB0CLK/PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
P1.5/P1MAP5
PM_UCA0RXD/PM_UCA0SOMI
USCI_A0 UART RXD (Direction controlled by USCI - input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P1.6/P1MAP6
PM_UCA0TXD/PM_UCA0SIMO
USCI_A0 UART TXD (Direction controlled by USCI - output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P1.7/P1MAP7
PM_UCA0CLK/PM_UCB0STE
USCI_A0 clock input/output (direction controlled by USCI),
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
P2.0/P2MAP0
PM_CBOUT1/PM_TA1CLK
TA1 clock input
Comparator_B output
P2.1/P2MAP1
PM_TA1CCR0A
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
P2.2/P2MAP2
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
P2.3/P2MAP3
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
P2.4/P2MAP4
PM_RTCCLK
None
RTCCLK output
P2.5/P2MAP5
PM_SVMOUT
None
SVM output
P2.6/P2MAP6
PM_ACLK
None
ACLK output
P2.7/P2MAP7
PM_ADC12CLK/PM_DMAE0
DMA external trigger input
ADC12CLK output
P3.0/P3MAP0
PM_CBOUT0/PM_TA0CLK
TA0 clock input
Comparator_B output
P3.1/P3MAP1
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P3.2/P3MAP2
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P3.3/P3MAP3
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P3.4/P3MAP4
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
P3.5/P3MAP5
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
P3.6/P3MAP6
PM_RFGDO1
None
Radio GDO1
P3.7/P3MAP7
PM_SMCLK
None
SMCLK output
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System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 12. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
SYSRSTIV, System Reset
019Eh
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Reserved
08h
SYSSNIV, System NMI
SYSUNIV, User NMI
019Ch
019Ah
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Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
DoPOR (POR)
14h
WDT timeout (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral.
Table 13. DMA Trigger Assignments (1)
TRIGGER
(1)
(2)
CHANNEL
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
Reserved
Reserved
Reserved
6
Reserved
Reserved
Reserved
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
Reserved
Reserved
Reserved
21
Reserved
Reserved
Reserved
22
Reserved
Reserved
Reserved
23
Reserved
Reserved
(2)
ADC12IFGx
Reserved
(2)
ADC12IFGx (2)
24
ADC12IFGx
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
Only on CC430F613x and CC430F513x. Reserved on CC430F612x.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the timer can be configured as an interval timer and can generate interrupts at selected time
intervals.
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CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
AES128 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to
the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
Universal Serial Communication Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The USCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
A USCI_A0 and USCI_B0 module are implemented.
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TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA0 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TA0CLK
TACLK
(1)
(2)
26
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
RFCLK/192 (1)
INCLK
PM_TA0CCR0A
CCI0A
DVSS
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT
SIGNAL
PM_TA0CCR0A
CCR0
TA0
DVCC
VCC
PM_TA0CCR1A
CCI1A
PM_TA0CCR1A
CBOUT (internal)
CCI1B
ADC12 (internal) (2)
ADC12SHSx = {1}
DVSS
GND
DVCC
VCC
PM_TA0CCR2A
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
PM_TA0CCR3A
CCI3A
GDO1 from Radio
(internal)
CCI3B
DVSS
GND
DVCC
VCC
PM_TA0CCR4A
CCI4A
GDO2 from Radio
(internal)
CCI4B
DVSS
GND
DVCC
VCC
CCR1
TA1
PM_TA0CCR2A
CCR2
TA2
PM_TA0CCR3A
CCR3
TA3
PM_TA0CCR4A
CCR4
TA4
If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
Only on CC430F613x and CC430F513x
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TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 15. TA1 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
RFCLK/192 (1)
INCLK
PM_TA1CCR0A
CCI0A
RF Async. Output
(internal)
CCI0B
(1)
DVSS
GND
DVCC
VCC
PM_TA1CCR1A
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
PM_TA1CCR2A
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PZ
NA
PM_TA1CCR0A
CCR0
TA0
RF Async. Input (internal)
PM_TA1CCR1A
CCR1
TA1
PM_TA1CCR2A
CCR2
TA2
If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated realtime clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that
can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode
integrates an internal calendar which compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device. These include the ADC12_A, LCD_B, and COMP_B modules.
LCD_B (Only CC430F613x and CC430F612x)
The LCD_B driver generates the segment and common signals required to drive a liquid crystal display (LCD).
The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The
module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage and thus contrast by software. The module also provides an
automatic blinking capability for individual segments.
Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
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ADC12_A (Only CC430F613x and CC430F513x)
The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
Embedded Emulation Module (EEM) (S Version)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM
implemented on all devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
28
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Peripheral File Map
Table 16. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 17)
0100h
000h-01Fh
PMM (see Table 18)
0120h
000h-00Fh
Flash Control (see Table 19)
0140h
000h-00Fh
CRC16 (see Table 20)
0150h
000h-007h
RAM Control (see Table 21)
0158h
000h-001h
Watchdog (see Table 22)
015Ch
000h-001h
UCS (see Table 23)
0160h
000h-01Fh
SYS (see Table 24)
0180h
000h-01Fh
Shared Reference (see Table 25)
01B0h
000h-001h
Port Mapping Control (see Table 26)
01C0h
000h-007h
Port Mapping Port P1 (see Table 27)
01C8h
000h-007h
Port Mapping Port P2 (see Table 28)
01D0h
000h-007h
Port Mapping Port P3 (see Table 29)
01D8h
000h-007h
Port P1, P2 (see Table 30)
0200h
000h-01Fh
Port P3, P4 (see Table 31)
(P4 not available on CC430F513x)
0220h
000h-01Fh
Port P5 (see Table 32)
0240h
000h-01Fh
Port PJ (see Table 33)
0320h
000h-01Fh
TA0 (see Table 34)
0340h
000h-03Fh
TA1 (see Table 35)
0380h
000h-03Fh
RTC_A (see Table 36)
04A0h
000h-01Fh
32-bit Hardware Multiplier (see Table 37)
04C0h
000h-02Fh
DMA Module Control (see Table 38)
0500h
000h-00Fh
DMA Channel 0 (see Table 39)
0510h
000h-00Fh
DMA Channel 1 (see Table 40)
0520h
000h-00Fh
DMA Channel 2 (see Table 41)
0530h
000h-00Fh
USCI_A0 (see Table 42)
05C0h
000h-01Fh
USCI_B0 (see Table 43)
05E0h
000h-01Fh
ADC12 (see Table 44)
(only CC430F613x and CC430F513x)
0700h
000h-03Fh
Comparator_B (see Table 45)
08C0h
000h-00Fh
AES Accelerator (see Table 46)
09C0h
000h-00Fh
LCD_B (see Table 47)
(only CC430F613x and CC430F612x)
0A00h
000h-05Fh
Radio Interface (see Table 48)
0F00h
000h-03Fh
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Table 17. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 18. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 19. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 20. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 21. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 23. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
30
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Table 24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 26. Port Mapping Control Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping key register
PMAPKEYID
00h
Port mapping control register
PMAPCTL
02h
Table 27. Port Mapping Port P1 Registers (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1.0 mapping register
P1MAP0
00h
Port P1.1 mapping register
P1MAP1
01h
Port P1.2 mapping register
P1MAP2
02h
Port P1.3 mapping register
P1MAP3
03h
Port P1.4 mapping register
P1MAP4
04h
Port P1.5 mapping register
P1MAP5
05h
Port P1.6 mapping register
P1MAP6
06h
Port P1.7 mapping register
P1MAP7
07h
Table 28. Port Mapping Port P2 Registers (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping register
P2MAP0
00h
Port P2.1 mapping register
P2MAP1
01h
Port P2.2 mapping register
P2MAP2
02h
Port P2.3 mapping register
P2MAP3
03h
Port P2.4 mapping register
P2MAP4
04h
Port P2.5 mapping register
P2MAP5
05h
Port P2.6 mapping register
P2MAP6
06h
Port P2.7 mapping register
P2MAP7
07h
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Table 29. Port Mapping Port P3 Registers (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping register
P3MAP0
00h
Port P3.1 mapping register
P3MAP1
01h
Port P3.2 mapping register
P3MAP2
02h
Port P3.3 mapping register
P3MAP3
03h
Port P3.4 mapping register
P3MAP4
04h
Port P3.5 mapping register
P3MAP5
05h
Port P3.6 mapping register
P3MAP6
06h
Port P3.7 mapping register
P3MAP7
07h
Table 30. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 31. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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Table 32. Port P5 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Table 33. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 34. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 4
TA0CCR4
1Ah
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 35. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
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Table 36. Real Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Table 37. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
34
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Table 38. DMA Module Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Ah
Table 39. DMA Channel 0 Registers (Base Address: 0510h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
Table 40. DMA Channel 1 Registers (Base Address: 0520h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
Table 41. DMA Channel 2 Registers (Base Address: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
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Table 42. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
USCI control 0
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Table 43. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB0CTL1
00h
USCI synchronous control 0
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
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Table 44. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Control register 0
ADC12CTL0
00h
Control register 1
ADC12CTL1
02h
Control register 2
ADC12CTL2
04h
Interrupt-flag register
ADC12IFG
0Ah
Interrupt-enable register
ADC12IE
0Ch
Interrupt-vector-word register
ADC12IV
0Eh
ADC memory-control register 0
ADC12MCTL0
10h
ADC memory-control register 1
ADC12MCTL1
11h
ADC memory-control register 2
ADC12MCTL2
12h
ADC memory-control register 3
ADC12MCTL3
13h
ADC memory-control register 4
ADC12MCTL4
14h
ADC memory-control register 5
ADC12MCTL5
15h
ADC memory-control register 6
ADC12MCTL6
16h
ADC memory-control register 7
ADC12MCTL7
17h
ADC memory-control register 8
ADC12MCTL8
18h
ADC memory-control register 9
ADC12MCTL9
19h
ADC memory-control register 10
ADC12MCTL10
1Ah
ADC memory-control register 11
ADC12MCTL11
1Bh
ADC memory-control register 12
ADC12MCTL12
1Ch
ADC memory-control register 13
ADC12MCTL13
1Dh
ADC memory-control register 14
ADC12MCTL14
1Eh
ADC memory-control register 15
ADC12MCTL15
1Fh
Conversion memory 0
ADC12MEM0
20h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 4
ADC12MEM4
28h
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 8
ADC12MEM8
30h
Conversion memory 9
ADC12MEM9
32h
Conversion memory 10
ADC12MEM10
34h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 12
ADC12MEM12
38h
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 15
ADC12MEM15
3Eh
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Table 45. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 46. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
AES accelerator control register 0
REGISTER
AESACTL0
Reserved
OFFSET
00h
02h
AES accelerator status register
AESASTAT
04h
AES accelerator key register
AESAKEY
06h
AES accelerator data in register
AESADIN
008h
AES accelerator data out register
AESADOUT
00Ah
Table 47. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_B control register 0
LCDBCTL0
000h
LCD_B control register 1
LCDBCTL1
002h
LCD_B blinking control register
LCDBBLKCTL
004h
LCD_B memory control register
LCDBMEMCTL
006h
LCD_B voltage control register
LCDBVCTL
008h
LCD_B port control register 0
LCDBPCTL0
00Ah
LCD_B port control register 1
LCDBPCTL1
00Ch
LCD_B charge pump control register
LCDBCTL0
012h
LCD_B interrupt vector word
LCDBIV
01Eh
LCD_B memory 1
LCDM1
020h
LCD_B memory 2
LCDM2
021h
LCD_B memory 14
LCDM14
02Dh
LCD_B blinking memory 1
LCDBM1
040h
LCD_B blinking memory 2
LCDBM2
041h
LCDBM14
04Dh
...
...
LCD_B blinking memory 14
38
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CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 48. Radio Interface Registers (Base Address: 0F00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Radio interface control register 0
RF1AIFCTL0
00h
Radio interface control register 1
RF1AIFCTL1
02h
Radio interface error flag register
RF1AIFERR
06h
Radio interface error vector word
RF1AIFERRV
0Ch
Radio interface interrupt vector word
RF1AIFIV
0Eh
Radio instruction word register
RF1AINSTRW
10h
Radio instruction word register, 1-byte auto-read
RF1AINSTR1W
12h
Radio instruction word register, 2-byte auto-read
RF1AINSTR2W
14h
Radio data in register
RF1ADINW
16h
Radio status word register
RF1ASTATW
20h
Radio status word register, 1-byte auto-read
RF1ASTAT1W
22h
Radio status word register, 2-byte auto-read
RF1AISTAT2W
24h
Radio data out register
RF1ADOUTW
28h
Radio data out register, 1-byte auto-read
RF1ADOUT1W
2Ah
Radio data out register, 2-byte auto-read
RF1ADOUT2W
2Ch
Radio core signal input register
RF1AIN
30h
Radio core interrupt flag register
RF1AIFG
32h
Radio core interrupt edge select register
RF1AIES
34h
Radio core interrupt enable register
RF1AIE
36h
Radio core interrupt vector word
RF1AIV
38h
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
–0.3 V to 4.1 V
–0.3 V to (VCC + 0.3 V),
4.1 V Max
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS) (2)
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS (2)
–0.3 V to 2.0 V
Input RF level at pins RF_P and RF_N
10 dBm
Diode current at any device terminal
±2 mA
Storage temperature range (3), Tstg
–55°C to 150°C
Maximum junction temperature, TJ
95°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
θJA
Junction-to-ambient thermal resistance, still air
Low-K board
48 QFN (RGZ)
98°C/W
High-K board
48 QFN (RGZ)
28°C/W
Low-K board
64 QFN (RGC)
83°C/W
High-K board
64 QFN (RGC)
26°C/W
Thermal Packaging Characteristics CC430F61xx
θJA
Junction-to-ambient thermal resistance, still air
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX
Supply voltage range applied at all DVCC and AVCC
pins (1) during program execution and flash programming
with PMM default settings, Radio is not operational with
PMMCOREVx = 0 or 1 (2) (3)
PMMCOREVx = 0
(default after POR)
1.8
3.6
PMMCOREVx = 1
2.0
3.6
Supply voltage range applied at all DVCC and AVCC
pins (1) during program execution, flash programming, and
radio operation with PMM default settings (2) (3)
PMMCOREVx = 2
2.2
3.6
VCC
PMMCOREVx = 3
2.4
3.6
VCC
Supply voltage range applied at all DVCC and AVCC
pins (1) during program execution, flash programming and
radio operation with PMMCOREVx = 2, high-side SVS
level lowered (SVSHRVLx = SVSHRRRLx = 1) or highside SVS disabled (SVSHE = 0) (2) (3) (4)
PMMCOREVx = 2,
SVSHRVLx = SVSHRRRLx = 1
or SVSHE = 0
2.0
3.6
VSS
Supply voltage applied at the exposed die attach VSS and
AVSS pin
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
CVCORE
Recommended capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of capacitor at DVCC to capacitor at
VCORE
VCC
(1)
(2)
(3)
(4)
40
UNIT
V
0
470
V
V
V
°C
°C
nF
10
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation, but the core voltage
will still stay within its limits and is still supervised by the low-side SVS ensuring reliable operation.
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CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
fSYSTEM
Processor (MCLK) frequency (5) (see Figure 2)
0
8
PMMCOREVx = 1
0
12
PMMCOREVx = 2
0
16
0
20
Internal power dissipation
PIO
I/O power dissipation of I/O pins powered by DVCC
PMAX
Maximum allowed power dissipation, PMAX > PIO + PINT
(5)
MAX
PMMCOREVx = 0
(default condition)
PMMCOREVx = 3
PINT
NOM
UNIT
MHz
VCC × I(DVCC)
W
(VCC - VIOH) × IIOH +
VIOL × IIOL
W
(TJ - TA) / θJA
W
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
System Frequency - MHz
20
3
16
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 2. Maximum System Frequency
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
(4)
(5)
Flash
RAM
(4)
(5)
EXECUTION
MEMORY
Flash
RAM
VCC
PMMCOREVx
3.0 V
3.0 V
1 MHz
8 MHz
12 MHz
TYP
MAX
1.55
2.30
2.65
1.75
16 MHz
TYP
MAX
TYP
MAX
0
0.23
0.26
1.35
1.60
TYP
MAX
1
0.25
0.28
2
0.27
0.30
2.60
3.45
3.90
3
0.28
0.32
1.85
0
0.18
0.20
0.95
2.75
3.65
1
0.20
0.22
1.10
1.60
2
0.21
0.24
1.20
1.80
2.40
3
0.22
0.25
1.30
1.90
2.50
20 MHz
TYP
UNIT
MAX
mA
4.55
5.10
1.10
1.85
mA
2.70
3.10
3.60
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3.0 V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0 V.
Typical Characteristics - Active Mode Supply Currents
Active Mode Supply Current
vs
MCLK Frequency
IAM - Active Mode Supply Current - mA
5
V CC = 3.0 V
PMMVCOREx=3
4
3
PMMVCOREx=2
2
PMMVCOREx=1
1
PMMVCOREx=0
0
0
5
10
15
20
MCLK Frequency - MHz
Figure 3.
42
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CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
ILPM3,XT1LF
ILPM3,VLO
ILPM4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
Low-power mode 4 (8)
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
UNIT
MAX
2.2 V
0
80
100
80
100
80
100
80
100
3.0 V
3
90
110
90
110
90
110
90
110
2.2 V
0
6.5
11
6.5
11
6.5
11
6.5
11
3.0 V
3
7.5
12
7.5
12
7.5
12
7.5
12
0
1.8
2.0
2.6
3.0
4.0
4.4
5.9
1
1.9
2.1
3.2
4.8
2
2.0
2.2
3.4
5.1
3
2.0
2.2
2.9
3.5
4.8
5.3
7.4
0
0.9
1.1
2.3
2.1
3.7
3.5
5.6
1
1.0
1.2
2.3
3.9
2
1.1
1.3
2.5
4.2
3
1.1
1.3
2.6
2.6
4.5
4.4
7.1
0
0.8
1.0
2.2
2.0
3.6
3.4
5.5
1
0.9
1.1
2.2
3.8
2
1.0
1.2
2.4
4.1
3
1.0
1.2
3.0 V
3.0 V
(4)
25°C
3.0 V
2.5
2.5
4.4
4.3
µA
µA
µA
µA
µA
7.0
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Typical Characteristics - Low-Power Mode Supply Currents
LPM3 Supply Current
vs
Temperature
LPM4 Supply Current
vs
Temperature
5
5
V DD = 3.0 V
ILPM4 - LPM4 Supply Current - uA
ILPM3,XT1LF - LPM3 Supply Current - uA
V CC = 3.0 V
4
3
PMMCOREVx = 3
2
PMMCOREVx = 0
1
4
3
2
PMMCOREVx = 3
1
PMMCOREVx = 0
0
-40
-20
0
20
40
60
TA - Free-Air Tem perature - °C
Figure 4.
44
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80
0
-40
-20
0
20
40
60
80
TA - Free-Air Tem perature - °C
Figure 5.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Low-Power Mode with LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM3
LCD,
ext. bias
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, external
biasing (3) (4)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (5)
3.0 V
3.0 V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
(6)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (6)
3.0 V
MAX
25°C
TYP
60°C
MAX
TYP
MAX
85°C
TYP
0
2.2
2.4
3.5
4.9
1
2.3
2.5
3.7
5.3
2
2.4
2.6
3.9
5.6
3
2.4
2.6
4.0
5.8
0
3.1
3.3
4.3
5.8
1
3.2
3.4
4.5
6.2
2
3.3
3.5
4.7
6.5
3
3.3
3.5
4.8
6.7
0
4.0
1
4.1
2
4.2
0
4.2
1
4.3
2
4.5
3
4.5
4.0
4.3
UNIT
MAX
µA
7.4
µA
8.9
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD= 3 V typ.), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
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Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
Ilkg(Px.y)
High-impedance leakage current
t(int)
External interrupt timing (External trigger pulse
width to set interrupt flag) (3)
(1)
(2)
(3)
46
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
1.8 V, 3 V
Ports with interrupt capability
(see block diagram and
terminal function
descriptions).
1.8 V, 3 V
20
V
V
V
50
kΩ
±50
nA
5
(1) (2)
UNIT
pF
ns
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
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CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA, PxDS.y = 0
High-level output voltage,
Reduced Drive Strength (1)
VOH
VCC
(2)
I(OHmax) = –3 mA, PxDS.y = 0 (3)
I(OHmax) = –2 mA, PxDS.y = 0 (2)
I(OHmax) = –6 mA, PxDS.y = 0 (3)
I(OLmax) = 1 mA, PxDS.y = 0
Low-level output voltage,
Reduced Drive Strength (1)
VOL
I(OLmax) = 3 mA, PxDS.y = 0 (3)
I(OLmax) = 2 mA, PxDS.y = 0 (2)
I(OHmax) = –3 mA, PxDS.y = 1 (2)
High-level output voltage,
Full Drive Strength
I(OHmax) = –10 mA, PxDS.y = 1 (3)
I(OHmax) = –5 mA, PxDS.y = 1
I(OLmax) = 3 mA, PxDS.y = 1 (2)
Low-level output voltage,
Full Drive Strength
I(OLmax) = 10 mA, PxDS.y = 1 (3)
I(OLmax) = 5 mA, PxDS.y = 1
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
(3)
(4)
(5)
Clock output frequency
CL = 20 pF, RL
CL = 20 pF (5)
(4) (5)
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS VSS + 0.60
VSS VSS + 0.25
3.0 V
UNIT
V
V
VSS VSS + 0.60
1.8 V
3V
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
V
VSS VSS + 0.25
1.8 V
VSS VSS + 0.60
(2)
I(OLmax) = 15 mA, PxDS.y = 1 (3)
MAX
VSS VSS + 0.25
1.8 V
(2)
I(OHmax) = –15 mA, PxDS.y = 1 (3)
VOL
3.0 V
(2)
I(OLmax) = 6 mA, PxDS.y = 0 (3)
VOH
1.8 V
MIN
VSS VSS + 0.25
3V
V
VSS VSS + 0.60
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 2
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 2
25
MHz
MHz
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
8
V CC = 3.0 V
P4.3
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
25
TA = 25°C
20
TA = 85°C
15
10
5
0
V CC = 1.8 V
V DD = 5.5 V
P4.3
7
6
TA = 85°C
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
0
V OL - Low -Level Output Voltage - V
0.5
1
1.5
2
V OL - Low -Level Output Voltage - V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
V CC = 3.0 V
V CC = 3.0 V
P4.3
IOH - Typical High-Level Output Current - mA
IOH - Typical High-Level Output Current - mA
TA = 25°C
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-25
V CC = 1.8 V
V DD = 5.5 V
P4.3
-1
-2
-3
-4
-5
TA = 85°C
-6
TA = 25°C
-7
-8
0
0.5
1
1.5
2
2.5
3
V OH - High-Level Output Voltage - V
3.5
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 8.
Figure 9.
Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
48
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TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
V CC = 3.0 V
P4.3
TA = 25°C
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
60
50
TA = 85°C
40
30
20
10
0
V CC = 1.8 V
V DD = 5.5 V
P4.3
TA = 25°C
20
TA = 85°C
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
0
V OL - Low -Level Output Voltage - V
0.5
1
1.5
2
V OL - Low -Level Output Voltage - V
Figure 10.
Figure 11.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
V CC = 3.0 V
V CC = 3.0 V
P4.3
IOH - Typical High-Level Output Current - mA
IOH - Typical High-Level Output Current - mA
CC430F613x
CC430F612x
CC430F513x
-10
-20
-30
-40
TA = 85°C
-50
TA = 25°C
-60
V CC = 1.8 V
V DD = 5.5 V
P4.3
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-25
0
0.5
1
1.5
2
2.5
3
V OH - High-Level Output Voltage - V
Figure 12.
Copyright © 2009–2013, Texas Instruments Incorporated
3.5
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 13.
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CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
0.170
32768
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
OALF
3.0 V
0.290
XT1 oscillator crystal frequency,
LF mode
(3)
10
CL,eff
fFault,LF
tSTART,LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
50
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
UNIT
300
µA
Hz
50
kHz
kΩ
XTS = 0, XCAPx = 0 (6)
Integrated effective load
capacitance, LF mode (5)
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
2
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
pF
Duty cycle, LF mode
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
30
70
%
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
10
10000
Hz
Startup time, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
kHz
%/°C
4
40
UNIT
%/V
50
60
TYP
MAX
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
3
fREFO
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
±3.5
3V
±1.5
REFO absolute tolerance calibrated
TA = 25°C
UNIT
µA
Hz
%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO startup time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
40
50
60
25
%
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31) (1)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
(1)
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0) (1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
(1)
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31) (1)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
(1)
40
50
60
%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 14. Typical DCO frequency
52
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse duration required at
RST/NMI pin to accept a
reset
MIN
0.80
TYP
1.30
60
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active
mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
VCORE2(AM)
Core voltage, active
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.80
V
VCORE1(AM)
Core voltage, active
mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.60
V
VCORE0(AM)
Core voltage, active
mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.40
V
VCORE3(LPM)
Core voltage, low-current
2.4 V ≤ DVCC ≤ 3.6 V
mode, PMMCOREV = 3
1.94
V
VCORE2(LPM)
Core voltage, low-current
2.2 V ≤ DVCC ≤ 3.6 V
mode, PMMCOREV = 2
1.84
V
VCORE1(LPM)
Core voltage, low-current
2.0 V ≤ DVCC ≤ 3.6 V
mode, PMMCOREV = 1
1.64
V
VCORE0(LPM)
Core voltage, low-current
1.8 V ≤ DVCC ≤ 3.6 V
mode, PMMCOREV = 0
1.44
V
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CC430F612x
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SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
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PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
tpd(SVSH)
t(SVSH)
54
SVSH off voltage level (1)
SVSH propagation delay
SVSH on or off delay time
dVDVCC/dt
(1)
SVSH on voltage level (1)
DVCC rise time
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.53
1.60
1.67
SVSHE = 1, SVSHRVL = 1
1.73
1.80
1.87
SVSHE = 1, SVSHRVL = 2
1.93
2.00
2.07
SVSHE = 1, SVSHRVL = 3
2.03
2.10
2.17
SVSHE = 1, SVSMHRRL = 0
1.60
1.70
1.80
SVSHE = 1, SVSMHRRL = 1
1.80
1.90
2.00
SVSHE = 1, SVSMHRRL = 2
2.00
2.10
2.20
SVSHE = 1, SVSMHRRL = 3
2.10
2.20
2.30
SVSHE = 1, SVSMHRRL = 4
2.25
2.35
2.50
SVSHE = 1, SVSMHRRL = 5
2.52
2.65
2.78
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
100
µs
0
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide (SLAU259) on recommended settings and usage.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level
tpd(SVMH)
t(SVMH)
(1)
SVMH propagation delay
SVMH on or off delay time
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.60
1.70
1.80
SVMHE = 1, SVSMHRRL = 1
1.80
1.90
2.00
SVMHE = 1, SVSMHRRL = 2
2.00
2.10
2.20
SVMHE = 1, SVSMHRRL = 3
2.10
2.20
2.30
SVMHE = 1, SVSMHRRL = 4
2.25
2.35
2.50
SVMHE = 1, SVSMHRRL = 5
2.52
2.65
2.78
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
UNIT
nA
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
MAX
0
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
(1)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
µs
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
100
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide (SLAU259) on recommended settings and usage.
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PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
t(SVSL)
SVSL propagation delay
SVSL on or off delay time
MAX
UNIT
0
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
µs
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
100
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
t(SVML)
SVML propagation delay
SVML on or off delay time
MAX
UNIT
0
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
µs
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
12.5
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
100
µs
Wake-Up From Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tWAKE-UPFAST
tWAKE-UPSLOW
tWAKE-UPRESET
(1)
(2)
(3)
56
Wake-up time from
LPM2, LPM3, or LPM4
to active mode (1)
TEST CONDITIONS
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
MIN
5
fMCLK < 4.0 MHz
6
Wake-up time from
PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3),
LPM2, LPM3 or LPM4 to
SVSLFP = 0
active mode (2)
Wake-up time from RST
or BOR event to active
mode (3)
TYP MAX UNIT
fMCLK ≥ 4.0 MHz
µs
150
165
µs
2
3
ms
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family
User's Guide (SLAU259).
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family User's Guide (SLAU259).
This value represents the time from the wakeup event to the reset vector execution.
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK,
External: TACLK,
Duty cycle = 50% ± 10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V, 3 V
Copyright © 2009–2013, Texas Instruments Incorporated
MIN
TYP
MAX
UNIT
25
MHz
20
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USCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
MAX
UNIT
fSYSTEM
MHz
1
MHz
MAX
UNIT
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
UART receive deglitch time (1)
tτ
(1)
TEST CONDITIONS
VCC
MIN
2.2 V
50
TYP
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
fUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
USCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 15 and Figure 16)
PARAMETER
TEST CONDITIONS
PMMCOR
EVx
0
tSU,MI
SOMI input data setup time
3
0
tHD,MI
SOMI input data hold time
3
0
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
3
0
tHD,MO
SIMO output data hold time
(3)
CL = 20 pF
3
(1)
(2)
(3)
58
VCC
MIN
1.8 V
55
3.0 V
38
2.4 V
30
3.0 V
25
1.8 V
0
3.0 V
0
2.4 V
0
3.0 V
0
TYP
MAX UNIT
ns
ns
ns
ns
1.8 V
20
3.0 V
18
2.4 V
16
3.0 V
15
1.8 V
-10
3.0 V
-8
2.4 V
-10
3.0 V
-8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 15. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 16. SPI Master Mode, CKPH = 1
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 17 and Figure 18)
PARAMETER
TEST CONDITIONS
PMMCOR
EVx
0
tSTE,LEAD
STE lead time, STE low to clock
3
0
tSTE,LAG
STE lag time, Last clock to STE
high
3
0
tSTE,ACC
STE access time, STE low to
SOMI data out
3
0
STE disable time, STE high to
SOMI high impedance
tSTE,DIS
3
0
tSU,SI
SIMO input data setup time
3
0
tHD,SI
SIMO input data hold time
3
0
tVALID,SO
SOMI output data valid time
(2)
UCLK edge to SOMI valid,
CL = 20 pF
3
0
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
3
(1)
(2)
(3)
60
VCC
MIN
1.8 V
11
3.0 V
8
2.4 V
7
3.0 V
6
1.8 V
3
3.0 V
3
2.4 V
3
3.0 V
3
TYP
MAX
ns
ns
1.8 V
66
3.0 V
50
2.4 V
36
3.0 V
30
1.8 V
30
3.0 V
23
2.4 V
16
3.0 V
UNIT
ns
ns
13
1.8 V
5
3.0 V
5
2.4 V
2
3.0 V
2
1.8 V
5
3.0 V
5
2.4 V
5
3.0 V
5
ns
ns
ns
ns
1.8 V
76
3.0 V
60
2.4 V
44
3.0 V
40
1.8 V
18
3.0 V
12
2.4 V
10
3.0 V
8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 17. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 18. SPI Slave Mode, CKPH = 1
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
tSP
Pulse width of spikes suppressed by input filter
fSCL > 100 kHz
tSU,STA
tHD,STA
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 19. I2C Mode Timing
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LCD_B Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC,LCD_B,CP en,3.6
Supply voltage range,
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
charge pump enabled,
(charge pump enabled, VLCD≤ 3.6 V)
VLCD ≤ 3.6 V
2.2
3.6
V
VCC,LCD_B,CP en,3.3
Supply voltage range,
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
charge pump enabled,
(charge pump enabled, VLCD≤ 3.3 V)
VLCD≤ 3.3 V
2.0
3.6
V
VCC,LCD_B,int. bias
Supply voltage range,
internal biasing,
LCDCPEN = 0, VLCDEXT=0
charge pump disabled
2.4
3.6
V
VCC,LCD_B,ext.
Supply voltage range,
external biasing,
LCDCPEN = 0, VLCDEXT=0
charge pump disabled
2.4
3.6
V
VCC,LCD_B,VLCDEXT
Supply voltage range,
external LCD voltage,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT=1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage
at LCDCAP/R33,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT=1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP
LCDCPEN = 1, VLCDx > 0000 (charge pump
when charge pump
enabled)
enabled
10
µF
fFrame
LCD frame frequency
range
100
Hz
fACLK,in
ACLK input frequency
range
40
kHz
CPanel
Panel capacitance
100-Hz frame frequency
10000
pF
VR33
Analog input voltage
at R33
LCDCPEN = 0, VLCDEXT=1
VCC+0.2
V
VR23,1/3bias
Analog input voltage
at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03 +
VR13 2/3*(VR33
-VR03)
VR33
V
VR13,1/3bias
Analog input voltage
at R13 with 1/3
biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03 +
VR03 1/3*(VR33
-VR03)
VR23
V
VR13,1/2bias
Analog input voltage
at R13 with 1/2
biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03 +
VR03 1/2*(VR33
-VR03)
VR33
V
VR03
Analog input voltage
at R03
R0EXT=1
VSS
VLCD-VR03
Voltage difference
between VLCD and
R03
LCDCPEN = 0, R0EXT=1
2.4
VLCDREF/R13
External LCD
reference voltage
applied at
LCDREF/R13
VLCDREFx = 01
0.8
bias
fLCD = 2 × mux × fFRAME with mux= 1 (static),
2, 3, 4
4.7
0
30
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4.7
32
2.4
V
1.2
VCC+0.2
V
1.5
V
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LCD_B Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VLCDx = 0000, VLCDEXT=0
2.4 V to
3.6 V
VCC
V
LCDCPEN = 1, VLCDx = 0001
2.0 V to
3.6 V
2.54
V
LCDCPEN = 1, VLCDx = 0010
2.0 V to
3.6 V
2.60
V
LCDCPEN = 1, VLCDx = 0011
2.0 V to
3.6 V
2.66
V
LCDCPEN = 1, VLCDx = 0100
2.0 V to
3.6 V
2.72
V
LCDCPEN = 1, VLCDx = 0101
2.0 V to
3.6 V
2.78
V
LCDCPEN = 1, VLCDx = 0110
2.0 V to
3.6 V
2.84
V
LCDCPEN = 1, VLCDx = 0111
2.0 V to
3.6 V
2.90
V
LCDCPEN = 1, VLCDx = 1000
2.0 V to
3.6 V
2.96
V
LCDCPEN = 1, VLCDx = 1001
2.0 V to
3.6 V
3.02
V
LCDCPEN = 1, VLCDx = 1010
2.0 V to
3.6 V
3.08
V
LCDCPEN = 1, VLCDx = 1011
2.0 V to
3.6 V
3.14
V
LCDCPEN = 1, VLCDx = 1100
2.0 V to
3.6 V
3.20
V
LCDCPEN = 1, VLCDx = 1101
2.2 V to
3.6 V
3.26
V
LCDCPEN = 1, VLCDx = 1110
2.2 V to
3.6 V
3.32
V
LCDCPEN = 1, VLCDx = 1111
2.2 V to
3.6 V
3.38
3.6
V
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111
2.2 V
200
tLCD,CP,on
Time to charge CLCD when
discharge
CLCDCAP = 4.7µF, LCDCPEN =
0→1, VLCDx = 1111
2.2 V
100
ICP,Load
Max. charge pump load current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
64
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µA
500
50
ms
µA
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12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage,
Full performance
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 analog input pins Ax
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at one
time
RI
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
(1)
(2)
(3)
VCC
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
AVCC
V
2.2 V
125
155
3V
150
220
2.2 V
20
25
pF
200
1900
Ω
10
µA
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference and REF, Built-In Reference.
The internal reference supply current is not included in current consumption parameter IADC12_A.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AVCC as reference. (1)
fADC12CLK
ADC conversion clock
For specified performance of ADC12 linearity
parameters using the internal reference. (2)
2.2 V, 3 V
For specified performance of ADC12 linearity
parameters using the internal reference. (3)
fADC12OSC
Internal ADC12
oscillator (4)
tCONVERT
Conversion time
tSample
(1)
(2)
(3)
(4)
(5)
(6)
Sampling time
MIN
TYP
MAX
0.45
4.8
5.0
0.45
2.4
4.0
0.45
2.4
2.7
4.8
5.4
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
4.2
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V, 3 V
2.4
MHz
MHz
3.1
µs
External fADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] × CI (6)
UNIT
(5)
2.2 V, 3 V
1000
ns
REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
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12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference
Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
EI
Integral linearity error (1)
ED
Differential linearity error (1)
EO
Offset error (3)
EG
Gain error (3)
ET
(1)
(2)
(3)
Total unadjusted error
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V (2)
1.6 V < dVREF (2)
VCC
MIN
TYP
MAX
±2.0
2.2 V, 3 V
±1.7
(2)
2.2 V, 3 V
dVREF ≤ 2.2 V (2)
2.2 V, 3 V
±1.0
±2.0
dVREF > 2.2 V (2)
2.2 V, 3 V
±1.0
±2.0
(2)
2.2 V, 3 V
±1.0
±2.0
dVREF ≤ 2.2 V (2)
2.2 V, 3 V
±1.4
±3.5
dVREF > 2.2 V (2)
2.2 V, 3 V
±1.4
±3.5
±1.0
UNIT
LSB
LSB
LSB
LSB
LSB
Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-, VR+ < AVCC, VR-> AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the CC430 Family User's Guide
(SLAU259).
Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
EI
Integral linearity
error (2)
ED
Differential
linearity error (2)
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
EO
Offset error (3)
EG
Gain error (3)
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
ET
Total unadjusted ADC12SR = 0, REFOUT = 1
error
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 4.0 MHz
(1)
(2)
(3)
(4)
66
fADC12CLK ≤ 2.7 MHz
VCC
MIN
TYP
±1.7
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MAX
±2.5
-1.0
+2.0
-1.0
+1.5
-1.0
+2.5
±1.0
±2.0
±1.0
±2.0
±1.0
±2.0
UNIT
LSB
LSB
LSB
LSB
±1.5% (4) VREF
±1.4
±3.5
±1.5%
(4)
LSB
VREF
The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.
The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.
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CC430F513x
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12-Bit ADC, Temperature Sensor and Built-In VMID (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
VSENSOR
See
(2) (3)
TCSENSOR
See
(3)
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh
Sample time required if
channel 11 is selected (5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
ADC12ON = 1, INCH = 0Ah
VMID
tVMID(sample)
(1)
(2)
(3)
(4)
(5)
VCC
MIN
TYP
2.2 V
680
3V
680
2.2 V
2.25
3V
2.25
2.2 V
30
3V
30
MAX
UNIT
mV
mV/°C
µs
0.48
0.5
0.52 VAVCC
2.2 V
1.06
1.1
1.14
3V
1.44
1.5
1.56
2.2 V, 3 V
1000
V
ns
The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Typical Temperature Sensor Voltage - mV
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature - ˚C
Figure 20. Typical Temperature Sensor Voltage
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REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VeREF+
Positive external reference voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
AVCC
V
VREF–/VeREF–
Negative external reference voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference voltage
input
VeREF+ > VREF–/VeREF–
(4)
1.4
AVCC
V
±26
µA
±1
µA
IVeREF+
IVREF–/VeREF–
CVREF+/(1)
(2)
(3)
(4)
(5)
68
Static input current
Capacitance at VREF+/-terminal, external
reference (5)
1.4 V ≤ VeREF+ ≤ VAVCC ,
VeREF– = 0 V
fADC12CLK = 5
MHz,ADC12SHTx = 1h,
Conversion rate 200ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC ,
VeREF– = 0 V
fADC12CLK = 5
MHz,ADC12SHTx = 8h,
Conversion rate 20ksps
2.2 V, 3 V
±8.5
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the CC430 Family User's Guide (SLAU259).
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CC430F612x
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REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VREF+
AVCC(min)
Positive built-in reference
voltage output
AVCC minimum voltage,
Positive built-in reference
active
TEST CONDITIONS
VCC
2.41
±1.5%
REFVSEL = 1 for 2.0 V,
REFON = REFOUT = 1,
IVREF+= 0 A
3V
1.93
±1.5%
REFVSEL = 0 for 1.5 V,
REFON = REFOUT = 1,
IVREF+= 0 A
2.2 V, 3 V
1.45
±1.5%
REFVSEL = 0 for 1.5 V, reduced performance
1.8
REFVSEL = 0 for 1.5 V
2.2
REFVSEL = 1 for 2.0 V
2.3
2.8
100
140
µA
3V
0.9
1.5
mA
REFVSEL = 0, 1, or 2,
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC (min) for each reference level,
REFON = REFOUT = 1
CVREF+
Capacitance at VREF+
terminals, internal reference
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference (5)
IVREF+ = 0 A,
REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
PSRR_DC
Power supply rejection ratio
(DC)
PSRR_AC
Power supply rejection ratio
(AC)
(4)
(5)
(6)
V
REFON = 1, REFOUT = 1, REFBURST = 0
Load-current regulation,
VREF+ terminal (4)
(3)
V
3V
IL(VREF+)
(2)
UNIT
REFON = 1, REFOUT = 0, REFBURST = 0
Operating supply current into
AVCC terminal (2) (3)
(1)
MAX
3V
IREF+
Settling time of reference
voltage (6)
TYP
REFVSEL = 2 for 2.5 V,
REFON = REFOUT = 1,
IVREF+= 0 A
REFVSEL = 2 for 2.5 V
tSETTLE
MIN
2500 µV/mA
100
pF
30
50
ppm/
°C
AVCC = AVCC (min) - AVCC(max),
TA = 25 °C, REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
120
300
µV/V
AVCC = AVCC (min) - AVCC(max)
TA = 25 °C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = 0, 1, or 2,
REFON = 1, REFOUT = 0 or 1
6.4
AVCC = AVCC (min) - AVCC(max),
REFVSEL = 0, 1, or 2,
REFOUT = 0, REFON = 0 → 1
75
AVCC = AVCC (min) - AVCC(max),
CVREF = CVREF(max),
REFVSEL = 0, 1, or 2,
REFOUT = 1, REFON = 0 → 1
20
mV/V
µs
75
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. REFOUT = 0 represents
the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON
=1 and REFOUT = 0.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
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Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
MAX
1.8
3.6
1.8 V
IAVCC_COMP
Comparator operating supply
current into AVCC, Excludes
reference resistor ladder
IAVCC_REF
Quiescent current of local
reference voltage amplifier into
AVCC
VIC
Common mode input range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
2.2 V
30
50
3.0 V
40
65
CBPWRMD = 01
2.2 V, 3 V
10
30
CBPWRMD = 10
2.2 V, 3 V
0.1
0.5
CBREFACC = 1, CBREFLx = 01
22
0
VCC-1
CBPWRMD = 00
CBPWRMD = 01, 10
ON - switch closed
3
µA
µA
V
±20
mV
±10
mV
4
kΩ
5
OFF - switch opened
V
40
pF
30
MΩ
CBPWRMD = 00, CBF = 0
450
ns
Propagation delay, response time CBPWRMD = 01, CBF = 0
600
ns
CBPWRMD = 10, CBF = 0
50
µs
Propagation delay with filter
active
tPD,filter
CBPWRMD = 00
UNIT
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
0.6
1.0
1.8
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
1.8
3.4
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
3.4
6.5
µs
tEN_CMP
Comparator enable time, settling
time
CBON = 0 to CBON = 1,
CBPWRMD = 00, 01, 10
1
2
µs
tEN_REF
Resistor reference enable time
CBON = 0 to CBON = 1
0.3
1.5
µs
Reference voltage for a given tap
VIN = reference into resistor ladder,
n = 0 to 31
VCB_REF
70
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V
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CC430F612x
CC430F513x
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
2
6.5
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank
erase
2
6.5
mA
16
ms
tCPT
Cumulative program time
(1)
4
Program and erase endurance
10
10
cycles
tRetention
Data retention duration
tWord
Word or byte program time (2)
64
85
µs
tBlock,
0
Block program time for first byte or word (2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word (2)
37
49
µs
55
73
µs
23
32
ms
0
1
MHz
tBlock,
N
Block program time for last byte or word
TJ = 25°C
5
(2)
tErase
Erase time for segment erase, mass erase, and bank erase when
available (2)
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1)
(2)
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3 V
1
µs
100
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency - 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
15
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V, 3 V
45
80
kΩ
60
Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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RF1A CC1101-Based Radio Parameters
Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
VCC
Supply voltage range during radio operation
PMMCOREVx
Core voltage range, PMMCOREVx setting during radio operation
3.6
3
300
348
(1)
464
779
928
2-FSK
0.6
500
2-GFSK, OOK, and ASK
0.6
250 kBaud
389
(Shaped) MSK (also known as differential offset QPSK)
(2)
26
V
MHz
500
26
26
Total tolerance including initial tolerance, crystal loading, aging and
temperature dependency. (3)
RF crystal load capacitance
27
±40
10
MHz
ppm
13
RF crystal effective series
resistance
(1)
(2)
(3)
UNIT
2
RF crystal frequency
RF crystal tolerance
MAX
2.0
RF frequency range
Data rate
TYP
20
pF
100
Ω
If using a 27-MHz crystal, the lower frequency limit for this band is 392 MHz.
If using optional Manchester encoding, the data rate in kbps is half the baud rate.
The acceptable crystal tolerance depends on frequency band, channel bandwidth, and spacing. Also see design note DN005 -- CC11xx
Sensitivity versus Frequency Offset and Crystal Accuracy (SWRA122).
RF Crystal Oscillator, XT2
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
Start-up time (2)
Duty cycle
(1)
(2)
45
TYP
MAX
UNIT
150
810
µs
50
55
%
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
The start-up time depends to a very large degree on the used crystal.
Current Consumption, Reduced-Power Modes
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
Current
consumption
(1)
(2)
72
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RF crystal oscillator only (for example, SLEEP state with MCSM0.OSC_FORCE_ON =
1)
100
µA
IDLE state (including RF crystal oscillator)
1.7
mA
FSTXON state (only the frequency synthesizer is running) (2)
9.5
mA
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
This current consumption is also representative of other intermediate states when going from IDLE to RX or TX, including the calibration
state.
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Current Consumption, Receive Mode
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
FREQ
(MHz)
DATA
RATE
(kBaud)
(2)
TEST CONDITIONS
1.2
315
38.4
Register settings
optimized for reduced
current
250
433
38.4
Register settings
optimized for reduced
current
1.2
868, 915
38.4
Register settings
optimized for reduced
current (3)
250
(1)
(2)
(3)
17
Input at -40 dBm (well above
sensitivity limit)
16
Input at -100 dBm (close to
sensitivity limit)
17
Input at -40 dBm (well above
sensitivity limit)
16
Input at -100 dBm (close to
sensitivity limit)
18
MAX
UNIT
16.5
Input at -100 dBm (close to
sensitivity limit)
18
Input at -40 dBm (well above
sensitivity limit)
17
Input at -100 dBm (close to
sensitivity limit)
18
Input at -40 dBm (well above
sensitivity limit)
17
Input at -100 dBm (close to
sensitivity limit)
250
TYP
Input at -100 dBm (close to
sensitivity limit)
Input at -40 dBm (well above
sensitivity limit)
1.2
Current
consumption,
RX
MIN
mA
18.5
Input at -40 dBm (well above
sensitivity limit)
17
Input at -100 dBm (close to
sensitivity limit)
16
Input at -40 dBm (well above
sensitivity limit)
15
Input at -100 dBm (close to
sensitivity limit)
16
Input at -40 dBm (well above
sensitivity limit)
15
Input at -100 dBm (close to
sensitivity limit)
16
Input at -40 dBm (well above
sensitivity limit)
15
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See tables "RF Receive" for additional details on current consumption and sensitivity.
For 868 or 915 MHz, see Figure 21 for current consumption with register settings optimized for sensitivity.
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19
19
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
Radio Current [mA]
Radio Current [mA]
TA = 85°C
18
17
16
-100
-80
-60
-40
18
17
16
-100
-20
-80
Input Pow er [dBm ]
-60
-20
Input Pow er [dBm ]
1.2 kBaud GFSK
38.4 kBaud GFSK
19
19
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
Radio Current [mA]
Radio Current [mA]
-40
18
17
16
-100
-80
-60
Input Pow er [dBm ]
250 kBaud GFSK
-40
-20
18
17
16
-100
-80
-60
-40
-20
Input Pow er [dBm ]
500 kBaud MSK
Figure 21. Typical RX Current Consumption Over Temperature and Input Power Level, 868 MHz,
Sensitivity-Optimized Setting
74
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Current Consumption, Transmit Mode
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
(2)
FREQUENCY
[MHz}
315
433
Current consumption, TX
868
915
(1)
(2)
PATABLE
Setting
OUTPUT
POWER (dBm)
0xC0
max.
26
mA
0xC4
+10
25
mA
0x51
0
15
mA
MIN
TYP
MAX
UNIT
0x29
-6
15
mA
0xC0
max.
33
mA
0xC6
+10
29
mA
0x50
0
17
mA
0x2D
-6
17
mA
0xC0
max.
36
mA
0xC3
+10
33
mA
0x8D
0
18
mA
0x2D
-6
18
mA
0xC0
max.
35
mA
0xC3
+10
32
mA
0x8D
0
18
mA
0x2D
-6
18
mA
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See tables "RF Receive" for additional details on current consumption and sensitivity.
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CC430F612x
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Typical TX Current Consumption, 315 MHz
PARAMETER
Current
consumption,
TX
PATABLE
Setting
Output
Power
(dBm)
VCC
2.0 V
3.0 V
3.6 V
TA
25°C
25°C
25°C
0xC0
max.
27.5
26.4
28.1
0xC4
+10
25.1
25.2
25.3
0x51
0
14.4
14.6
14.7
0x29
-6
14.2
14.7
15.0
UNIT
mA
Typical TX Current Consumption, 433 MHz
PARAMETER
Current
consumption,
TX
PATABLE
Setting
Output
Power
(dBm)
VCC
2.0 V
3.0 V
3.6 V
TA
25°C
25°C
25°C
0xC0
0xC6
max.
33.1
33.4
33.8
+10
28.6
28.8
28.8
0x50
0
16.6
16.8
16.9
0x2D
-6
16.8
17.5
17.8
3.0 V
3.6 V
UNIT
mA
Typical TX Current Consumption, 868 MHz
PARAMETER
Current
consumption,
TX
PATABLE
Setting
Output
Power
(dBm)
0xC0
0xC3
VCC
TA
2.0 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
max.
36.7
35.2
34.2
38.5
35.5
34.9
37.1
35.7
34.7
+10
34.0
32.8
32.0
34.2
33.0
32.5
34.3
33.1
32.2
0x8D
0
18.0
17.6
17.5
18.3
17.8
18.1
18.4
18.0
17.7
0x2D
-6
17.1
17.0
17.2
17.8
17.8
18.3
18.2
18.1
18.1
UNIT
mA
Typical TX Current Consumption, 915 MHz
PARAMETER
Current
consumption,
TX
76
PATABLE
Setting
Output
Power
(dBm)
0xC0
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
max.
35.5
33.8
33.2
36.2
34.8
33.6
36.3
35.0
33.8
0xC3
+10
33.2
32.0
31.0
33.4
32.1
31.2
33.5
32.3
31.3
0x8D
0
17.8
17.4
17.1
18.1
17.6
17.3
18.2
17.8
17.5
0x2D
-6
17.0
16.9
16.9
17.7
17.6
17.6
18.1
18.0
18.0
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UNIT
mA
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
RF Receive, Overall
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
Digital channel filter bandwidth
Spurious emissions (3)
(4)
TYP
58
MAX
UNIT
812
kHz
25 MHz to 1 GHz
-68
-57
Above 1 GHz
-66
-47
Serial operation (5)
RX latency
(1)
(2)
(3)
(4)
(5)
MIN
(2)
9
dBm
bit
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal)
Typical radiated spurious emission is -49 dBm measured at the VCO frequency
Maximum figure is the ETSI EN 300 220 limit
Time from start of reception until data is available on the receiver data output pin is equal to 9 bit.
RF Receive, 315 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
PARAMETER
DATA RATE
(kBaud)
0.6
Receiver sensitivity
(1)
(2)
(3)
(4)
TEST CONDITIONS
MIN
14.3kHz deviation, 58kHz digital channel filter bandwidth
TYP
MAX
UNIT
-117
(2)
1.2
5.2kHz deviation, 58kHz digital channel filter bandwidth
38.4
20kHz deviation, 100kHz digital channel filter bandwidth (3)
-111
250
127kHz deviation, 540kHz digital channel filter bandwidth
500
MSK, 812kHz digital channel filter bandwidth (4)
-103
(4)
dBm
-95
-86
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -109dBm.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -102dBm.
MDMCFG2.DEM_DCFILT_OFF=1 can not be used for data rates ≥ 250kBaud.
RF Receive, 433 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
PARAMETER
Receiver sensitivity
DATA RATE
(kBaud)
(4)
TYP
14.3kHz deviation, 58kHz digital channel filter bandwidth
-114
1.2
5.2-kHz deviation, 58-kHz digital channel filter bandwidth (2)
-111
38.4
20-kHz deviation, 100-kHz digital channel filter bandwidth (3)
-104
500
(3)
MIN
0.6
250
(1)
(2)
TEST CONDITIONS
127-kHz deviation, 540-kHz digital channel filter bandwidth
(4)
MSK, 812kHz digital channel filter bandwidth
(4)
MAX
UNIT
dBm
-93
-85
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -109dBm.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -101dBm.
MDMCFG2.DEM_DCFILT_OFF=1 can not be used for data rates ≥ 250kBaud.
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CC430F612x
CC430F513x
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RF Receive, 868 or 915 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.6-kBaud data rate, 2-FSK, 14.3-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity
-115
dBm
1.2-kBaud data rate, 2-FSK, 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
-109
Receiver sensitivity (2)
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT=2,
Gaussian filter with BT = 0.5
Saturation
FIFOTHR.CLOSE_IN_RX=0 (3)
-109
-28
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
100 kHz channel spacing (4)
Image channel rejection
IF frequency 152 kHz, desired channel 3 dB above
the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit (5)
-100-kHz offset
39
+100-kHz offset
39
dBm
dBm
dB
29
dB
±2 MHz offset
-48
dBm
±10 MHz offset
-40
dBm
38.4-kBaud data rate, 2-FSK, 20-kHz deviation, 100-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity (6)
-102
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
-101
Saturation
FIFOTHR.CLOSE_IN_RX=0 (3)
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
200 kHz channel spacing (5)
Image channel rejection
IF frequency 152 kHz, Desired channel 3 dB above the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit (5)
-19
-200-kHz offset
20
+200-kHz offset
25
dBm
dBm
dB
23
dB
±2-MHz offset
-48
dBm
±10-MHz offset
-40
dBm
250-kBaud data rate, 2-FSK, 127-kHz deviation, 540-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity
(7)
-90
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
-90
Saturation
FIFOTHR.CLOSE_IN_RX=0 (3)
-19
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
750-kHz channel spacing (8)
Image channel rejection
IF frequency 304 kHz, Desired channel 3 dB above the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit (8)
-750-kHz offset
24
+750-kHz offset
30
dBm
dBm
dB
18
dB
±2-MHz offset
-53
dBm
±10-MHz offset
-39
dBm
-84
dBm
-2
dB
±2-MHz offset
-53
dBm
±10-MHz offset
-38
dBm
500-kBaud data rate, MSK, 812-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity (7)
Image channel rejection
Blocking
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
78
IF frequency 355 kHz, Desired channel 3 dB above the sensitivity limit
Desired channel 3 dB above the sensitivity limit
(9)
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -107dBm
See design note DN010 Close-in Reception with CC1101 (SWRA147).
See Figure 22 for blocking performance at other offset frequencies.
See Figure 23 for blocking performance at other offset frequencies.
Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -100dBm.
MDMCFG2.DEM_DCFILT_OFF = 1 cannot be used for data rates ≥ 250kBaud.
See Figure 24 for blocking performance at other offset frequencies.
See Figure 25 for blocking performance at other offset frequencies.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
60
80
70
50
60
40
Selectivity [dB]
Blocking [dB]
50
40
30
20
10
30
20
10
0
0
-10
-20
-40
-10
-30
-20
-10
0
10
20
30
-1
40
Offset [MHz]
-0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Offset [MHz]
NOTE: 868.3 MHz, 2-FSK, 5.2-kHz deviation, IF frequency is 152.3 kHz, digital channel filter bandwidth is 58 kHz
Figure 22. Typical Selectivity at 1.2-kBaud Data Rate
80
50
70
40
60
30
Selectivity [dB]
Blocking [dB]
50
40
30
20
10
20
10
0
0
-10
-10
-20
-40
-20
-30
-20
-10
0
10
Offset [MHz]
20
30
40
-1
-0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Offset [MHz]
NOTE: 868 MHz, 2-FSK, 20 kHz deviation, IF frequency is 152.3 kHz, digital channel filter bandwidth is 100 kHz
Figure 23. Typical Selectivity at 38.4-kBaud Data Rate
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50
80
70
40
60
30
Selectivity [dB]
Blocking [dB]
50
40
30
20
10
20
10
0
0
-10
-10
-20
-40
-20
-30
-20
-10
0
10
20
30
-3
40
-2
-1
Offset [MHz]
0
1
2
3
1
2
3
Offset [MHz]
NOTE: 868 MHz, 2-FSK, IF frequency is 304 kHz, digital channel filter bandwidth is 540 kHz
Figure 24. Typical Selectivity at 250-kBaud Data Rate
80
50
70
40
60
30
Selectivity [dB]
Blocking [dB]
50
40
30
20
10
20
10
0
0
-10
-10
-20
-40
-20
-30
-20
-10
0
10
20
30
40
-3
-2
Offset [MHz]
-1
0
Offset [MHz]
NOTE: 868 MHz, 2-FSK, IF frequency is 355 kHz, digital channel filter bandwidth is 812 kHz
Figure 25. Typical Selectivity at 500-kBaud Data Rate
80
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
315MHz
DATA RATE (kBaud)
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
1.2
-112
-112
-110
-112
-111
-109
-112
-111
-108
38.4
-105
-105
-104
-105
-103
-102
-105
-104
-102
250
-95
-95
-92
-94
-95
-92
-95
-94
-91
UNIT
dBm
Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
433MHz
DATA RATE (kBaud)
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
1.2
-111
-110
-108
-111
-111
-108
-111
-110
-107
38.4
-104
-104
-101
-104
-104
-101
-104
-103
-101
250
-93
-94
-91
-93
-93
-90
-93
-93
-90
UNIT
dBm
Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
868MHz
DATA RATE (kBaud)
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
1.2
-109
-109
-107
-109
-109
-106
-109
-108
-106
38.4
-102
-102
-100
-102
-102
-99
-102
-101
-99
250
-90
-90
-88
-89
-90
-87
-89
-90
-87
500
-84
-84
-81
-84
-84
-80
-84
-84
-80
UNIT
dBm
Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
PARAMETER
Sensitivity,
915MHz
DATA RATE (kBaud)
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
1.2
-109
-109
-107
-109
-109
-106
-109
-108
-105
38.4
-102
-102
-100
-102
-102
-99
-103
-102
-99
250
-92
-92
-89
-92
-92
-88
-92
-92
-88
500
-87
-86
-81
-86
-86
-81
-86
-85
-80
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UNIT
dBm
81
CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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RF Transmit
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
PTX = +10 dBm (unless otherwise noted)
PARAMETER
FREQUENCY
(MHz)
TEST CONDITIONS
MIN
315
Differential load
impedance (2)
116 + j41
868, 915
86.5 + j43
433
868
433
Harmonics,
radiated (4) (5) (6)
868
915
315
433
Harmonics, conducted
868
915
315
Delivered to a 50Ω single-ended load via CC430
reference design's RF matching network
Spurious emissions,
conducted, harmonics
not included (8)
868
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
82
+13
+11
Delivered to a 50Ω single-ended load via CC430
reference design's RF matching network
-30
Second harmonic
-56
Third harmonic
-57
Second harmonic
-50
Third harmonic
-52
Second harmonic
-50
Third harmonic
Frequencies below 960 MHz
dBm
Frequencies above 960 MHz
Frequencies below 1 GHz
Frequencies above 1 GHz
Second harmonic
Other harmonics
Second harmonic
Other harmonics
Frequencies below 960 MHz
Frequencies above 960 MHz
Frequencies above 1 GHz
+10 dBm CW
+10 dBm CW
+10 dBm CW
+11 dBm CW (7)
+10 dBm CW
< -48
-45
< -48
-59
-53
< -47
< -58
< -53
< -54
+10 dBm CW
< -54
Frequencies below 1 GHz
< -46
Frequencies above 960 MHz
dBm
< -71
< -63
Frequencies below 960 MHz
dBm
< -38
Frequencies within 47 to 74, 87.5 to
118, 174 to 230, 470 to 862 MHz
Frequencies above 1 GHz
dBm
-54
+10 dBm CW
Frequencies within 47 to 74, 87.5 to
118, 174 to 230, 470 to 862 MHz
915
Ω
+11
Frequencies below 1 GHz
433
UNIT
+12
915
Output power, lowest
setting (3)
MAX
122 + j31
433
315
Output power, highest
setting (3)
TYP
dBm
< -59
< -56
+11 dBm CW
< -49
< -63
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC430 reference designs available
from the TI website.
Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by regulatory limits.
See also application note AN050 Using the CC1101 in the European 868MHz SRD Band (SWRA146) and design note DN013
Programming Output Power on CC1101 (SWRA168), which gives the output power and harmonics when using multi-layer inductors.
The output power is then typically +10 dBm when operating at 868 or 915 MHz.
The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in
attenuating the harmonics.
Measured on EM430F6137RF900 with CW, maximum output power
All harmonics are below -41.2 dBm when operating in the 902 to 928 MHz band.
Requirement is -20 dBc under FCC 15.247
All radiated spurious emissions are within the limits of ETSI. Also see design note DN017 CC11xx 868/915 MHz RF Matching
(SWRA168).
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
RF Transmit (continued)
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PTX = +10 dBm (unless otherwise noted)
PARAMETER
TX latency (9)
(9)
FREQUENCY
(MHz)
TEST CONDITIONS
MIN
Serial operation
TYP
MAX
8
UNIT
bits
Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports
Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
Output Power (dBm)
(1)
PATABLE Setting
315 MHz
433 MHz
868 MHz
915 MHz
-30
0x12
0x05
0x03
0x03
-12
0x33
0x26
0x25
0x25
-6
0x29
0x2D
0x2D
0x2D
0
0x51
0x50
0x8D
0x8D
10
0xC4
0xC4
0xC3
0xC3
Maximum
0xC0
0xC0
0xC0
0xC0
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
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Typical Output Power, 315 MHz (1)
PARAMETER
Output power,
315 MHz
(1)
PATABLE Setting
VCC
TA
2.0 V
-40°C
25°C
3.0 V
85°C
-40°C
25°C
3.6 V
85°C
-40°C
25°C
0xC0 (max)
11.9
11.8
11.8
0xC4 (10 dBm)
10.3
10.3
10.3
0xC6 (default)
85°C
9.3
UNIT
dBm
0x51 (0 dBm)
0.7
0.6
0.7
0x29 (-6 dBm)
-6.8
-5.6
-5.3
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Typical Output Power, 433 MHz (1)
PARAMETER
Output power,
433 MHz
(1)
PATABLE Setting
VCC
TA
2.0 V
-40°C
25°C
3.0 V
85°C
-40°C
25°C
3.6 V
85°C
-40°C
25°C
0xC0 (max)
12.6
12.6
12.6
0xC4 (10 dBm)
10.3
10.2
10.2
0xC6 (default)
85°C
10.0
UNIT
dBm
0x50 (0 dBm)
0.3
0.3
0.3
0x2D (-6 dBm)
-6.4
-5.4
-5.1
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Typical Output Power, 868 MHz (1)
PARAMETER
Output power,
868 MHz
(1)
PATABLE Setting
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
0xC0 (max)
11.9
11.2
10.5
11.9
11.2
10.5
11.9
11.2
10.5
0xC3 (10 dBm)
10.8
10.1
9.4
10.8
10.1
9.4
10.7
10.1
9.4
0xC6 (default)
8.8
UNIT
dBm
0x8D (0 dBm)
1.0
0.3
-0.3
1.1
0.3
-0.3
1.1
0.3
-0.3
0x2D (-6 dBm)
-6.5
-6.8
-7.3
-5.3
-5.8
-6.3
-4.9
-5.4
-6.0
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
Typical Output Power, 915 MHz (1)
PARAMETER
Output power,
915 MHz
(1)
84
PATABLE Setting
VCC
TA
2.0 V
3.0 V
3.6 V
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
0xC0 (max)
12.2
11.4
10.6
12.1
11.4
10.7
12.1
11.4
10.7
0xC3 (10 dBm)
11.0
10.3
9.5
11.0
10.3
9.5
11.0
10.3
9.6
0xC6 (default)
8.8
UNIT
dBm
0x8D (0 dBm)
1.9
1.0
0.3
1.9
1.0
0.3
1.9
1.1
0.3
0x2D (-6 dBm)
-5.5
-6.0
-6.5
-4.3
-4.8
-5.5
-3.9
-4.4
-5.1
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Frequency Synthesizer Characteristics
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
MIN figures are given using a 27MHz crystal. TYP and MAX figures are given using a 26MHz crystal.
PARAMETER
Programmed frequency resolution (2)
Synthesizer frequency tolerance
TEST CONDITIONS
26- to 27-MHz crystal
MIN
TYP
MAX
UNIT
397
fXOSC/216
412
Hz
(3)
±40
50-kHz offset from carrier
–95
100-kHz offset from carrier
–94
200-kHz offset from carrier
–94
500-kHz offset from carrier
RF carrier phase noise
–98
1-MHz offset from carrier
–107
2-MHz offset from carrier
–112
5-MHz offset from carrier
–118
10-MHz offset from carrier
PLL turn-on and hop time (4)
Crystal oscillator running
88.4
88.4
µs
9.6
9.6
µs
21.5
21.5
µs
721
µs
9.3
PLL TX to RX settling time (6)
20.7
PLL calibration time (7)
694
721
(1)
(2)
(3)
(4)
(5)
(6)
(7)
dBc/Hz
–129
85.1
(5)
PLL RX to TX settling time
ppm
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
The resolution (in Hz) is equal for all frequency bands.
Depends on crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth and
spacing.
Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration.
Settling time for the 1-IF frequency step from RX to TX
Settling time for the 1-IF frequency step from TX to RX
Calibration can be initiated manually or automatically before entering or after leaving RX or TX.
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Typical RSSI_offset Values
TA = 25°C, VCC = 3 V (unless otherwise noted) (1)
RSSI_OFFSET (dB)
DATA RATE (kBaud)
(1)
433 MHz
868 MHz
1.2
74
74
38.4
74
74
250
74
74
500
74
74
All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 49).
0
0
250kBaud
1.2kBaud
-20
RSSI Readout [dBm]
RSSI Readout [dBm]
-20
38.4kBaud
-40
-60
-80
-100
500kBaud
-40
-60
-80
-100
-120
-120
-100
-80
-60
-40
Input Pow er [dBm ]
-20
0
-120
-120
-100
-80
-60
-40
-20
0
Input Pow er [dBm ]
Figure 26. Typical RSSI Value vs Input Power Level for Different Data Rates at 868 MHz
86
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C19
Copyright © 2009–2013, Texas Instruments Incorporated
C11
C10
DVCC
VCORE
R2
TCK
TEST/SBWTCK
CC430F61xx
34
35
36
37
38
39
40
41
42
43
44
45
46
47
C9
C8
VDD
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
15
14
13
12
11
10
9
8
7
6
5
4
3
2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
C20
TMS
RF_XIN
RF_XOUT
AVCC_RF
AVCC_RF
RF_P
RF_N
AVCC_RF
AVCC_RF
R_BIAS
GUARD
TDO
TDI/TCLK
R1
C21
26MHz
AVDD
(JTAG / SBW signals)
C22
C4
C5
C1
C6
C2
C7
C3
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
required by ETSI.)
C16
C17
C18
L1
L2
L4
C23
C24
C25
C26
L3
C27
L5
L6
C28
L7
C29
SMA STRAIGHT JACK, SMT
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DVCC
VDD
C14
AVCC
C12
AVSS
C15
DVCC
C13
VDD
nRST/NMI/SBWTDIO
AVDD
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APPLICATION CIRCUIT
For a complete reference design including layout see the CC430 Wireless Development Tools and related
documentation [MSP430 Hardware Tools User's Guide (SLAU278)].
Figure 27. Typical Application Circuit CC430F61xx
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87
C19
C11
VDD
C10
DVCC
VCORE
C12
C13
C14
C15
R2
C20
31
26
11
C9
C8
VDD
25
12
13 14 15 16 17 18 19 20 21 22 23 24
27
28
9
10
29
8
30
32
5
6
7
34
33
3
4
CC430F51xx
35
AVSS
2
TEST/SBWTCK
48 47 46 45 44 43 42 41 40 39 38 37
36
TCK
1
DVCC
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AVCC
VDD
nRST/NMI/SBWTDIO
AVDD
TMS
88
DVCC
RF_XIN
RF_XOUT
AVCC_RF
AVCC_RF
RF_P
RF_N
AVCC_RF
AVCC_RF
R_BIAS
GUARD
TDO
TDI/TCLK
C21
C16
C17
C18
R1
C22
C4
C5
C1
C6
C2
(May be added close to the respective pins
to reduce emissions at 5GHz to levels
required by ETSI.)
26MHz
AVDD
(JTAG / SBW signals)
C7
C3
L1
L2
L4
C23
C24
C25
C26
L3
C27
L5
L6
C28
L7
C29
SMA STRAIGHT JACK, SMT
CC430F613x
CC430F612x
CC430F513x
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For a complete reference design including layout see the CC430 Wireless Development Tools and related
documentation [MSP430 Hardware Tools User's Guide (SLAU278)].
Figure 28. Typical Application Circuit CC430F51xx
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ECCN 5E002 TSPA - Technology / Software Publicly Available
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 49. Bill of Materials
Components
(1)
(2)
For 315 MHz
For 433 MHz
For 868, 915 MHz
Comment
C1,3,4,5,7,9,11,13,15
100 nF
Decoupling capacitors
C8,10,12,14
10 µF
Decoupling capacitors
C2,6,16,17,18
2 pF
Decoupling capacitors
C19
470 nF
VCORE capacitor
C20
2.2 nF
RST decoupling cap
(optimized for SBW)
C21,22
27 pF
Load capacitors for
26 MHz crystal (1)
R1
56 kΩ
R_BIAS (±1% required)
R2
47 kΩ
RST pullup
L1,2
Capacitors: 220 pF
0.016 µH
0.012 µH
L3,4
0.033 µH
0.027 µH
0.018 µH
L5
0.033 µH
0.047 µH
0.015 µH
L6
dnp (2)
dnp (2)
0.0022 µH
L7
0.033 µH
0.051 µH
0.015 µH
(2)
C23
dnp
2.7 pF
1 pF
C24
220 pF
220 pF
100 pF
C25
6.8 pF
3.9 pF
1.5 pF
C26
6.8 pF
3.9 pF
1.5 pF
C27
220 pF
220 pF
1.5 pF
C28
10 pF
4.7 pF
8.2 pF
C29
220 pF
220 pF
1.5 pF
The load capacitance CL seen by the crystal is CL = 1/((1/C21)+(1/C22)) + Cparasitic. The parasitic capacitance Cparasitic includes pin
capacitance and PCB stray capacitance. It can be typically estimated to be approximately 2.5 pF.
dnp = do not populate
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
S18...S22
(n/a CC430F513x)
LCDS18...LCDS22
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
to Port Mapping
P1.0/P1MAP0(/S18)
P1.1/P1MAP1(/S19)
P1.2/P1MAP2(/S20)
P1.3/P1MAP3(/S21)
P1.4/P1MAP4(/S22)
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
CC430F513x devices don't provide LCD functionality on port P1 pins.
90
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Table 50. Port P1 (P1.0 to P1.4) Pin Functions
CONTROL BITS/SIGNALS (1)
PIN NAME (P1.x)
P1.0/P1MAP/S18
x
0
FUNCTION
P1.0 (I/O)
Mapped secondary digital function - see Table 10
Output driver and input Schmitt trigger disabled
S18 (not available on CC430F513x)
P1.1/P1MAP1/S19
1
P1.1 (I/O)
Mapped secondary digital function - see Table 10
P1.2/P1MAP2/S20
2
3
4
X
0
1
≤ 30 (3)
0
X
1
= 31
0
0; 1 (3)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
X
1
= 31
0
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
P1.2 (I/O)
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S22 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
P1.3 (I/O)
0; 1
(3)
1
≤ 30
0
(3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S21 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S22 (not available on CC430F513x)
X
X
X
1
P1.4 (I/O)
Mapped secondary digital function - see Table 10
(1)
(2)
(3)
0
I: 0; O: 1
S19 (not available on CC430F513x)
Mapped secondary digital function - see Table 10
P1.4/P1MAP4/S22
LCDS19...
22 (2)
P1SEL.x
Output driver and input Schmitt trigger disabled
Mapped secondary digital function - see Table 10
P1.3/P1MAP3/S21
P1MAPx
P1DIR.x
X = don't care
LCDSx not available in CC430F513x.
According to mapped function - see Table 10.
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Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
to LCD_B
(n/a CC430F513x)
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.5/P1MAP5(/R23)
P1.6/P1MAP6(/R13)
P1.7/P1MAP7(/R03)
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
to Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
CC430F513x devices don't provide LCD functionality on port P1 pins.
Table 51. Port P1 (P1.5 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.5/P1MAP5/R23
x
5
FUNCTION
P1.5 (I/O)
Mapped secondary digital function - see Table 10
R23 (3) (not available on CC430F513x)
P1.6/P1MAP6/R13/
LCDREF
6
P1.6 (I/O)
Mapped secondary digital function - see Table 10
R13/LCDREF (3) (not available on CC430F513x)
P1.7/P1MAP7/R03
7
P1.7 (I/O)
Mapped secondary digital function - see Table 10
R03 (3) (not available on CC430F513x)
(1)
(2)
(3)
92
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
I: 0; O: 1
0
P1MAPx
X
0; 1 (2)
1
≤ 30 (2)
X
1
= 31
I: 0; O: 1
0
X
0; 1 (2)
1
≤ 30 (2)
X
1
= 31
I: 0; O: 1
0
X
0; 1 (2)
1
≤ 30 (2)
X
1
= 31
X = don't care
According to mapped function - see Table 10.
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P2, P2.0 to P2.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.0/P2MAP0/CB0(/A0)
P2.1/P2MAP2/CB1(/A1)
P2.2/P2MAP2/CB2(/A2)
P2.3/P2MAP3/CB3(/A3)
Bus
Keeper
EN
to Port Mapping
1
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
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Set
Interrupt
Edge
Select
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Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
Pad Logic
to/from Reference
(n/a CC430F612x)
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.4/P2MAP4/CB4(/A4/VREF-/VeREF-)
P2.5/P2MAP5/CB5(/A5/VREF+/VeRF+)
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
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Interrupt
Edge
Select
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
(n/a CC430F513x)
INCHx = x
To Comparator_B
(n/a CC430F513x)
from Comparator_B
CBPD.x
(n/a CC430F513x)
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.6/P2MAP6(/CB6/A6)
P2.7/P2MAP7(/CB7/A7)
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
CC430F513x devices don't provide analog functionality on port P2.6 and P2.7 pins.
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Table 52. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/P2MAP0/CB0
(/A0)
P2.1/P2MAP1/CB1
(/A1)
x
0
CONTROL BITS/SIGNALS (1)
FUNCTION
P2DIR.x
P2SEL.x
I: 0; O: 1
0; 1 (2)
A0 (not available on CC430F612x) (3)
CB0 (4)
P2.0 (I/O)
Mapped secondary digital function - see Table 10
1
P2.1 (I/O)
Mapped secondary digital function - see Table 10
A1 (not available on CC430F612x) (3)
CB1 (4)
P2.2/P2MAP2/CB2
(/A2)
2
P2.2 (I/O)
Mapped secondary digital function - see Table 10
A2 (not available on CC430F612x)
(3)
CB2 (4)
P2.3/P2MAP3/CB3
(/A3)
3
P2.3 (I/O)
Mapped secondary digital function - see Table 10
A3 (not available on CC430F612x)
(3)
CB3 (4)
P2.4/P2MAP4/CB4
(/A4/VREF-/VeREF-)
P2.5/P2MAP5/CB5
(/A5/VREF+/VeREF+)
P2.6/P2MAP6(/CB6)
(/A6)
4
P2.4 (I/O)
Mapped secondary digital function - see Table 10
5
96
0
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
X
X
X
1
I: 0; O: 1
0
X
0; 1
(2)
1
≤ 30
0
(2)
0
= 31
X
CB4 (4)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
A5/VREF+/VeREF+ (not available on CC430F612x) (3)
X
1
= 31
X
CB5 (4)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
X
1
= 31
X
P2.5 (I/O)
P2.6 (I/O)
CB6 (not available on CC430F513x) (4)
(1)
(2)
(3)
(4)
X
1
1
Mapped secondary digital function - see Table 10
7
0
X
A6 (not available on CC430F612x and
CC430F513x) (3)
P2.7/P2MAP7(/CB7)
(/A7)
CBPD.x
A4/VREF-/VeREF- (not available on CC430F612x) (3)
Mapped secondary digital function - see Table 10
6
P2MAPx
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (2)
1
≤ 30 (2)
0
A7 (not available on CC430F612x and
CC430F513x) (3)
X
1
= 31
X
CB7 (not available on CC430F513x) (4)
X
X
X
1
P2.7 (I/O)
Mapped secondary digital function - see Table 10
X = don't care
According to mapped function - see Table 10.
Setting P2SEL.x bit together with P2MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
S10...S17
(n/a CC430F513x)
LCDS10...LCDS17
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
to Port Mapping
1
D
Bus
Keeper
P3.0/P3MAP0(/S10)
P3.1/P3MAP1(/S11)
P3.2/P3MAP2(/S12)
P3.3/P3MAP3(/S13)
P3.4/P3MAP4(/S14)
P3.5/P3MAP5(/S15)
P3.6/P3MAP6(/S16)
P3.7/P3MAP7(/S17)
CC430F513x devices don't provide LCD functionality on port P3 pins.
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CC430F612x
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Table 53. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS/SIGNALS (1)
PIN NAME (P3.x)
P3.0/P3MAP0/S10
x
0
FUNCTION
P3.0 (I/O)
Mapped secondary digital function - see Table 10
Output driver and input Schmitt trigger disabled
S10 (not available on CC430F513x)
P3.1/P3MAP1/S11
1
P3.1 (I/O)
Mapped secondary digital function - see Table 10
P3.2/P3MAP7/S12
2
3
4
5
98
0
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
0
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
P3.2 (I/O)
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S12 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
P3.3 (I/O)
0; 1
(3)
1
≤ 30
0
(3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S13 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S14 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
X
1
= 31
0
P3.4 (I/O)
P3.5 (I/O)
P3.6 (I/O)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S16 (not available on CC430F513x)
X
X
X
1
I: 0; O: 1
0
X
0
0; 1 (3)
1
≤ 30 (3)
0
P3.7 (I/O)
Mapped secondary digital function - see Table 10
(1)
(2)
(3)
= 31
= 31
Mapped secondary digital function - see Table 10
7
1
1
S15 (not available on CC430F513x)
P3.7/P3MAP7/S17
0
X
X
Output driver and input Schmitt trigger disabled
6
0
≤ 30 (3)
X
Mapped secondary digital function - see Table 10
P3.6/P3MAP6/S16
X
1
0; 1 (3)
X
Mapped secondary digital function - see Table 10
P3.5/P3MAP5/S15
0
I: 0; O: 1
S11 (not available on CC430F513x)
Mapped secondary digital function - see Table 10
P3.4/P3MAP4/S14
LCDS10...
17 (2)
P3SEL.x
Output driver and input Schmitt trigger disabled
Mapped secondary digital function - see Table 10
P3.3/P3MAP3/S13
P3MAPx
P3DIR.x
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S17 (not available on CC430F513x)
X
X
X
1
X = don't care
LCDSx not available in CC430F513x.
According to mapped function - see Table 10.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S2...S9
LCDS2...LCDS9
Pad Logic
P4REN.x
P4DIR.x
0
0
DVSS
1
0
DVCC
1
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
Not Used
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
D
Copyright © 2009–2013, Texas Instruments Incorporated
Bus
Keeper
P4.0/S2
P4.1/S3
P4.2/S4
P4.3/S5
P4.4/S6
P4.5/S7
P4.6/S8
P4.7/S9
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CC430F612x
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Table 54. Port P4 (P4.0 to P4.7) Pin Functions (CC430F613x and CC430F612x only)
PIN NAME (P4.x)
P4.0/P4MAP0/S2
P4.1/P4MAP1/S3
x
0
1
FUNCTION
P4.0 (I/O)
2
3
P4.5/P4MAP5/S7
P4.6/P4MAP6/S8
4
5
6
0
0
1
0
DVSS
1
1
0
S2
X
X
1
P4.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.2 (I/O)
7
100
X
1
0
0
0
1
0
1
1
0
S4
X
X
1
I: 0; O: 1
0
0
0
1
0
P4.3 (I/O)
DVSS
1
1
0
S5
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P4.4 (I/O)
P4.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S7
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S8
P4.7/P4MAP7/S9
LCDS2...7
0
N/A
P4.4/P4MAP4/S6
P4SEL.x
I: 0; O: 1
N/A
P4.3/P4MAP3/S5
P4DIR.x
N/A
S3
P4.2/P4MAP7/S4
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S9
X
X
1
X = don't care
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P5, P5.0, Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.0
P5DIR.0
DVSS
0
DVCC
1
1
0
1
P5OUT.0
0
Module X OUT
1
P5DS.x
0: Low drive
1: High drive
P5SEL.0
P5.0/XIN
P5IN.0
EN
Module X IN
Bus
Keeper
D
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CC430F612x
CC430F513x
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Port P5, P5.1, Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.1
P5DIR.1
DVSS
0
DVCC
1
1
0
1
P5OUT.1
0
Module X OUT
1
P5.1/XOUT
P5DS.x
0: Low drive
1: High drive
P5SEL.0
XT1BYPASS
P5IN.1
Bus
Keeper
EN
Module X IN
D
Table 55. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/XIN
P5.1/XOUT
(1)
(2)
(3)
102
x
0
1
FUNCTION
P5.0 (I/O)
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.0
P5SEL.1
XT1BYPASS
I: 0; O: 1
0
X
X
XIN crystal mode (2)
X
1
X
0
XIN bypass mode (2)
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P5.1 (I/O) (3)
X
1
X
1
P5.1 (I/O)
X = don't care
Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal
mode or bypass mode.
Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as
general-purpose I/O.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S0(P5.2)/S1(P5.3)/S23(P5.4)
LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4)
Pad Logic
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
DVSS
1
P5.2/S0
P5.3/S1
P5.4/S23
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Not Used
D
Table 56. Port P5 (P5.2 to P5.3) Pin Functions (CC430F613x and CC430F612x only)
PIN NAME (P5.x)
P5.2/S0
x
2
FUNCTION
P5.2 (I/O)
N/A
P5.3/S1
(1)
3
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
LCDS0...1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S0
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
X
X
1
P5.3 (I/O)
X = don't care
Table 57. Port P5 (P5.4) Pin Functions (CC430F613x and CC430F612x only)
PIN NAME (P5.x)
P5.4/S23
(1)
x
4
FUNCTION
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
LCDS23
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S23
X
X
1
P5.4 (I/O)
X = don't care
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Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S24(P5.5)/S25(P5.6)/S26(P5.7)
LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7)
COM3(P5.5)/COM2(P5.6)/COM1(P5.7)
Pad Logic
P5REN.x
DVSS
0
DVCC
1
1
P5DIR.x
P5OUT.x
P5.5/COM3/S24
P5.6/COM2/S25
P5.7/COM1/S26
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
Table 58. Port P5 (P5.5 to P5.7) Pin Functions (CC430F613x and CC430F612x only)
PIN NAME (P5.x)
P5.5/COM3/S24
P5.6/COM2/S25
P5.7/COM1/S26
(1)
(2)
104
x
5
6
7
FUNCTION
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
P5.5 (I/O)
I: 0; O: 1
0
LCDS24...26
0
COM3 (2)
X
1
X
S24 (2)
X
0
1
P5.6 (I/O)
I: 0; O: 1
0
0
COM2 (2)
X
1
X
S25 (2)
X
0
1
P5.7 (I/O)
I: 0; O: 1
0
0
COM1 (2)
X
1
X
S26 (2)
X
0
1
X = don't care
Setting P5SEL.x bit disables the output driver as well as the input Schmitt trigger.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.x
0: Low drive
1: High drive
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
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CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Table 59. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS/
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
(2)
I: 0; O: 1
PJ.1 (I/O) (2)
I: 0; O: 1
PJ.0 (I/O)
TDO (3)
PJ.1/TDI/TCLK
1
X
TDI/TCLK (3)
PJ.2/TMS
2
PJ.2 (I/O)
TMS (3)
PJ.3/TCK
3
(1)
(2)
(3)
(4)
106
X
I: 0; O: 1
(4)
PJ.3 (I/O)
TCK (3)
(4)
(2)
X
(2)
I: 0; O: 1
(4)
X
X = don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
Device Descriptor Structures
Table 60 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F613x and
CC430F513x device types.
Table 61 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F612x device types.
Table 60. Device Descriptor Table (CC430F613x and CC430F513x)
Info Block
Die Record
ADC12
Calibration
REF
Calibration
Description
Address
Size
bytes
'F6137
'F6135
'F5137
'F5135
'F5133
Value
Value
Value
Value
Value
06h
Info length
01A00h
1
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
61h
61h
51h
51h
51h
Device ID
01A05h
1
37h
35h
37h
35h
33h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
ADC12 Calibration
Tag
01A14h
1
11h
11h
11h
11h
11h
ADC12 Calibration
length
01A15h
1
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
ADC 1.5V
Reference
Temp. Sensor
30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
ADC 1.5V
Reference
Temp. Sensor
85°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
ADC 2.0V
Reference
Temp. Sensor
30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
ADC 2.0V
Reference
Temp. Sensor
85°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
ADC 2.5V
Reference
Temp. Sensor
30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
ADC 2.5V
Reference
Temp. Sensor
85°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
REF Calibration
Tag
01A26h
1
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
1
06h
06h
06h
06h
06h
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Table 60. Device Descriptor Table (CC430F613x and CC430F513x) (continued)
Peripheral
Descriptor
(PD)
Description
Address
Size
bytes
'F6137
'F6135
'F5137
'F5135
'F5133
Value
Value
Value
Value
Value
1.5V Reference
Factor
01A28h
2
per unit
per unit
per unit
per unit
per unit
2.0V Reference
Factor
01A2Ah
2
per unit
per unit
per unit
per unit
per unit
2.5V Reference
Factor
01A2Ch
2
per unit
per unit
per unit
per unit
per unit
Peripheral
Descriptor Tag
01A2Eh
1
02h
02h
02h
02h
02h
Peripheral
Descriptor Length
01A2Fh
1
57h
57h
55h
55h
55h
Peripheral
Descriptors
01A30h
PD
Length
...
...
...
...
...
Table 61. Device Descriptor Table (CC430F612x)
Info Block
Die Record
Empty Descriptor
REF Calibration
Peripheral
Descriptor (PD)
108
Description
Address
Size
bytes
'F6127
'F6126
'F6125
Value
Value
Value
06h
Info length
01A00h
1
06h
06h
CRC length
01A01h
1
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
Device ID
01A04h
1
61h
61h
61h
Device ID
01A05h
1
27h
26h
25h
Hardware revision
01A06h
1
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
Empty Tag
01A14h
1
05h
05h
05h
Empty Tag Length
01A15h
1
10h
10h
10h
01A16h
16
undefined
undefined
undefined
REF Calibration Tag
01A26h
1
12h
12h
12h
REF Calibration length
01A27h
1
06h
06h
06h
1.5V Reference Factor
01A28h
2
per unit
per unit
per unit
2.0V Reference Factor
01A2Ah
2
per unit
per unit
per unit
2.5V Reference Factor
01A2Ch
2
per unit
per unit
per unit
Peripheral Descriptor Tag
01A2Eh
1
02h
02h
02h
Peripheral Descriptor
Length
01A2Fh
1
55h
55h
55h
Peripheral Descriptors
01A30h
PD Length
...
...
...
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
www.ti.com
CC430F613x
CC430F612x
CC430F513x
SLAS554G – MAY 2009 – REVISED FEBRUARY 2013
REVISION HISTORY
REVISION
DESCRIPTION
SLAS554
Product Preview data sheet release
SLAS554A
Product Preview data sheet updated with electrical parameters
SLAS554B
Production Data release data sheet for CC430F51xx devices. CC430F61xx devices are Product Preview.
SLAS554C
Production Data release data sheet for CC430F61xx devices.
SLAS554D
Added correct termination of LCDCAP/R33 if not used.
Corrected unit in Frequency Synthesizer Characteristics from "ms" to "µs".
SLAS554E
Removed RFRXIFG (14) and RFTXIFG (15) from DMA Trigger Assignments table
Corrected USCI control register location in Peripheral File Map.
Changed Tstg maximum limit from 105°C to 150°C in Absolute Maximum Ratings.
Replaced values for "Hardware revision" and "Firmware revision" in Device Descriptor Tables with "per unit".
SLAS554F
Table 4, Corrected USCI signal names for pins 5 and 6 (descriptions unchanged).
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage, ADC12 linearity
parameter test conditions revised.
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage, linearity parameters with internal reference
added.
SLAS554G
Table 12, Changed SYSRSTIV interrupt event at 1Ch to Reserved.
Recommended Operating Conditions, Added test conditions for typical characteristics.
Recommended Operating Conditions, Added note regarding relationship between SVS and MIN VCC.
DCO Frequency, Added note (1).
Flash Memory, Changed IERASE and IMERASE values.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
109
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
CC430F5133IRGZ
ACTIVE
VQFN
RGZ
48
52
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CC430F5133IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5133
CC430F5133IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5133
CC430F5135IRGZ
ACTIVE
VQFN
RGZ
48
52
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5135IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5135IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5135
CC430F5137IRGZ
ACTIVE
VQFN
RGZ
48
52
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F5137IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F5137IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430
F5137
CC430F6125IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6125
CC430F6125IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6125
CC430F6126IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6126
CC430F6126IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6126
CC430F6127IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6127
CC430F6127IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6127
CC430F6135IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6135
CC430F6135IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6135
Addendum-Page 1
CC430
F5133
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Aug-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
CC430F6137IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6137
CC430F6137IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC430F6137
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CC430F5133IRGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F5133IRGZT
VQFN
RGZ
48
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F5135IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F5135IRGZT
VQFN
RGZ
48
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F5137IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F5137IRGZT
VQFN
RGZ
48
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CC430F6125IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
CC430F6126IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
CC430F6127IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
CC430F6135IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
CC430F6137IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC430F5133IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
CC430F5133IRGZT
VQFN
RGZ
48
250
336.6
336.6
28.6
CC430F5135IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
CC430F5135IRGZT
VQFN
RGZ
48
250
336.6
336.6
28.6
CC430F5137IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
CC430F5137IRGZT
VQFN
RGZ
48
250
336.6
336.6
28.6
CC430F6125IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
CC430F6126IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
CC430F6127IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
CC430F6135IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
CC430F6137IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
Pack Materials-Page 2
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