AZM AZP53 Low phase noise sine wave to lvpecl buffer/divider Datasheet

ARIZONA MICROTEK, INC.
AZP51
AZP52
AZP53
AZP54
Low Phase Noise Sine Wave to LVPECL Buffer/Divider
PACKAGE AVAILABILITY
FEATURES
BASE PART
•
•
•
•
•
•
3.0 to 3.6 V
operating supply
range
LVPECL Outputs
Optimized for
Low Phase Noise
Frequency Input
to >650 MHz
QFN 8 (1.5x1.5
mm), SC-70 or
SOT-23 packages
All Packages
Green / RoHS
Compliant / Lead
(Pb) Free
AZP51 (÷1)
AZP52 (÷2)
AZP53 (÷1,2)
AZP54 (÷1)
1
2
3
PACKAGE
SC-70 Green /
RoHS Compliant /
Lead (Pb) Free
SC-70 Green /
RoHS Compliant /
Lead (Pb) Free
QFN 8 (1.5x1.5
mm) Green / RoHS
Compliant / Lead
(Pb) Free
SOT-23 Green /
RoHS Compliant /
Lead (Pb) Free
PART NO.
MARKING
NOTES
AZP51SG
D1G
<Date Code>
1,2
AZP52SG
D2G
<Date Code>
1,2
AZP53PG
D3
<Date Code>
1,3
AZP54VG
D4G
<Date Code>
1,2
Add R1 at end of part number for 7 inch , R2 for 13 inch Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
See Arizona Microtek web site for date code format.
DESCRIPTION
The AZP51 series is a family of sine wave to LVPECL buffers optimized for low phase noise. It is particularly
useful in converting sine wave crystal or SAW based oscillator outputs into LVPECL outputs. The IC also includes
an optional ÷2 function to provide better frequency range coverage when using a SAW based oscillator.
The D input is internally biased to VDD/2. A sine wave input of at least 750 mv p-p ensures the AZP51 series
meets its AC specifications. This input (D) should be capacitively coupled from the oscillator stage to ensure best
output duty cycle.
AZP51S (÷1), AZP52S (÷2), SC-70 Package
The Enable input (EN) is active high with an internal pullup. When EN is high or not connected, the outputs
(Q,Q̄) are active. When EN is low, Q and Q̄ are disabled in a high impedance (tri-state) condition. Refer to the
Functional Operation table for more information.
AZP53P (÷1, ÷2), QFN 8 1.5x1.5mm Package
The EN_SEL input selects the operational polarity for the EN input, so the EN input can be set to active high or
active low operation. Refer to the Functional Operation table for more information.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414
www.azmicrotek.com
AZP51
AZP52
AZP53
AZP54
AZP54V (÷1) SOT-23 Package
The Enable input (EN) is active low with an internal pulldown. When EN is low or not connected, the outputs
(Q,Q̄) are active. When EN is high, Q and Q̄ are disabled in a high impedance (tri-state) condition. Refer to the
Functional Operation table for more information.
BLOCK DIAGRAMS
AZP52
AZP51
AZP53
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AZP54
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AZP51
AZP52
AZP53
AZP54
SIGNAL DESCRIPTION
PIN/PAD
D
Q,Q̄
EN
DIV_SEL
EN_SEL
VDD
GND
FUNCTION
Sine or LVCMOS Input
LVPECL Outputs
Output Enable
Divide Select (AZP53 only)
Enable Select (AZP53 only)
Positive Supply
Negative Supply (Ground)
DIV-SEL OPERATION
PART
NUMBER
AZP51
AZP54
AZP52
DIV-SEL
DIVIDE
RATIO
-2
÷1
-2
NC1,L
AZP53
H
1. NC – no connection
2. Internally connected
÷2
÷1
÷2
FUNCTIONAL OPERATION
PART
NUMBER
INPUTS
7
EN_SEL
AZP51
AZP52
-
2
EN
D
NC1, H
L
H
X5
L
H
X5
L
H
X5
L
H
X5
L
NC1, H
NC1, L
H
AZP53
L
NC1, H
L
AZP54
1.
2.
3.
4.
5.
6.
7.
8.
-2
NC1, L
EN LOGIC
Active High
4
EN
PULLUP/
PULLDOWN
Pullup
Active Low3
Pulldown
Active High4
Pullup
Active Low3
Pulldown
H
NC – no connection
Internally tied
Active Low: Output enabled when EN low, Tri-state when EN high
Active High: Output enabled when EN high, Tri-state when EN low
X – Don’t care
Z – High impedance
EN_SEL input has an internal pullup resistor
÷1 modes only
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OUTPUTS
Q
Q̄
L8
H8
Z6
L8
H8
Z6
L8
H8
Z6
L
H
Z6
H8
L8
Z6
H8
L8
Z6
H8
L8
Z6
H
L
Z6
AZP51
AZP52
AZP53
AZP54
AZP53P
QFN 8, 1.5x1.5 mm
TOP VIEW
AZP51S, 52S
SC-70
TOP VIEW
AZP54V
SOT-23
TOP VIEW
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AZP51
AZP52
AZP53
AZP54
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VDD
VI
TA
TSTG
Characteristic
Power Supply
Input Voltage
Operating Temperature Range
Storage Temperature Range
Rating
0 to +5.5
-0.5 to VDD+0.5
-40 to +85
-65 to +150
Unit
Vdc
Vdc
°C
°C
DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40 to 85 C)
Symbol
Characteristic
VOH
Output HIGH Voltage1
VOL
Output LOW Voltage1
Conditions
-40 C
25 C
85 C
-40 C
25 C
85 C
VDD = 3.3V
VDD = 3.3V
Min
Typ
Max
Unit
2.05
2.05
2.05
1.365
1.430
1.490
2.415
2.480
2.540
1.615
1.680
1.740
-10
10
μA
0.8
V
V
V
VIH
Output Leakage Current, Tristate2
High Level Input Voltage
VIL
Low Level Input Voltage
RPU
RPD
RP
Pullup Resistor4
Pulldown Resistor4
Pullup/Pulldown Resistor5
RBIAS
Bias Resistor
IDD
Power Supply Current
22
35
mA
1.
Specified with outputs terminated through 50Ω resistors to VDD - 2V or Thevenin equivalent.
2.
Measured at Q/Q̄ pins.
3.
See functional tables for Disable state definition.
4.
AZP53 only.
5.
See functional operation table for pullup/pulldown mode selection.
IZ
EN=Disable3
4
EN_SEL
DIV_SEL4
EN
EN_SEL
DIV_SEL
EN
D Input to Internal
VDD/2 Reference
2.0
V
50k
50k
50k
Ω
Ω
Ω
10k
Ω
AC Characteristics (VDD = 3.0V to 3.6V, TA = -40 to 85 C)
Symbol
Characteristic
Unit
Min
Max
Output Rise/Fall1
0.25
0.7
ns
tr / t f
(20% - 80%)
Maximum Input
650
MHz
fMAX
Frequency – Sine wave2
1,3,6
Propagation Delay
tpd
1.0
3.0
ns
D to Q/Q̄
1,4
Enable
200
ns
ten
EN to Q/Q̄
1,5
Disable
80
ns
tdis
EN to Q/Q̄
dBc/
Phase Noise1,3
-158
nP
10 MHz offset
Hz
1.
Specified with outputs terminated through 50Ω resistors to VCC - 2V or Thevenin equivalent.
2.
750 mv p-p sine wave, AC coupled to D input.
3.
155 MHz 750 mv p-p sine wave input.
4.
EN asserted (enabled) to Q/Q̄ outputs producing specified VOH & VOL levels.
5.
EN deasserted (disabled) to Q/Q̄ outputs ≤ VOL min.
6.
Measured from 50% D to 50% Q/Q̄.
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AZP51
AZP52
AZP53
AZP54
PACKAGE DIAGRAM
P – QFN 8 1.5x1.5mm
Note: All dimensions are in mm
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AZP51
AZP52
AZP53
AZP54
2.467
D
e
e
Gauge Plane
Seating Plane
PACKAGE DIAGRAM
S – SC-70 6L
L
HE C
L
E
C
L
A2
C
b
A1
A
SYMBOL
MIN
MAX
E
1.15
1.35
D
1.85
2.25
HE
2.00
2.30
A
0.80
1.00
A2
0.80
0.91
A1
0.00
0.09
e
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONS ARE EXCLUSIVE OF
MOLD FLASH & GATE BURR.
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0.65 BSC
b
0.15
0.30
c
0.08
0.25
L
0.21
0.41
AZP51
AZP52
AZP53
AZP54
PACKAGE DIAGRAM
V – SOT-23 6L
2.90±0.100
C
L
0.950
TYP.
NOTE:
1. Dimensions and tolerances are as per ANSI
Y14.5M, 1982.
2. Package surface to be matte finish VDI 11~13.
3. Die is facing up for mold. Die is facing
down for trim/form, ie. reverse trim/form.
1.60±0.100
2.80±0.200
5
0.950
TYP.
5
C
L
4. The footlength measuring is based on the
gauge plane method.
5. Dimension are exclusive of mold flash and gate burr.
6. Dimension are exclusive of solder plating.
0.350(MIN)
0.500(MAX)
(6 PLCS)
1.15±0.150
10° TYP.
(2 plcs)
SEATING PLANE
0.05(MIN)
0.15(MAX)
10° TYP.
(2 plcs)
10° TYP.
(2 plcs)
0°~3°
0.20 BSC
Gauge Plane
0.127
5
10° TYP.
(2 plcs)
December 2009 * REV - 2
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0.45
±0.10
AZP51
AZP52
AZP53
AZP54
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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